linux/platform_data/xilinx-ll-temac.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __LINUX_XILINX_LL_TEMAC_H
0003 #define __LINUX_XILINX_LL_TEMAC_H
0004
0005 #include <linux/if_ether.h>
0006 #include <linux/phy.h>
0007 #include <linux/spinlock.h>
0008
0009 struct ll_temac_platform_data {
0010     bool txcsum;        /* Enable/disable TX checksum */
0011     bool rxcsum;        /* Enable/disable RX checksum */
0012     u8 mac_addr[ETH_ALEN];  /* MAC address (6 bytes) */
0013     /* Clock frequency for input to MDIO clock generator */
0014     u32 mdio_clk_freq;
0015     unsigned long long mdio_bus_id; /* Unique id for MDIO bus */
0016     int phy_addr;       /* Address of the PHY to connect to */
0017     phy_interface_t phy_interface; /* PHY interface mode */
0018     bool reg_little_endian; /* Little endian TEMAC register access  */
0019     bool dma_little_endian; /* Little endian DMA register access  */
0020     /* Pre-initialized mutex to use for synchronizing indirect
0021      * register access.  When using both interfaces of a single
0022      * TEMAC IP block, the same mutex should be passed here, as
0023      * they share the same DCR bus bridge.
0024      */
0025     spinlock_t *indirect_lock;
0026     /* DMA channel control setup */
0027     u8 tx_irq_timeout;  /* TX Interrupt Delay Time-out */
0028     u8 tx_irq_count;    /* TX Interrupt Coalescing Threshold Count */
0029     u8 rx_irq_timeout;  /* RX Interrupt Delay Time-out */
0030     u8 rx_irq_count;    /* RX Interrupt Coalescing Threshold Count */
0031 };
0032
0033 #endif /* __LINUX_XILINX_LL_TEMAC_H */