platform_data/x86/clk-pmc-atom.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Intel Atom platform clocks for BayTrail and CherryTrail SoC.
0004  *
0005  * Copyright (C) 2016, Intel Corporation
0006  * Author: Irina Tirdea <irina.tirdea@intel.com>
0007  */
0008
0009 #ifndef __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
0010 #define __PLATFORM_DATA_X86_CLK_PMC_ATOM_H
0011
0012 /**
0013  * struct pmc_clk - PMC platform clock configuration
0014  *
0015  * @name:   identified, typically pmc_plt_clk_<x>, x=[0..5]
0016  * @freq:   in Hz, 19.2MHz  and 25MHz (Baytrail only) supported
0017  * @parent_name: one of 'xtal' or 'osc'
0018  */
0019 struct pmc_clk {
0020     const char *name;
0021     unsigned long freq;
0022     const char *parent_name;
0023 };
0024
0025 /**
0026  * struct pmc_clk_data - common PMC clock configuration
0027  *
0028  * @base:   PMC clock register base offset
0029  * @clks:   pointer to set of registered clocks, typically 0..5
0030  * @critical:   flag to indicate if firmware enabled pmc_plt_clks
0031  *      should be marked as critial or not
0032  */
0033 struct pmc_clk_data {
0034     void __iomem *base;
0035     const struct pmc_clk *clks;
0036     bool critical;
0037 };
0038
0039 #endif /* __PLATFORM_DATA_X86_CLK_PMC_ATOM_H */