linux/platform_data/video-pxafb.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Support for the xscale frame buffer.
0004  *
0005  *  Author:     Jean-Frederic Clere
0006  *  Created:    Sep 22, 2003
0007  *  Copyright:  jfclere@sinix.net
0008  */
0009
0010 #include <linux/fb.h>
0011
0012 /*
0013  * Supported LCD connections
0014  *
0015  * bits 0 - 3: for LCD panel type:
0016  *
0017  *   STN  - for passive matrix
0018  *   DSTN - for dual scan passive matrix
0019  *   TFT  - for active matrix
0020  *
0021  * bits 4 - 9 : for bus width
0022  * bits 10-17 : for AC Bias Pin Frequency
0023  * bit     18 : for output enable polarity
0024  * bit     19 : for pixel clock edge
0025  * bit     20 : for output pixel format when base is RGBT16
0026  */
0027 #define LCD_CONN_TYPE(_x)   ((_x) & 0x0f)
0028 #define LCD_CONN_WIDTH(_x)  (((_x) >> 4) & 0x1f)
0029
0030 #define LCD_TYPE_MASK       0xf
0031 #define LCD_TYPE_UNKNOWN    0
0032 #define LCD_TYPE_MONO_STN   1
0033 #define LCD_TYPE_MONO_DSTN  2
0034 #define LCD_TYPE_COLOR_STN  3
0035 #define LCD_TYPE_COLOR_DSTN 4
0036 #define LCD_TYPE_COLOR_TFT  5
0037 #define LCD_TYPE_SMART_PANEL    6
0038 #define LCD_TYPE_MAX        7
0039
0040 #define LCD_MONO_STN_4BPP   ((4  << 4) | LCD_TYPE_MONO_STN)
0041 #define LCD_MONO_STN_8BPP   ((8  << 4) | LCD_TYPE_MONO_STN)
0042 #define LCD_MONO_DSTN_8BPP  ((8  << 4) | LCD_TYPE_MONO_DSTN)
0043 #define LCD_COLOR_STN_8BPP  ((8  << 4) | LCD_TYPE_COLOR_STN)
0044 #define LCD_COLOR_DSTN_16BPP    ((16 << 4) | LCD_TYPE_COLOR_DSTN)
0045 #define LCD_COLOR_TFT_8BPP  ((8  << 4) | LCD_TYPE_COLOR_TFT)
0046 #define LCD_COLOR_TFT_16BPP ((16 << 4) | LCD_TYPE_COLOR_TFT)
0047 #define LCD_COLOR_TFT_18BPP ((18 << 4) | LCD_TYPE_COLOR_TFT)
0048 #define LCD_SMART_PANEL_8BPP    ((8  << 4) | LCD_TYPE_SMART_PANEL)
0049 #define LCD_SMART_PANEL_16BPP   ((16 << 4) | LCD_TYPE_SMART_PANEL)
0050 #define LCD_SMART_PANEL_18BPP   ((18 << 4) | LCD_TYPE_SMART_PANEL)
0051
0052 #define LCD_AC_BIAS_FREQ(x) (((x) & 0xff) << 10)
0053 #define LCD_BIAS_ACTIVE_HIGH    (0 << 18)
0054 #define LCD_BIAS_ACTIVE_LOW (1 << 18)
0055 #define LCD_PCLK_EDGE_RISE  (0 << 19)
0056 #define LCD_PCLK_EDGE_FALL  (1 << 19)
0057 #define LCD_ALTERNATE_MAPPING   (1 << 20)
0058
0059 /*
0060  * This structure describes the machine which we are running on.
0061  * It is set in linux/arch/arm/mach-pxa/machine_name.c and used in the probe routine
0062  * of linux/drivers/video/pxafb.c
0063  */
0064 struct pxafb_mode_info {
0065     u_long      pixclock;
0066
0067     u_short     xres;
0068     u_short     yres;
0069
0070     u_char      bpp;
0071     u_int       cmap_greyscale:1,
0072             depth:8,
0073             transparency:1,
0074             unused:22;
0075
0076     /* Parallel Mode Timing */
0077     u_char      hsync_len;
0078     u_char      left_margin;
0079     u_char      right_margin;
0080
0081     u_char      vsync_len;
0082     u_char      upper_margin;
0083     u_char      lower_margin;
0084     u_char      sync;
0085
0086     /* Smart Panel Mode Timing - see PXA27x DM 7.4.15.0.3 for details
0087      * Note:
0088      * 1. all parameters in nanosecond (ns)
0089      * 2. a0cs{rd,wr}_set_hld are controlled by the same register bits
0090      *    in pxa27x and pxa3xx, initialize them to the same value or
0091      *    the larger one will be used
0092      * 3. same to {rd,wr}_pulse_width
0093      *
0094      * 4. LCD_PCLK_EDGE_{RISE,FALL} controls the L_PCLK_WR polarity
0095      * 5. sync & FB_SYNC_HOR_HIGH_ACT controls the L_LCLK_A0
0096      * 6. sync & FB_SYNC_VERT_HIGH_ACT controls the L_LCLK_RD
0097      */
0098     unsigned    a0csrd_set_hld; /* A0 and CS Setup/Hold Time before/after L_FCLK_RD */
0099     unsigned    a0cswr_set_hld; /* A0 and CS Setup/Hold Time before/after L_PCLK_WR */
0100     unsigned    wr_pulse_width; /* L_PCLK_WR pulse width */
0101     unsigned    rd_pulse_width; /* L_FCLK_RD pulse width */
0102     unsigned    cmd_inh_time;   /* Command Inhibit time between two writes */
0103     unsigned    op_hold_time;   /* Output Hold time from L_FCLK_RD negation */
0104 };
0105
0106 struct pxafb_mach_info {
0107     struct pxafb_mode_info *modes;
0108     unsigned int num_modes;
0109
0110     unsigned int    lcd_conn;
0111     unsigned long   video_mem_size;
0112
0113     u_int       fixed_modes:1,
0114             cmap_inverse:1,
0115             cmap_static:1,
0116             acceleration_enabled:1,
0117             unused:28;
0118
0119     /* The following should be defined in LCCR0
0120      *      LCCR0_Act or LCCR0_Pas          Active or Passive
0121      *      LCCR0_Sngl or LCCR0_Dual        Single/Dual panel
0122      *      LCCR0_Mono or LCCR0_Color       Mono/Color
0123      *      LCCR0_4PixMono or LCCR0_8PixMono (in mono single mode)
0124      *      LCCR0_DMADel(Tcpu) (optional)   DMA request delay
0125      *
0126      * The following should not be defined in LCCR0:
0127      *      LCCR0_OUM, LCCR0_BM, LCCR0_QDM, LCCR0_DIS, LCCR0_EFM
0128      *      LCCR0_IUM, LCCR0_SFM, LCCR0_LDM, LCCR0_ENB
0129      */
0130     u_int       lccr0;
0131     /* The following should be defined in LCCR3
0132      *      LCCR3_OutEnH or LCCR3_OutEnL    Output enable polarity
0133      *      LCCR3_PixRsEdg or LCCR3_PixFlEdg Pixel clock edge type
0134      *      LCCR3_Acb(X)                    AB Bias pin frequency
0135      *      LCCR3_DPC (optional)            Double Pixel Clock mode (untested)
0136      *
0137      * The following should not be defined in LCCR3
0138      *      LCCR3_HSP, LCCR3_VSP, LCCR0_Pcd(x), LCCR3_Bpp
0139      */
0140     u_int       lccr3;
0141     /* The following should be defined in LCCR4
0142      *  LCCR4_PAL_FOR_0 or LCCR4_PAL_FOR_1 or LCCR4_PAL_FOR_2
0143      *
0144      * All other bits in LCCR4 should be left alone.
0145      */
0146     u_int       lccr4;
0147     void (*pxafb_backlight_power)(int);
0148     void (*pxafb_lcd_power)(int, struct fb_var_screeninfo *);
0149     void (*smart_update)(struct fb_info *);
0150 };
0151
0152 void pxa_set_fb_info(struct device *, struct pxafb_mach_info *);
0153 unsigned long pxafb_get_hsync_time(struct device *dev);
0154
0155 /* smartpanel related */
0156 #define SMART_CMD_A0             (0x1 << 8)
0157 #define SMART_CMD_READ_STATUS_REG    (0x0 << 9)
0158 #define SMART_CMD_READ_FRAME_BUFFER ((0x0 << 9) | SMART_CMD_A0)
0159 #define SMART_CMD_WRITE_COMMAND      (0x1 << 9)
0160 #define SMART_CMD_WRITE_DATA        ((0x1 << 9) | SMART_CMD_A0)
0161 #define SMART_CMD_WRITE_FRAME       ((0x2 << 9) | SMART_CMD_A0)
0162 #define SMART_CMD_WAIT_FOR_VSYNC     (0x3 << 9)
0163 #define SMART_CMD_NOOP           (0x4 << 9)
0164 #define SMART_CMD_INTERRUPT      (0x5 << 9)
0165
0166 #define SMART_CMD(x)    (SMART_CMD_WRITE_COMMAND | ((x) & 0xff))
0167 #define SMART_DAT(x)    (SMART_CMD_WRITE_DATA | ((x) & 0xff))
0168
0169 /* SMART_DELAY() is introduced for software controlled delay primitive which
0170  * can be inserted between command sequences, unused command 0x6 is used here
0171  * and delay ranges from 0ms ~ 255ms
0172  */
0173 #define SMART_CMD_DELAY     (0x6 << 9)
0174 #define SMART_DELAY(ms)     (SMART_CMD_DELAY | ((ms) & 0xff))
0175
0176 #ifdef CONFIG_FB_PXA_SMARTPANEL
0177 extern int pxafb_smart_queue(struct fb_info *info, uint16_t *cmds, int);
0178 extern int pxafb_smart_flush(struct fb_info *info);
0179 #else
0180 static inline int pxafb_smart_queue(struct fb_info *info,
0181                     uint16_t *cmds, int n)
0182 {
0183     return 0;
0184 }
0185
0186 static inline int pxafb_smart_flush(struct fb_info *info)
0187 {
0188     return 0;
0189 }
0190 #endif