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0008 #define OMAP3_HS_USB_PORTS 3
0009
0010 enum usbhs_omap_port_mode {
0011 OMAP_USBHS_PORT_MODE_UNUSED,
0012 OMAP_EHCI_PORT_MODE_PHY,
0013 OMAP_EHCI_PORT_MODE_TLL,
0014 OMAP_EHCI_PORT_MODE_HSIC,
0015 OMAP_OHCI_PORT_MODE_PHY_6PIN_DATSE0,
0016 OMAP_OHCI_PORT_MODE_PHY_6PIN_DPDM,
0017 OMAP_OHCI_PORT_MODE_PHY_3PIN_DATSE0,
0018 OMAP_OHCI_PORT_MODE_PHY_4PIN_DPDM,
0019 OMAP_OHCI_PORT_MODE_TLL_6PIN_DATSE0,
0020 OMAP_OHCI_PORT_MODE_TLL_6PIN_DPDM,
0021 OMAP_OHCI_PORT_MODE_TLL_3PIN_DATSE0,
0022 OMAP_OHCI_PORT_MODE_TLL_4PIN_DPDM,
0023 OMAP_OHCI_PORT_MODE_TLL_2PIN_DATSE0,
0024 OMAP_OHCI_PORT_MODE_TLL_2PIN_DPDM
0025 };
0026
0027 struct usbtll_omap_platform_data {
0028 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
0029 };
0030
0031 struct ehci_hcd_omap_platform_data {
0032 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
0033 int reset_gpio_port[OMAP3_HS_USB_PORTS];
0034 struct regulator *regulator[OMAP3_HS_USB_PORTS];
0035 unsigned phy_reset:1;
0036 };
0037
0038 struct ohci_hcd_omap_platform_data {
0039 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
0040 unsigned es2_compatibility:1;
0041 };
0042
0043 struct usbhs_omap_platform_data {
0044 int nports;
0045 enum usbhs_omap_port_mode port_mode[OMAP3_HS_USB_PORTS];
0046 int reset_gpio_port[OMAP3_HS_USB_PORTS];
0047 struct regulator *regulator[OMAP3_HS_USB_PORTS];
0048
0049 struct ehci_hcd_omap_platform_data *ehci_data;
0050 struct ohci_hcd_omap_platform_data *ohci_data;
0051
0052
0053 unsigned single_ulpi_bypass:1;
0054 unsigned es2_compatibility:1;
0055 unsigned phy_reset:1;
0056 };
0057
0058
0059
0060 struct omap_musb_board_data {
0061 u8 interface_type;
0062 u8 mode;
0063 u16 power;
0064 unsigned extvbus:1;
0065 void (*set_phy_power)(u8 on);
0066 void (*clear_irq)(void);
0067 void (*set_mode)(u8 mode);
0068 void (*reset)(void);
0069 };
0070
0071 enum musb_interface {
0072 MUSB_INTERFACE_ULPI,
0073 MUSB_INTERFACE_UTMI
0074 };