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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 
0003 /*
0004  * Copyright (C) 2009 Samsung Electronics Ltd.
0005  *  Jaswinder Singh <jassi.brar@samsung.com>
0006  */
0007 
0008 #ifndef __SPI_S3C64XX_H
0009 #define __SPI_S3C64XX_H
0010 
0011 #include <linux/dmaengine.h>
0012 
0013 struct platform_device;
0014 
0015 /**
0016  * struct s3c64xx_spi_csinfo - ChipSelect description
0017  * @fb_delay: Slave specific feedback delay.
0018  *            Refer to FB_CLK_SEL register definition in SPI chapter.
0019  *
0020  * This is per SPI-Slave Chipselect information.
0021  * Allocate and initialize one in machine init code and make the
0022  * spi_board_info.controller_data point to it.
0023  */
0024 struct s3c64xx_spi_csinfo {
0025     u8 fb_delay;
0026 };
0027 
0028 /**
0029  * struct s3c64xx_spi_info - SPI Controller defining structure
0030  * @src_clk_nr: Clock source index for the CLK_CFG[SPI_CLKSEL] field.
0031  * @num_cs: Number of CS this controller emulates.
0032  * @cfg_gpio: Configure pins for this SPI controller.
0033  */
0034 struct s3c64xx_spi_info {
0035     int src_clk_nr;
0036     int num_cs;
0037     bool no_cs;
0038     int (*cfg_gpio)(void);
0039 };
0040 
0041 /**
0042  * s3c64xx_spi_set_platdata - SPI Controller configure callback by the board
0043  *              initialization code.
0044  * @src_clk_nr: Clock the SPI controller is to use to generate SPI clocks.
0045  * @num_cs: Number of elements in the 'cs' array.
0046  *
0047  * Call this from machine init code for each SPI Controller that
0048  * has some chips attached to it.
0049  */
0050 extern void s3c64xx_spi0_set_platdata(int src_clk_nr, int num_cs);
0051 
0052 /* defined by architecture to configure gpio */
0053 extern int s3c64xx_spi0_cfg_gpio(void);
0054 
0055 extern struct s3c64xx_spi_info s3c64xx_spi0_pdata;
0056 #endif /*__SPI_S3C64XX_H */