linux/platform_data/si5351.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Si5351A/B/C programmable clock generator platform_data.
0004  */
0005
0006 #ifndef __LINUX_PLATFORM_DATA_SI5351_H__
0007 #define __LINUX_PLATFORM_DATA_SI5351_H__
0008
0009 /**
0010  * enum si5351_pll_src - Si5351 pll clock source
0011  * @SI5351_PLL_SRC_DEFAULT: default, do not change eeprom config
0012  * @SI5351_PLL_SRC_XTAL: pll source clock is XTAL input
0013  * @SI5351_PLL_SRC_CLKIN: pll source clock is CLKIN input (Si5351C only)
0014  */
0015 enum si5351_pll_src {
0016     SI5351_PLL_SRC_DEFAULT = 0,
0017     SI5351_PLL_SRC_XTAL = 1,
0018     SI5351_PLL_SRC_CLKIN = 2,
0019 };
0020
0021 /**
0022  * enum si5351_multisynth_src - Si5351 multisynth clock source
0023  * @SI5351_MULTISYNTH_SRC_DEFAULT: default, do not change eeprom config
0024  * @SI5351_MULTISYNTH_SRC_VCO0: multisynth source clock is VCO0
0025  * @SI5351_MULTISYNTH_SRC_VCO1: multisynth source clock is VCO1/VXCO
0026  */
0027 enum si5351_multisynth_src {
0028     SI5351_MULTISYNTH_SRC_DEFAULT = 0,
0029     SI5351_MULTISYNTH_SRC_VCO0 = 1,
0030     SI5351_MULTISYNTH_SRC_VCO1 = 2,
0031 };
0032
0033 /**
0034  * enum si5351_clkout_src - Si5351 clock output clock source
0035  * @SI5351_CLKOUT_SRC_DEFAULT: default, do not change eeprom config
0036  * @SI5351_CLKOUT_SRC_MSYNTH_N: clkout N source clock is multisynth N
0037  * @SI5351_CLKOUT_SRC_MSYNTH_0_4: clkout N source clock is multisynth 0 (N<4)
0038  *                                or 4 (N>=4)
0039  * @SI5351_CLKOUT_SRC_XTAL: clkout N source clock is XTAL
0040  * @SI5351_CLKOUT_SRC_CLKIN: clkout N source clock is CLKIN (Si5351C only)
0041  */
0042 enum si5351_clkout_src {
0043     SI5351_CLKOUT_SRC_DEFAULT = 0,
0044     SI5351_CLKOUT_SRC_MSYNTH_N = 1,
0045     SI5351_CLKOUT_SRC_MSYNTH_0_4 = 2,
0046     SI5351_CLKOUT_SRC_XTAL = 3,
0047     SI5351_CLKOUT_SRC_CLKIN = 4,
0048 };
0049
0050 /**
0051  * enum si5351_drive_strength - Si5351 clock output drive strength
0052  * @SI5351_DRIVE_DEFAULT: default, do not change eeprom config
0053  * @SI5351_DRIVE_2MA: 2mA clock output drive strength
0054  * @SI5351_DRIVE_4MA: 4mA clock output drive strength
0055  * @SI5351_DRIVE_6MA: 6mA clock output drive strength
0056  * @SI5351_DRIVE_8MA: 8mA clock output drive strength
0057  */
0058 enum si5351_drive_strength {
0059     SI5351_DRIVE_DEFAULT = 0,
0060     SI5351_DRIVE_2MA = 2,
0061     SI5351_DRIVE_4MA = 4,
0062     SI5351_DRIVE_6MA = 6,
0063     SI5351_DRIVE_8MA = 8,
0064 };
0065
0066 /**
0067  * enum si5351_disable_state - Si5351 clock output disable state
0068  * @SI5351_DISABLE_DEFAULT: default, do not change eeprom config
0069  * @SI5351_DISABLE_LOW: CLKx is set to a LOW state when disabled
0070  * @SI5351_DISABLE_HIGH: CLKx is set to a HIGH state when disabled
0071  * @SI5351_DISABLE_FLOATING: CLKx is set to a FLOATING state when
0072  *              disabled
0073  * @SI5351_DISABLE_NEVER: CLKx is NEVER disabled
0074  */
0075 enum si5351_disable_state {
0076     SI5351_DISABLE_DEFAULT = 0,
0077     SI5351_DISABLE_LOW,
0078     SI5351_DISABLE_HIGH,
0079     SI5351_DISABLE_FLOATING,
0080     SI5351_DISABLE_NEVER,
0081 };
0082
0083 /**
0084  * struct si5351_clkout_config - Si5351 clock output configuration
0085  * @clkout: clkout number
0086  * @multisynth_src: multisynth source clock
0087  * @clkout_src: clkout source clock
0088  * @pll_master: if true, clkout can also change pll rate
0089  * @pll_reset: if true, clkout can reset its pll
0090  * @drive: output drive strength
0091  * @rate: initial clkout rate, or default if 0
0092  */
0093 struct si5351_clkout_config {
0094     enum si5351_multisynth_src multisynth_src;
0095     enum si5351_clkout_src clkout_src;
0096     enum si5351_drive_strength drive;
0097     enum si5351_disable_state disable_state;
0098     bool pll_master;
0099     bool pll_reset;
0100     unsigned long rate;
0101 };
0102
0103 /**
0104  * struct si5351_platform_data - Platform data for the Si5351 clock driver
0105  * @clk_xtal: xtal input clock
0106  * @clk_clkin: clkin input clock
0107  * @pll_src: array of pll source clock setting
0108  * @clkout: array of clkout configuration
0109  */
0110 struct si5351_platform_data {
0111     enum si5351_pll_src pll_src[2];
0112     struct si5351_clkout_config clkout[8];
0113 };
0114
0115 #endif