linux/platform_data/sh_mmcif.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * platform data for eMMC driver
0004  *
0005  * Copyright (C) 2010 Renesas Solutions Corp.
0006  */
0007
0008 #ifndef LINUX_MMC_SH_MMCIF_H
0009 #define LINUX_MMC_SH_MMCIF_H
0010
0011 #include <linux/io.h>
0012 #include <linux/platform_device.h>
0013
0014 /*
0015  * MMCIF : CE_CLK_CTRL [19:16]
0016  * 1000 : Peripheral clock / 512
0017  * 0111 : Peripheral clock / 256
0018  * 0110 : Peripheral clock / 128
0019  * 0101 : Peripheral clock / 64
0020  * 0100 : Peripheral clock / 32
0021  * 0011 : Peripheral clock / 16
0022  * 0010 : Peripheral clock / 8
0023  * 0001 : Peripheral clock / 4
0024  * 0000 : Peripheral clock / 2
0025  * 1111 : Peripheral clock (sup_pclk set '1')
0026  */
0027
0028 struct sh_mmcif_plat_data {
0029     unsigned int        slave_id_tx;    /* embedded slave_id_[tr]x */
0030     unsigned int        slave_id_rx;
0031     u8          sup_pclk;   /* 1 :SH7757, 0: SH7724/SH7372 */
0032     unsigned long       caps;
0033     u32         ocr;
0034 };
0035
0036 #define MMCIF_CE_CMD_SET    0x00000000
0037 #define MMCIF_CE_ARG        0x00000008
0038 #define MMCIF_CE_ARG_CMD12  0x0000000C
0039 #define MMCIF_CE_CMD_CTRL   0x00000010
0040 #define MMCIF_CE_BLOCK_SET  0x00000014
0041 #define MMCIF_CE_CLK_CTRL   0x00000018
0042 #define MMCIF_CE_BUF_ACC    0x0000001C
0043 #define MMCIF_CE_RESP3      0x00000020
0044 #define MMCIF_CE_RESP2      0x00000024
0045 #define MMCIF_CE_RESP1      0x00000028
0046 #define MMCIF_CE_RESP0      0x0000002C
0047 #define MMCIF_CE_RESP_CMD12 0x00000030
0048 #define MMCIF_CE_DATA       0x00000034
0049 #define MMCIF_CE_INT        0x00000040
0050 #define MMCIF_CE_INT_MASK   0x00000044
0051 #define MMCIF_CE_HOST_STS1  0x00000048
0052 #define MMCIF_CE_HOST_STS2  0x0000004C
0053 #define MMCIF_CE_CLK_CTRL2  0x00000070
0054 #define MMCIF_CE_VERSION    0x0000007C
0055
0056 /* CE_BUF_ACC */
0057 #define BUF_ACC_DMAWEN      (1 << 25)
0058 #define BUF_ACC_DMAREN      (1 << 24)
0059 #define BUF_ACC_BUSW_32     (0 << 17)
0060 #define BUF_ACC_BUSW_16     (1 << 17)
0061 #define BUF_ACC_ATYP        (1 << 16)
0062
0063 /* CE_CLK_CTRL */
0064 #define CLK_ENABLE      (1 << 24) /* 1: output mmc clock */
0065 #define CLK_CLEAR       (0xf << 16)
0066 #define CLK_SUP_PCLK        (0xf << 16)
0067 #define CLKDIV_4        (1 << 16) /* mmc clock frequency.
0068                        * n: bus clock/(2^(n+1)) */
0069 #define CLKDIV_256      (7 << 16) /* mmc clock frequency. (see above) */
0070 #define SRSPTO_256      (2 << 12) /* resp timeout */
0071 #define SRBSYTO_29      (0xf << 8) /* resp busy timeout */
0072 #define SRWDTO_29       (0xf << 4) /* read/write timeout */
0073 #define SCCSTO_29       (0xf << 0) /* ccs timeout */
0074
0075 /* CE_VERSION */
0076 #define SOFT_RST_ON     (1 << 31)
0077 #define SOFT_RST_OFF        0
0078
0079 static inline u32 sh_mmcif_readl(void __iomem *addr, int reg)
0080 {
0081     return __raw_readl(addr + reg);
0082 }
0083
0084 static inline void sh_mmcif_writel(void __iomem *addr, int reg, u32 val)
0085 {
0086     __raw_writel(val, addr + reg);
0087 }
0088
0089 #define SH_MMCIF_BBS 512 /* boot block size */
0090
0091 static inline void sh_mmcif_boot_cmd_send(void __iomem *base,
0092                       unsigned long cmd, unsigned long arg)
0093 {
0094     sh_mmcif_writel(base, MMCIF_CE_INT, 0);
0095     sh_mmcif_writel(base, MMCIF_CE_ARG, arg);
0096     sh_mmcif_writel(base, MMCIF_CE_CMD_SET, cmd);
0097 }
0098
0099 static inline int sh_mmcif_boot_cmd_poll(void __iomem *base, unsigned long mask)
0100 {
0101     unsigned long tmp;
0102     int cnt;
0103
0104     for (cnt = 0; cnt < 1000000; cnt++) {
0105         tmp = sh_mmcif_readl(base, MMCIF_CE_INT);
0106         if (tmp & mask) {
0107             sh_mmcif_writel(base, MMCIF_CE_INT, tmp & ~mask);
0108             return 0;
0109         }
0110     }
0111
0112     return -1;
0113 }
0114
0115 static inline int sh_mmcif_boot_cmd(void __iomem *base,
0116                     unsigned long cmd, unsigned long arg)
0117 {
0118     sh_mmcif_boot_cmd_send(base, cmd, arg);
0119     return sh_mmcif_boot_cmd_poll(base, 0x00010000);
0120 }
0121
0122 static inline int sh_mmcif_boot_do_read_single(void __iomem *base,
0123                            unsigned int block_nr,
0124                            unsigned long *buf)
0125 {
0126     int k;
0127
0128     /* CMD13 - Status */
0129     sh_mmcif_boot_cmd(base, 0x0d400000, 0x00010000);
0130
0131     if (sh_mmcif_readl(base, MMCIF_CE_RESP0) != 0x0900)
0132         return -1;
0133
0134     /* CMD17 - Read */
0135     sh_mmcif_boot_cmd(base, 0x11480000, block_nr * SH_MMCIF_BBS);
0136     if (sh_mmcif_boot_cmd_poll(base, 0x00100000) < 0)
0137         return -1;
0138
0139     for (k = 0; k < (SH_MMCIF_BBS / 4); k++)
0140         buf[k] = sh_mmcif_readl(base, MMCIF_CE_DATA);
0141
0142     return 0;
0143 }
0144
0145 static inline int sh_mmcif_boot_do_read(void __iomem *base,
0146                     unsigned long first_block,
0147                     unsigned long nr_blocks,
0148                     void *buf)
0149 {
0150     unsigned long k;
0151     int ret = 0;
0152
0153     /* In data transfer mode: Set clock to Bus clock/4 (about 20Mhz) */
0154     sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
0155             CLK_ENABLE | CLKDIV_4 | SRSPTO_256 |
0156             SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
0157
0158     /* CMD9 - Get CSD */
0159     sh_mmcif_boot_cmd(base, 0x09806000, 0x00010000);
0160
0161     /* CMD7 - Select the card */
0162     sh_mmcif_boot_cmd(base, 0x07400000, 0x00010000);
0163
0164     /* CMD16 - Set the block size */
0165     sh_mmcif_boot_cmd(base, 0x10400000, SH_MMCIF_BBS);
0166
0167     for (k = 0; !ret && k < nr_blocks; k++)
0168         ret = sh_mmcif_boot_do_read_single(base, first_block + k,
0169                            buf + (k * SH_MMCIF_BBS));
0170
0171     return ret;
0172 }
0173
0174 static inline void sh_mmcif_boot_init(void __iomem *base)
0175 {
0176     /* reset */
0177     sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_ON);
0178     sh_mmcif_writel(base, MMCIF_CE_VERSION, SOFT_RST_OFF);
0179
0180     /* byte swap */
0181     sh_mmcif_writel(base, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
0182
0183     /* Set block size in MMCIF hardware */
0184     sh_mmcif_writel(base, MMCIF_CE_BLOCK_SET, SH_MMCIF_BBS);
0185
0186     /* Enable the clock, set it to Bus clock/256 (about 325Khz). */
0187     sh_mmcif_writel(base, MMCIF_CE_CLK_CTRL,
0188             CLK_ENABLE | CLKDIV_256 | SRSPTO_256 |
0189             SRBSYTO_29 | SRWDTO_29 | SCCSTO_29);
0190
0191     /* CMD0 */
0192     sh_mmcif_boot_cmd(base, 0x00000040, 0);
0193
0194     /* CMD1 - Get OCR */
0195     do {
0196         sh_mmcif_boot_cmd(base, 0x01405040, 0x40300000); /* CMD1 */
0197     } while ((sh_mmcif_readl(base, MMCIF_CE_RESP0) & 0x80000000)
0198          != 0x80000000);
0199
0200     /* CMD2 - Get CID */
0201     sh_mmcif_boot_cmd(base, 0x02806040, 0);
0202
0203     /* CMD3 - Set card relative address */
0204     sh_mmcif_boot_cmd(base, 0x03400040, 0x00010000);
0205 }
0206
0207 #endif /* LINUX_MMC_SH_MMCIF_H */