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0006 #ifndef _MTD_NAND_OMAP2_H
0007 #define _MTD_NAND_OMAP2_H
0008
0009 #include <linux/mtd/partitions.h>
0010 #include <linux/mod_devicetable.h>
0011
0012 #define GPMC_BCH_NUM_REMAINDER 8
0013
0014 enum nand_io {
0015 NAND_OMAP_PREFETCH_POLLED = 0,
0016 NAND_OMAP_POLLED,
0017 NAND_OMAP_PREFETCH_DMA,
0018 NAND_OMAP_PREFETCH_IRQ
0019 };
0020
0021 enum omap_ecc {
0022
0023
0024
0025
0026 OMAP_ECC_HAM1_CODE_SW = 0,
0027
0028
0029
0030
0031
0032 OMAP_ECC_HAM1_CODE_HW,
0033
0034 OMAP_ECC_BCH4_CODE_HW_DETECTION_SW,
0035
0036 OMAP_ECC_BCH4_CODE_HW,
0037
0038 OMAP_ECC_BCH8_CODE_HW_DETECTION_SW,
0039
0040 OMAP_ECC_BCH8_CODE_HW,
0041
0042 OMAP_ECC_BCH16_CODE_HW,
0043 };
0044
0045 struct gpmc_nand_regs {
0046 void __iomem *gpmc_nand_command;
0047 void __iomem *gpmc_nand_address;
0048 void __iomem *gpmc_nand_data;
0049 void __iomem *gpmc_prefetch_config1;
0050 void __iomem *gpmc_prefetch_config2;
0051 void __iomem *gpmc_prefetch_control;
0052 void __iomem *gpmc_prefetch_status;
0053 void __iomem *gpmc_ecc_config;
0054 void __iomem *gpmc_ecc_control;
0055 void __iomem *gpmc_ecc_size_config;
0056 void __iomem *gpmc_ecc1_result;
0057 void __iomem *gpmc_bch_result0[GPMC_BCH_NUM_REMAINDER];
0058 void __iomem *gpmc_bch_result1[GPMC_BCH_NUM_REMAINDER];
0059 void __iomem *gpmc_bch_result2[GPMC_BCH_NUM_REMAINDER];
0060 void __iomem *gpmc_bch_result3[GPMC_BCH_NUM_REMAINDER];
0061 void __iomem *gpmc_bch_result4[GPMC_BCH_NUM_REMAINDER];
0062 void __iomem *gpmc_bch_result5[GPMC_BCH_NUM_REMAINDER];
0063 void __iomem *gpmc_bch_result6[GPMC_BCH_NUM_REMAINDER];
0064 };
0065
0066 static const struct of_device_id omap_nand_ids[] = {
0067 { .compatible = "ti,omap2-nand", },
0068 { .compatible = "ti,am64-nand", },
0069 {},
0070 };
0071
0072 #endif