linux/platform_data/mtd-davinci.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * mach-davinci/nand.h
0004  *
0005  * Copyright © 2006 Texas Instruments.
0006  *
0007  * Ported to 2.6.23 Copyright © 2008 by
0008  *   Sander Huijsen <Shuijsen@optelecom-nkf.com>
0009  *   Troy Kisky <troy.kisky@boundarydevices.com>
0010  *   Dirk Behme <Dirk.Behme@gmail.com>
0011  *
0012  * --------------------------------------------------------------------------
0013  */
0014
0015 #ifndef __ARCH_ARM_DAVINCI_NAND_H
0016 #define __ARCH_ARM_DAVINCI_NAND_H
0017
0018 #include <linux/mtd/rawnand.h>
0019
0020 #define NANDFCR_OFFSET      0x60
0021 #define NANDFSR_OFFSET      0x64
0022 #define NANDF1ECC_OFFSET    0x70
0023
0024 /* 4-bit ECC syndrome registers */
0025 #define NAND_4BIT_ECC_LOAD_OFFSET   0xbc
0026 #define NAND_4BIT_ECC1_OFFSET       0xc0
0027 #define NAND_4BIT_ECC2_OFFSET       0xc4
0028 #define NAND_4BIT_ECC3_OFFSET       0xc8
0029 #define NAND_4BIT_ECC4_OFFSET       0xcc
0030 #define NAND_ERR_ADD1_OFFSET        0xd0
0031 #define NAND_ERR_ADD2_OFFSET        0xd4
0032 #define NAND_ERR_ERRVAL1_OFFSET     0xd8
0033 #define NAND_ERR_ERRVAL2_OFFSET     0xdc
0034
0035 /* NOTE:  boards don't need to use these address bits
0036  * for ALE/CLE unless they support booting from NAND.
0037  * They're used unless platform data overrides them.
0038  */
0039 #define MASK_ALE        0x08
0040 #define MASK_CLE        0x10
0041
0042 struct davinci_nand_pdata {     /* platform_data */
0043     uint32_t        mask_ale;
0044     uint32_t        mask_cle;
0045
0046     /*
0047      * 0-indexed chip-select number of the asynchronous
0048      * interface to which the NAND device has been connected.
0049      *
0050      * So, if you have NAND connected to CS3 of DA850, you
0051      * will pass '1' here. Since the asynchronous interface
0052      * on DA850 starts from CS2.
0053      */
0054     uint32_t        core_chipsel;
0055
0056     /* for packages using two chipselects */
0057     uint32_t        mask_chipsel;
0058
0059     /* board's default static partition info */
0060     struct mtd_partition    *parts;
0061     unsigned        nr_parts;
0062
0063     /* none  == NAND_ECC_ENGINE_TYPE_NONE (strongly *not* advised!!)
0064      * soft  == NAND_ECC_ENGINE_TYPE_SOFT
0065      * else  == NAND_ECC_ENGINE_TYPE_ON_HOST, according to ecc_bits
0066      *
0067      * All DaVinci-family chips support 1-bit hardware ECC.
0068      * Newer ones also support 4-bit ECC, but are awkward
0069      * using it with large page chips.
0070      */
0071     enum nand_ecc_engine_type engine_type;
0072     enum nand_ecc_placement ecc_placement;
0073     u8          ecc_bits;
0074
0075     /* e.g. NAND_BUSWIDTH_16 */
0076     unsigned        options;
0077     /* e.g. NAND_BBT_USE_FLASH */
0078     unsigned        bbt_options;
0079
0080     /* Main and mirror bbt descriptor overrides */
0081     struct nand_bbt_descr   *bbt_td;
0082     struct nand_bbt_descr   *bbt_md;
0083
0084     /* Access timings */
0085     struct davinci_aemif_timing *timing;
0086 };
0087
0088 #endif  /* __ARCH_ARM_DAVINCI_NAND_H */