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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Information for the Marvell Armada MMP camera
0004  */
0005 
0006 #include <media/v4l2-mediabus.h>
0007 
0008 enum dphy3_algo {
0009     DPHY3_ALGO_DEFAULT = 0,
0010     DPHY3_ALGO_PXA910,
0011     DPHY3_ALGO_PXA2128
0012 };
0013 
0014 struct mmp_camera_platform_data {
0015     enum v4l2_mbus_type bus_type;
0016     int mclk_src;   /* which clock source the MCLK derives from */
0017     int mclk_div;   /* Clock Divider Value for MCLK */
0018     /*
0019      * MIPI support
0020      */
0021     int dphy[3];        /* DPHY: CSI2_DPHY3, CSI2_DPHY5, CSI2_DPHY6 */
0022     enum dphy3_algo dphy3_algo; /* algos for calculate CSI2_DPHY3 */
0023     int lane;       /* ccic used lane number; 0 means DVP mode */
0024     int lane_clk;
0025 };