linux/platform_data/gpmc-omap.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * OMAP GPMC Platform data
0004  *
0005  * Copyright (C) 2014 Texas Instruments, Inc. - https://www.ti.com
0006  *  Roger Quadros <rogerq@ti.com>
0007  */
0008
0009 #ifndef _GPMC_OMAP_H_
0010 #define _GPMC_OMAP_H_
0011
0012 /* Maximum Number of Chip Selects */
0013 #define GPMC_CS_NUM     8
0014
0015 /* bool type time settings */
0016 struct gpmc_bool_timings {
0017     bool cycle2cyclediffcsen;
0018     bool cycle2cyclesamecsen;
0019     bool we_extra_delay;
0020     bool oe_extra_delay;
0021     bool adv_extra_delay;
0022     bool cs_extra_delay;
0023     bool time_para_granularity;
0024 };
0025
0026 /*
0027  * Note that all values in this struct are in nanoseconds except sync_clk
0028  * (which is in picoseconds), while the register values are in gpmc_fck cycles.
0029  */
0030 struct gpmc_timings {
0031     /* Minimum clock period for synchronous mode (in picoseconds) */
0032     u32 sync_clk;
0033
0034     /* Chip-select signal timings corresponding to GPMC_CS_CONFIG2 */
0035     u32 cs_on;      /* Assertion time */
0036     u32 cs_rd_off;      /* Read deassertion time */
0037     u32 cs_wr_off;      /* Write deassertion time */
0038
0039     /* ADV signal timings corresponding to GPMC_CONFIG3 */
0040     u32 adv_on;     /* Assertion time */
0041     u32 adv_rd_off;     /* Read deassertion time */
0042     u32 adv_wr_off;     /* Write deassertion time */
0043     u32 adv_aad_mux_on; /* ADV assertion time for AAD */
0044     u32 adv_aad_mux_rd_off; /* ADV read deassertion time for AAD */
0045     u32 adv_aad_mux_wr_off; /* ADV write deassertion time for AAD */
0046
0047     /* WE signals timings corresponding to GPMC_CONFIG4 */
0048     u32 we_on;      /* WE assertion time */
0049     u32 we_off;     /* WE deassertion time */
0050
0051     /* OE signals timings corresponding to GPMC_CONFIG4 */
0052     u32 oe_on;      /* OE assertion time */
0053     u32 oe_off;     /* OE deassertion time */
0054     u32 oe_aad_mux_on;  /* OE assertion time for AAD */
0055     u32 oe_aad_mux_off; /* OE deassertion time for AAD */
0056
0057     /* Access time and cycle time timings corresponding to GPMC_CONFIG5 */
0058     u32 page_burst_access;  /* Multiple access word delay */
0059     u32 access;     /* Start-cycle to first data valid delay */
0060     u32 rd_cycle;       /* Total read cycle time */
0061     u32 wr_cycle;       /* Total write cycle time */
0062
0063     u32 bus_turnaround;
0064     u32 cycle2cycle_delay;
0065
0066     u32 wait_monitoring;
0067     u32 clk_activation;
0068
0069     /* The following are only on OMAP3430 */
0070     u32 wr_access;      /* WRACCESSTIME */
0071     u32 wr_data_mux_bus;    /* WRDATAONADMUXBUS */
0072
0073     struct gpmc_bool_timings bool_timings;
0074 };
0075
0076 /* Device timings in picoseconds */
0077 struct gpmc_device_timings {
0078     u32 t_ceasu;    /* address setup to CS valid */
0079     u32 t_avdasu;   /* address setup to ADV valid */
0080     /* XXX: try to combine t_avdp_r & t_avdp_w. Issue is
0081      * of tusb using these timings even for sync whilst
0082      * ideally for adv_rd/(wr)_off it should have considered
0083      * t_avdh instead. This indirectly necessitates r/w
0084      * variations of t_avdp as it is possible to have one
0085      * sync & other async
0086      */
0087     u32 t_avdp_r;   /* ADV low time (what about t_cer ?) */
0088     u32 t_avdp_w;
0089     u32 t_aavdh;    /* address hold time */
0090     u32 t_oeasu;    /* address setup to OE valid */
0091     u32 t_aa;   /* access time from ADV assertion */
0092     u32 t_iaa;  /* initial access time */
0093     u32 t_oe;   /* access time from OE assertion */
0094     u32 t_ce;   /* access time from CS asertion */
0095     u32 t_rd_cycle; /* read cycle time */
0096     u32 t_cez_r;    /* read CS deassertion to high Z */
0097     u32 t_cez_w;    /* write CS deassertion to high Z */
0098     u32 t_oez;  /* OE deassertion to high Z */
0099     u32 t_weasu;    /* address setup to WE valid */
0100     u32 t_wpl;  /* write assertion time */
0101     u32 t_wph;  /* write deassertion time */
0102     u32 t_wr_cycle; /* write cycle time */
0103
0104     u32 clk;
0105     u32 t_bacc; /* burst access valid clock to output delay */
0106     u32 t_ces;  /* CS setup time to clk */
0107     u32 t_avds; /* ADV setup time to clk */
0108     u32 t_avdh; /* ADV hold time from clk */
0109     u32 t_ach;  /* address hold time from clk */
0110     u32 t_rdyo; /* clk to ready valid */
0111
0112     u32 t_ce_rdyz;  /* XXX: description ?, or use t_cez instead */
0113     u32 t_ce_avd;   /* CS on to ADV on delay */
0114
0115     /* XXX: check the possibility of combining
0116      * cyc_aavhd_oe & cyc_aavdh_we
0117      */
0118     u8 cyc_aavdh_oe;/* read address hold time in cycles */
0119     u8 cyc_aavdh_we;/* write address hold time in cycles */
0120     u8 cyc_oe;  /* access time from OE assertion in cycles */
0121     u8 cyc_wpl; /* write deassertion time in cycles */
0122     u32 cyc_iaa;    /* initial access time in cycles */
0123
0124     /* extra delays */
0125     bool ce_xdelay;
0126     bool avd_xdelay;
0127     bool oe_xdelay;
0128     bool we_xdelay;
0129 };
0130
0131 #define GPMC_BURST_4            4   /* 4 word burst */
0132 #define GPMC_BURST_8            8   /* 8 word burst */
0133 #define GPMC_BURST_16           16  /* 16 word burst */
0134 #define GPMC_DEVWIDTH_8BIT      1   /* 8-bit device width */
0135 #define GPMC_DEVWIDTH_16BIT     2   /* 16-bit device width */
0136 #define GPMC_MUX_AAD            1   /* Addr-Addr-Data multiplex */
0137 #define GPMC_MUX_AD         2   /* Addr-Data multiplex */
0138
0139 struct gpmc_settings {
0140     bool burst_wrap;    /* enables wrap bursting */
0141     bool burst_read;    /* enables read page/burst mode */
0142     bool burst_write;   /* enables write page/burst mode */
0143     bool device_nand;   /* device is NAND */
0144     bool sync_read;     /* enables synchronous reads */
0145     bool sync_write;    /* enables synchronous writes */
0146     bool wait_on_read;  /* monitor wait on reads */
0147     bool wait_on_write; /* monitor wait on writes */
0148     u32 burst_len;      /* page/burst length */
0149     u32 device_width;   /* device bus width (8 or 16 bit) */
0150     u32 mux_add_data;   /* multiplex address & data */
0151     u32 wait_pin;       /* wait-pin to be used */
0152 };
0153
0154 /* Data for each chip select */
0155 struct gpmc_omap_cs_data {
0156     bool valid;         /* data is valid */
0157     bool is_nand;           /* device within this CS is NAND */
0158     struct gpmc_settings *settings;
0159     struct gpmc_device_timings *device_timings;
0160     struct gpmc_timings *gpmc_timings;
0161     struct platform_device *pdev;   /* device within this CS region */
0162     unsigned int pdata_size;
0163 };
0164
0165 struct gpmc_omap_platform_data {
0166     struct gpmc_omap_cs_data cs[GPMC_CS_NUM];
0167 };
0168
0169 #endif /* _GPMC_OMAP_H */