linux/platform_data/gpio-omap.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * OMAP GPIO handling defines and functions
0004  *
0005  * Copyright (C) 2003-2005 Nokia Corporation
0006  *
0007  * Written by Juha Yrjölä <juha.yrjola@nokia.com>
0008  */
0009
0010 #ifndef __ASM_ARCH_OMAP_GPIO_H
0011 #define __ASM_ARCH_OMAP_GPIO_H
0012
0013 #ifndef __ASSEMBLER__
0014 #include <linux/io.h>
0015 #include <linux/platform_device.h>
0016 #endif
0017
0018 #define OMAP1_MPUIO_BASE            0xfffb5000
0019
0020 /*
0021  * These are the omap15xx/16xx offsets. The omap7xx offset are
0022  * OMAP_MPUIO_ / 2 offsets below.
0023  */
0024 #define OMAP_MPUIO_INPUT_LATCH      0x00
0025 #define OMAP_MPUIO_OUTPUT       0x04
0026 #define OMAP_MPUIO_IO_CNTL      0x08
0027 #define OMAP_MPUIO_KBR_LATCH        0x10
0028 #define OMAP_MPUIO_KBC          0x14
0029 #define OMAP_MPUIO_GPIO_EVENT_MODE  0x18
0030 #define OMAP_MPUIO_GPIO_INT_EDGE    0x1c
0031 #define OMAP_MPUIO_KBD_INT      0x20
0032 #define OMAP_MPUIO_GPIO_INT     0x24
0033 #define OMAP_MPUIO_KBD_MASKIT       0x28
0034 #define OMAP_MPUIO_GPIO_MASKIT      0x2c
0035 #define OMAP_MPUIO_GPIO_DEBOUNCING  0x30
0036 #define OMAP_MPUIO_LATCH        0x34
0037
0038 #define OMAP34XX_NR_GPIOS       6
0039
0040 /*
0041  * OMAP1510 GPIO registers
0042  */
0043 #define OMAP1510_GPIO_DATA_INPUT    0x00
0044 #define OMAP1510_GPIO_DATA_OUTPUT   0x04
0045 #define OMAP1510_GPIO_DIR_CONTROL   0x08
0046 #define OMAP1510_GPIO_INT_CONTROL   0x0c
0047 #define OMAP1510_GPIO_INT_MASK      0x10
0048 #define OMAP1510_GPIO_INT_STATUS    0x14
0049 #define OMAP1510_GPIO_PIN_CONTROL   0x18
0050
0051 #define OMAP1510_IH_GPIO_BASE       64
0052
0053 /*
0054  * OMAP1610 specific GPIO registers
0055  */
0056 #define OMAP1610_GPIO_REVISION      0x0000
0057 #define OMAP1610_GPIO_SYSCONFIG     0x0010
0058 #define OMAP1610_GPIO_SYSSTATUS     0x0014
0059 #define OMAP1610_GPIO_IRQSTATUS1    0x0018
0060 #define OMAP1610_GPIO_IRQENABLE1    0x001c
0061 #define OMAP1610_GPIO_WAKEUPENABLE  0x0028
0062 #define OMAP1610_GPIO_DATAIN        0x002c
0063 #define OMAP1610_GPIO_DATAOUT       0x0030
0064 #define OMAP1610_GPIO_DIRECTION     0x0034
0065 #define OMAP1610_GPIO_EDGE_CTRL1    0x0038
0066 #define OMAP1610_GPIO_EDGE_CTRL2    0x003c
0067 #define OMAP1610_GPIO_CLEAR_IRQENABLE1  0x009c
0068 #define OMAP1610_GPIO_CLEAR_WAKEUPENA   0x00a8
0069 #define OMAP1610_GPIO_CLEAR_DATAOUT 0x00b0
0070 #define OMAP1610_GPIO_SET_IRQENABLE1    0x00dc
0071 #define OMAP1610_GPIO_SET_WAKEUPENA 0x00e8
0072 #define OMAP1610_GPIO_SET_DATAOUT   0x00f0
0073
0074 /*
0075  * OMAP7XX specific GPIO registers
0076  */
0077 #define OMAP7XX_GPIO_DATA_INPUT     0x00
0078 #define OMAP7XX_GPIO_DATA_OUTPUT    0x04
0079 #define OMAP7XX_GPIO_DIR_CONTROL    0x08
0080 #define OMAP7XX_GPIO_INT_CONTROL    0x0c
0081 #define OMAP7XX_GPIO_INT_MASK       0x10
0082 #define OMAP7XX_GPIO_INT_STATUS     0x14
0083
0084 /*
0085  * omap2+ specific GPIO registers
0086  */
0087 #define OMAP24XX_GPIO_REVISION      0x0000
0088 #define OMAP24XX_GPIO_SYSCONFIG     0x0010
0089 #define OMAP24XX_GPIO_IRQSTATUS1    0x0018
0090 #define OMAP24XX_GPIO_IRQSTATUS2    0x0028
0091 #define OMAP24XX_GPIO_IRQENABLE2    0x002c
0092 #define OMAP24XX_GPIO_IRQENABLE1    0x001c
0093 #define OMAP24XX_GPIO_WAKE_EN       0x0020
0094 #define OMAP24XX_GPIO_CTRL      0x0030
0095 #define OMAP24XX_GPIO_OE        0x0034
0096 #define OMAP24XX_GPIO_DATAIN        0x0038
0097 #define OMAP24XX_GPIO_DATAOUT       0x003c
0098 #define OMAP24XX_GPIO_LEVELDETECT0  0x0040
0099 #define OMAP24XX_GPIO_LEVELDETECT1  0x0044
0100 #define OMAP24XX_GPIO_RISINGDETECT  0x0048
0101 #define OMAP24XX_GPIO_FALLINGDETECT 0x004c
0102 #define OMAP24XX_GPIO_DEBOUNCE_EN   0x0050
0103 #define OMAP24XX_GPIO_DEBOUNCE_VAL  0x0054
0104 #define OMAP24XX_GPIO_CLEARIRQENABLE1   0x0060
0105 #define OMAP24XX_GPIO_SETIRQENABLE1 0x0064
0106 #define OMAP24XX_GPIO_CLEARWKUENA   0x0080
0107 #define OMAP24XX_GPIO_SETWKUENA     0x0084
0108 #define OMAP24XX_GPIO_CLEARDATAOUT  0x0090
0109 #define OMAP24XX_GPIO_SETDATAOUT    0x0094
0110
0111 #define OMAP4_GPIO_REVISION     0x0000
0112 #define OMAP4_GPIO_SYSCONFIG        0x0010
0113 #define OMAP4_GPIO_EOI          0x0020
0114 #define OMAP4_GPIO_IRQSTATUSRAW0    0x0024
0115 #define OMAP4_GPIO_IRQSTATUSRAW1    0x0028
0116 #define OMAP4_GPIO_IRQSTATUS0       0x002c
0117 #define OMAP4_GPIO_IRQSTATUS1       0x0030
0118 #define OMAP4_GPIO_IRQSTATUSSET0    0x0034
0119 #define OMAP4_GPIO_IRQSTATUSSET1    0x0038
0120 #define OMAP4_GPIO_IRQSTATUSCLR0    0x003c
0121 #define OMAP4_GPIO_IRQSTATUSCLR1    0x0040
0122 #define OMAP4_GPIO_IRQWAKEN0        0x0044
0123 #define OMAP4_GPIO_IRQWAKEN1        0x0048
0124 #define OMAP4_GPIO_IRQENABLE1       0x011c
0125 #define OMAP4_GPIO_WAKE_EN      0x0120
0126 #define OMAP4_GPIO_IRQSTATUS2       0x0128
0127 #define OMAP4_GPIO_IRQENABLE2       0x012c
0128 #define OMAP4_GPIO_CTRL         0x0130
0129 #define OMAP4_GPIO_OE           0x0134
0130 #define OMAP4_GPIO_DATAIN       0x0138
0131 #define OMAP4_GPIO_DATAOUT      0x013c
0132 #define OMAP4_GPIO_LEVELDETECT0     0x0140
0133 #define OMAP4_GPIO_LEVELDETECT1     0x0144
0134 #define OMAP4_GPIO_RISINGDETECT     0x0148
0135 #define OMAP4_GPIO_FALLINGDETECT    0x014c
0136 #define OMAP4_GPIO_DEBOUNCENABLE    0x0150
0137 #define OMAP4_GPIO_DEBOUNCINGTIME   0x0154
0138 #define OMAP4_GPIO_CLEARIRQENABLE1  0x0160
0139 #define OMAP4_GPIO_SETIRQENABLE1    0x0164
0140 #define OMAP4_GPIO_CLEARWKUENA      0x0180
0141 #define OMAP4_GPIO_SETWKUENA        0x0184
0142 #define OMAP4_GPIO_CLEARDATAOUT     0x0190
0143 #define OMAP4_GPIO_SETDATAOUT       0x0194
0144
0145 #define OMAP_MAX_GPIO_LINES     192
0146
0147 #define OMAP_MPUIO(nr)      (OMAP_MAX_GPIO_LINES + (nr))
0148 #define OMAP_GPIO_IS_MPUIO(nr)  ((nr) >= OMAP_MAX_GPIO_LINES)
0149
0150 #ifndef __ASSEMBLER__
0151 struct omap_gpio_reg_offs {
0152     u16 revision;
0153     u16 sysconfig;
0154     u16 direction;
0155     u16 datain;
0156     u16 dataout;
0157     u16 set_dataout;
0158     u16 clr_dataout;
0159     u16 irqstatus;
0160     u16 irqstatus2;
0161     u16 irqstatus_raw0;
0162     u16 irqstatus_raw1;
0163     u16 irqenable;
0164     u16 irqenable2;
0165     u16 set_irqenable;
0166     u16 clr_irqenable;
0167     u16 debounce;
0168     u16 debounce_en;
0169     u16 ctrl;
0170     u16 wkup_en;
0171     u16 leveldetect0;
0172     u16 leveldetect1;
0173     u16 risingdetect;
0174     u16 fallingdetect;
0175     u16 irqctrl;
0176     u16 edgectrl1;
0177     u16 edgectrl2;
0178     u16 pinctrl;
0179
0180     bool irqenable_inv;
0181 };
0182
0183 struct omap_gpio_platform_data {
0184     int bank_type;
0185     int bank_width;     /* GPIO bank width */
0186     int bank_stride;    /* Only needed for omap1 MPUIO */
0187     bool dbck_flag;     /* dbck required or not - True for OMAP3&4 */
0188     bool loses_context; /* whether the bank would ever lose context */
0189     bool is_mpuio;      /* whether the bank is of type MPUIO */
0190     u32 non_wakeup_gpios;
0191
0192     const struct omap_gpio_reg_offs *regs;
0193
0194     /* Return context loss count due to PM states changing */
0195     int (*get_context_loss_count)(struct device *dev);
0196 };
0197
0198 #endif /* __ASSEMBLER__ */
0199
0200 #endif