linux/platform_data/fb-s3c2410.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (c) 2004 Arnaud Patard <arnaud.patard@rtp-net.org>
0004  *
0005  * Inspired by pxafb.h
0006 */
0007
0008 #ifndef __ASM_PLAT_FB_S3C2410_H
0009 #define __ASM_PLAT_FB_S3C2410_H __FILE__
0010
0011 #include <linux/compiler_types.h>
0012
0013 struct s3c2410fb_hw {
0014     unsigned long   lcdcon1;
0015     unsigned long   lcdcon2;
0016     unsigned long   lcdcon3;
0017     unsigned long   lcdcon4;
0018     unsigned long   lcdcon5;
0019 };
0020
0021 /* LCD description */
0022 struct s3c2410fb_display {
0023     /* LCD type */
0024     unsigned type;
0025 #define S3C2410_LCDCON1_DSCAN4     (0<<5)
0026 #define S3C2410_LCDCON1_STN4       (1<<5)
0027 #define S3C2410_LCDCON1_STN8       (2<<5)
0028 #define S3C2410_LCDCON1_TFT    (3<<5)
0029
0030 #define S3C2410_LCDCON1_TFT1BPP    (8<<1)
0031 #define S3C2410_LCDCON1_TFT2BPP    (9<<1)
0032 #define S3C2410_LCDCON1_TFT4BPP    (10<<1)
0033 #define S3C2410_LCDCON1_TFT8BPP    (11<<1)
0034 #define S3C2410_LCDCON1_TFT16BPP   (12<<1)
0035 #define S3C2410_LCDCON1_TFT24BPP   (13<<1)
0036
0037     /* Screen size */
0038     unsigned short width;
0039     unsigned short height;
0040
0041     /* Screen info */
0042     unsigned short xres;
0043     unsigned short yres;
0044     unsigned short bpp;
0045
0046     unsigned pixclock;      /* pixclock in picoseconds */
0047     unsigned short left_margin;  /* value in pixels (TFT) or HCLKs (STN) */
0048     unsigned short right_margin; /* value in pixels (TFT) or HCLKs (STN) */
0049     unsigned short hsync_len;    /* value in pixels (TFT) or HCLKs (STN) */
0050     unsigned short upper_margin;    /* value in lines (TFT) or 0 (STN) */
0051     unsigned short lower_margin;    /* value in lines (TFT) or 0 (STN) */
0052     unsigned short vsync_len;   /* value in lines (TFT) or 0 (STN) */
0053
0054     /* lcd configuration registers */
0055     unsigned long   lcdcon5;
0056 #define S3C2410_LCDCON5_BPP24BL     (1<<12)
0057 #define S3C2410_LCDCON5_FRM565      (1<<11)
0058 #define S3C2410_LCDCON5_INVVCLK     (1<<10)
0059 #define S3C2410_LCDCON5_INVVLINE    (1<<9)
0060 #define S3C2410_LCDCON5_INVVFRAME   (1<<8)
0061 #define S3C2410_LCDCON5_INVVD       (1<<7)
0062 #define S3C2410_LCDCON5_INVVDEN     (1<<6)
0063 #define S3C2410_LCDCON5_INVPWREN    (1<<5)
0064 #define S3C2410_LCDCON5_INVLEND     (1<<4)
0065 #define S3C2410_LCDCON5_PWREN       (1<<3)
0066 #define S3C2410_LCDCON5_ENLEND      (1<<2)
0067 #define S3C2410_LCDCON5_BSWP        (1<<1)
0068 #define S3C2410_LCDCON5_HWSWP       (1<<0)
0069 };
0070
0071 struct s3c2410fb_mach_info {
0072
0073     struct s3c2410fb_display *displays; /* attached displays info */
0074     unsigned num_displays;          /* number of defined displays */
0075     unsigned default_display;
0076
0077     /* GPIOs */
0078
0079     unsigned long   gpcup;
0080     unsigned long   gpcup_mask;
0081     unsigned long   gpccon;
0082     unsigned long   gpccon_mask;
0083     unsigned long   gpdup;
0084     unsigned long   gpdup_mask;
0085     unsigned long   gpdcon;
0086     unsigned long   gpdcon_mask;
0087
0088     void __iomem *  gpccon_reg;
0089     void __iomem *  gpcup_reg;
0090     void __iomem *  gpdcon_reg;
0091     void __iomem *  gpdup_reg;
0092
0093     /* lpc3600 control register */
0094     unsigned long   lpcsel;
0095 };
0096
0097 extern void s3c24xx_fb_set_platdata(struct s3c2410fb_mach_info *);
0098
0099 #endif /* __ASM_PLAT_FB_S3C2410_H */