linux/platform_data/edma.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  TI EDMA definitions
0004  *
0005  *  Copyright (C) 2006-2013 Texas Instruments.
0006  */
0007
0008 /*
0009  * This EDMA3 programming framework exposes two basic kinds of resource:
0010  *
0011  *  Channel Triggers transfers, usually from a hardware event but
0012  *      also manually or by "chaining" from DMA completions.
0013  *      Each channel is coupled to a Parameter RAM (PaRAM) slot.
0014  *
0015  *  Slot    Each PaRAM slot holds a DMA transfer descriptor (PaRAM
0016  *      "set"), source and destination addresses, a link to a
0017  *      next PaRAM slot (if any), options for the transfer, and
0018  *      instructions for updating those addresses.  There are
0019  *      more than twice as many slots as event channels.
0020  *
0021  * Each PaRAM set describes a sequence of transfers, either for one large
0022  * buffer or for several discontiguous smaller buffers.  An EDMA transfer
0023  * is driven only from a channel, which performs the transfers specified
0024  * in its PaRAM slot until there are no more transfers.  When that last
0025  * transfer completes, the "link" field may be used to reload the channel's
0026  * PaRAM slot with a new transfer descriptor.
0027  *
0028  * The EDMA Channel Controller (CC) maps requests from channels into physical
0029  * Transfer Controller (TC) requests when the channel triggers (by hardware
0030  * or software events, or by chaining).  The two physical DMA channels provided
0031  * by the TCs are thus shared by many logical channels.
0032  *
0033  * DaVinci hardware also has a "QDMA" mechanism which is not currently
0034  * supported through this interface.  (DSP firmware uses it though.)
0035  */
0036
0037 #ifndef EDMA_H_
0038 #define EDMA_H_
0039
0040 enum dma_event_q {
0041     EVENTQ_0 = 0,
0042     EVENTQ_1 = 1,
0043     EVENTQ_2 = 2,
0044     EVENTQ_3 = 3,
0045     EVENTQ_DEFAULT = -1
0046 };
0047
0048 #define EDMA_CTLR_CHAN(ctlr, chan)  (((ctlr) << 16) | (chan))
0049 #define EDMA_CTLR(i)            ((i) >> 16)
0050 #define EDMA_CHAN_SLOT(i)       ((i) & 0xffff)
0051
0052 #define EDMA_FILTER_PARAM(ctlr, chan)   ((int[]) { EDMA_CTLR_CHAN(ctlr, chan) })
0053
0054 struct edma_rsv_info {
0055
0056     const s16   (*rsv_chans)[2];
0057     const s16   (*rsv_slots)[2];
0058 };
0059
0060 struct dma_slave_map;
0061
0062 /* platform_data for EDMA driver */
0063 struct edma_soc_info {
0064     /*
0065      * Default queue is expected to be a low-priority queue.
0066      * This way, long transfers on the default queue started
0067      * by the codec engine will not cause audio defects.
0068      */
0069     enum dma_event_q    default_queue;
0070
0071     /* Resource reservation for other cores */
0072     struct edma_rsv_info    *rsv;
0073
0074     /* List of channels allocated for memcpy, terminated with -1 */
0075     s32         *memcpy_channels;
0076
0077     s8  (*queue_priority_mapping)[2];
0078     const s16   (*xbar_chans)[2];
0079
0080     const struct dma_slave_map *slave_map;
0081     int slavecnt;
0082 };
0083
0084 #endif