linux/platform_data/dma-ste-dma40.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright (C) ST-Ericsson SA 2007-2010
0004  * Author: Per Forlin <per.forlin@stericsson.com> for ST-Ericsson
0005  * Author: Jonas Aaberg <jonas.aberg@stericsson.com> for ST-Ericsson
0006  */
0007
0008
0009 #ifndef STE_DMA40_H
0010 #define STE_DMA40_H
0011
0012 #include <linux/dmaengine.h>
0013 #include <linux/scatterlist.h>
0014 #include <linux/workqueue.h>
0015 #include <linux/interrupt.h>
0016
0017 /*
0018  * Maxium size for a single dma descriptor
0019  * Size is limited to 16 bits.
0020  * Size is in the units of addr-widths (1,2,4,8 bytes)
0021  * Larger transfers will be split up to multiple linked desc
0022  */
0023 #define STEDMA40_MAX_SEG_SIZE 0xFFFF
0024
0025 /* dev types for memcpy */
0026 #define STEDMA40_DEV_DST_MEMORY (-1)
0027 #define STEDMA40_DEV_SRC_MEMORY (-1)
0028
0029 enum stedma40_mode {
0030     STEDMA40_MODE_LOGICAL = 0,
0031     STEDMA40_MODE_PHYSICAL,
0032     STEDMA40_MODE_OPERATION,
0033 };
0034
0035 enum stedma40_mode_opt {
0036     STEDMA40_PCHAN_BASIC_MODE = 0,
0037     STEDMA40_LCHAN_SRC_LOG_DST_LOG = 0,
0038     STEDMA40_PCHAN_MODULO_MODE,
0039     STEDMA40_PCHAN_DOUBLE_DST_MODE,
0040     STEDMA40_LCHAN_SRC_PHY_DST_LOG,
0041     STEDMA40_LCHAN_SRC_LOG_DST_PHY,
0042 };
0043
0044 #define STEDMA40_ESIZE_8_BIT  0x0
0045 #define STEDMA40_ESIZE_16_BIT 0x1
0046 #define STEDMA40_ESIZE_32_BIT 0x2
0047 #define STEDMA40_ESIZE_64_BIT 0x3
0048
0049 /* The value 4 indicates that PEN-reg shall be set to 0 */
0050 #define STEDMA40_PSIZE_PHY_1  0x4
0051 #define STEDMA40_PSIZE_PHY_2  0x0
0052 #define STEDMA40_PSIZE_PHY_4  0x1
0053 #define STEDMA40_PSIZE_PHY_8  0x2
0054 #define STEDMA40_PSIZE_PHY_16 0x3
0055
0056 /*
0057  * The number of elements differ in logical and
0058  * physical mode
0059  */
0060 #define STEDMA40_PSIZE_LOG_1  STEDMA40_PSIZE_PHY_2
0061 #define STEDMA40_PSIZE_LOG_4  STEDMA40_PSIZE_PHY_4
0062 #define STEDMA40_PSIZE_LOG_8  STEDMA40_PSIZE_PHY_8
0063 #define STEDMA40_PSIZE_LOG_16 STEDMA40_PSIZE_PHY_16
0064
0065 /* Maximum number of possible physical channels */
0066 #define STEDMA40_MAX_PHYS 32
0067
0068 enum stedma40_flow_ctrl {
0069     STEDMA40_NO_FLOW_CTRL,
0070     STEDMA40_FLOW_CTRL,
0071 };
0072
0073 /**
0074  * struct stedma40_half_channel_info - dst/src channel configuration
0075  *
0076  * @big_endian: true if the src/dst should be read as big endian
0077  * @data_width: Data width of the src/dst hardware
0078  * @p_size: Burst size
0079  * @flow_ctrl: Flow control on/off.
0080  */
0081 struct stedma40_half_channel_info {
0082     bool big_endian;
0083     enum dma_slave_buswidth data_width;
0084     int psize;
0085     enum stedma40_flow_ctrl flow_ctrl;
0086 };
0087
0088 /**
0089  * struct stedma40_chan_cfg - Structure to be filled by client drivers.
0090  *
0091  * @dir: MEM 2 MEM, PERIPH 2 MEM , MEM 2 PERIPH, PERIPH 2 PERIPH
0092  * @high_priority: true if high-priority
0093  * @realtime: true if realtime mode is to be enabled.  Only available on DMA40
0094  * version 3+, i.e DB8500v2+
0095  * @mode: channel mode: physical, logical, or operation
0096  * @mode_opt: options for the chosen channel mode
0097  * @dev_type: src/dst device type (driver uses dir to figure out which)
0098  * @src_info: Parameters for dst half channel
0099  * @dst_info: Parameters for dst half channel
0100  * @use_fixed_channel: if true, use physical channel specified by phy_channel
0101  * @phy_channel: physical channel to use, only if use_fixed_channel is true
0102  *
0103  * This structure has to be filled by the client drivers.
0104  * It is recommended to do all dma configurations for clients in the machine.
0105  *
0106  */
0107 struct stedma40_chan_cfg {
0108     enum dma_transfer_direction      dir;
0109     bool                     high_priority;
0110     bool                     realtime;
0111     enum stedma40_mode           mode;
0112     enum stedma40_mode_opt           mode_opt;
0113     int                  dev_type;
0114     struct stedma40_half_channel_info    src_info;
0115     struct stedma40_half_channel_info    dst_info;
0116
0117     bool                     use_fixed_channel;
0118     int                  phy_channel;
0119 };
0120
0121 /**
0122  * struct stedma40_platform_data - Configuration struct for the dma device.
0123  *
0124  * @dev_tx: mapping between destination event line and io address
0125  * @dev_rx: mapping between source event line and io address
0126  * @disabled_channels: A vector, ending with -1, that marks physical channels
0127  * that are for different reasons not available for the driver.
0128  * @soft_lli_chans: A vector, that marks physical channels will use LLI by SW
0129  * which avoids HW bug that exists in some versions of the controller.
0130  * SoftLLI introduces relink overhead that could impact performace for
0131  * certain use cases.
0132  * @num_of_soft_lli_chans: The number of channels that needs to be configured
0133  * to use SoftLLI.
0134  * @use_esram_lcla: flag for mapping the lcla into esram region
0135  * @num_of_memcpy_chans: The number of channels reserved for memcpy.
0136  * @num_of_phy_chans: The number of physical channels implemented in HW.
0137  * 0 means reading the number of channels from DMA HW but this is only valid
0138  * for 'multiple of 4' channels, like 8.
0139  */
0140 struct stedma40_platform_data {
0141     int              disabled_channels[STEDMA40_MAX_PHYS];
0142     int             *soft_lli_chans;
0143     int              num_of_soft_lli_chans;
0144     bool                 use_esram_lcla;
0145     int              num_of_memcpy_chans;
0146     int              num_of_phy_chans;
0147 };
0148
0149 #ifdef CONFIG_STE_DMA40
0150
0151 /**
0152  * stedma40_filter() - Provides stedma40_chan_cfg to the
0153  * ste_dma40 dma driver via the dmaengine framework.
0154  * does some checking of what's provided.
0155  *
0156  * Never directly called by client. It used by dmaengine.
0157  * @chan: dmaengine handle.
0158  * @data: Must be of type: struct stedma40_chan_cfg and is
0159  * the configuration of the framework.
0160  *
0161  *
0162  */
0163
0164 bool stedma40_filter(struct dma_chan *chan, void *data);
0165
0166 /**
0167  * stedma40_slave_mem() - Transfers a raw data buffer to or from a slave
0168  * (=device)
0169  *
0170  * @chan: dmaengine handle
0171  * @addr: source or destination physicall address.
0172  * @size: bytes to transfer
0173  * @direction: direction of transfer
0174  * @flags: is actually enum dma_ctrl_flags. See dmaengine.h
0175  */
0176
0177 static inline struct
0178 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
0179                         dma_addr_t addr,
0180                         unsigned int size,
0181                         enum dma_transfer_direction direction,
0182                         unsigned long flags)
0183 {
0184     struct scatterlist sg;
0185     sg_init_table(&sg, 1);
0186     sg.dma_address = addr;
0187     sg.length = size;
0188
0189     return dmaengine_prep_slave_sg(chan, &sg, 1, direction, flags);
0190 }
0191
0192 #else
0193 static inline bool stedma40_filter(struct dma_chan *chan, void *data)
0194 {
0195     return false;
0196 }
0197
0198 static inline struct
0199 dma_async_tx_descriptor *stedma40_slave_mem(struct dma_chan *chan,
0200                         dma_addr_t addr,
0201                         unsigned int size,
0202                         enum dma_transfer_direction direction,
0203                         unsigned long flags)
0204 {
0205     return NULL;
0206 }
0207 #endif
0208
0209 #endif