linux/platform_data/dma-iop32x.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * Copyright © 2006, Intel Corporation.
0004  */
0005 #ifndef IOP_ADMA_H
0006 #define IOP_ADMA_H
0007 #include <linux/types.h>
0008 #include <linux/dmaengine.h>
0009 #include <linux/interrupt.h>
0010
0011 #define IOP_ADMA_SLOT_SIZE 32
0012 #define IOP_ADMA_THRESHOLD 4
0013 #ifdef DEBUG
0014 #define IOP_PARANOIA 1
0015 #else
0016 #define IOP_PARANOIA 0
0017 #endif
0018 #define iop_paranoia(x) BUG_ON(IOP_PARANOIA && (x))
0019
0020 #define DMA0_ID 0
0021 #define DMA1_ID 1
0022 #define AAU_ID 2
0023
0024 /**
0025  * struct iop_adma_device - internal representation of an ADMA device
0026  * @pdev: Platform device
0027  * @id: HW ADMA Device selector
0028  * @dma_desc_pool: base of DMA descriptor region (DMA address)
0029  * @dma_desc_pool_virt: base of DMA descriptor region (CPU address)
0030  * @common: embedded struct dma_device
0031  */
0032 struct iop_adma_device {
0033     struct platform_device *pdev;
0034     int id;
0035     dma_addr_t dma_desc_pool;
0036     void *dma_desc_pool_virt;
0037     struct dma_device common;
0038 };
0039
0040 /**
0041  * struct iop_adma_chan - internal representation of an ADMA device
0042  * @pending: allows batching of hardware operations
0043  * @lock: serializes enqueue/dequeue operations to the slot pool
0044  * @mmr_base: memory mapped register base
0045  * @chain: device chain view of the descriptors
0046  * @device: parent device
0047  * @common: common dmaengine channel object members
0048  * @last_used: place holder for allocation to continue from where it left off
0049  * @all_slots: complete domain of slots usable by the channel
0050  * @slots_allocated: records the actual size of the descriptor slot pool
0051  * @irq_tasklet: bottom half where iop_adma_slot_cleanup runs
0052  */
0053 struct iop_adma_chan {
0054     int pending;
0055     spinlock_t lock; /* protects the descriptor slot pool */
0056     void __iomem *mmr_base;
0057     struct list_head chain;
0058     struct iop_adma_device *device;
0059     struct dma_chan common;
0060     struct iop_adma_desc_slot *last_used;
0061     struct list_head all_slots;
0062     int slots_allocated;
0063     struct tasklet_struct irq_tasklet;
0064 };
0065
0066 /**
0067  * struct iop_adma_desc_slot - IOP-ADMA software descriptor
0068  * @slot_node: node on the iop_adma_chan.all_slots list
0069  * @chain_node: node on the op_adma_chan.chain list
0070  * @hw_desc: virtual address of the hardware descriptor chain
0071  * @phys: hardware address of the hardware descriptor chain
0072  * @group_head: first operation in a transaction
0073  * @slot_cnt: total slots used in an transaction (group of operations)
0074  * @slots_per_op: number of slots per operation
0075  * @idx: pool index
0076  * @tx_list: list of descriptors that are associated with one operation
0077  * @async_tx: support for the async_tx api
0078  * @group_list: list of slots that make up a multi-descriptor transaction
0079  *  for example transfer lengths larger than the supported hw max
0080  * @xor_check_result: result of zero sum
0081  * @crc32_result: result crc calculation
0082  */
0083 struct iop_adma_desc_slot {
0084     struct list_head slot_node;
0085     struct list_head chain_node;
0086     void *hw_desc;
0087     struct iop_adma_desc_slot *group_head;
0088     u16 slot_cnt;
0089     u16 slots_per_op;
0090     u16 idx;
0091     struct list_head tx_list;
0092     struct dma_async_tx_descriptor async_tx;
0093     union {
0094         u32 *xor_check_result;
0095         u32 *crc32_result;
0096         u32 *pq_check_result;
0097     };
0098 };
0099
0100 struct iop_adma_platform_data {
0101     int hw_id;
0102     dma_cap_mask_t cap_mask;
0103     size_t pool_size;
0104 };
0105
0106 #define to_iop_sw_desc(addr_hw_desc) \
0107     container_of(addr_hw_desc, struct iop_adma_desc_slot, hw_desc)
0108 #define iop_hw_desc_slot_idx(hw_desc, idx) \
0109     ( (void *) (((unsigned long) hw_desc) + ((idx) << 5)) )
0110 #endif