linux/platform_data/dma-dw.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Driver for the Synopsys DesignWare DMA Controller
0004  *
0005  * Copyright (C) 2007 Atmel Corporation
0006  * Copyright (C) 2010-2011 ST Microelectronics
0007  */
0008 #ifndef _PLATFORM_DATA_DMA_DW_H
0009 #define _PLATFORM_DATA_DMA_DW_H
0010
0011 #include <linux/bits.h>
0012 #include <linux/types.h>
0013
0014 #define DW_DMA_MAX_NR_MASTERS   4
0015 #define DW_DMA_MAX_NR_CHANNELS  8
0016 #define DW_DMA_MIN_BURST    1
0017 #define DW_DMA_MAX_BURST    256
0018
0019 struct device;
0020
0021 /**
0022  * struct dw_dma_slave - Controller-specific information about a slave
0023  *
0024  * @dma_dev:    required DMA master device
0025  * @src_id: src request line
0026  * @dst_id: dst request line
0027  * @m_master:   memory master for transfers on allocated channel
0028  * @p_master:   peripheral master for transfers on allocated channel
0029  * @channels:   mask of the channels permitted for allocation (zero value means any)
0030  * @hs_polarity:set active low polarity of handshake interface
0031  */
0032 struct dw_dma_slave {
0033     struct device       *dma_dev;
0034     u8          src_id;
0035     u8          dst_id;
0036     u8          m_master;
0037     u8          p_master;
0038     u8          channels;
0039     bool            hs_polarity;
0040 };
0041
0042 /**
0043  * struct dw_dma_platform_data - Controller configuration parameters
0044  * @nr_masters: Number of AHB masters supported by the controller
0045  * @nr_channels: Number of channels supported by hardware (max 8)
0046  * @chan_allocation_order: Allocate channels starting from 0 or 7
0047  * @chan_priority: Set channel priority increasing from 0 to 7 or 7 to 0.
0048  * @block_size: Maximum block size supported by the controller
0049  * @data_width: Maximum data width supported by hardware per AHB master
0050  *      (in bytes, power of 2)
0051  * @multi_block: Multi block transfers supported by hardware per channel.
0052  * @max_burst: Maximum value of burst transaction size supported by hardware
0053  *         per channel (in units of CTL.SRC_TR_WIDTH/CTL.DST_TR_WIDTH).
0054  * @protctl: Protection control signals setting per channel.
0055  * @quirks: Optional platform quirks.
0056  */
0057 struct dw_dma_platform_data {
0058     u32     nr_masters;
0059     u32     nr_channels;
0060 #define CHAN_ALLOCATION_ASCENDING   0   /* zero to seven */
0061 #define CHAN_ALLOCATION_DESCENDING  1   /* seven to zero */
0062     u32     chan_allocation_order;
0063 #define CHAN_PRIORITY_ASCENDING     0   /* chan0 highest */
0064 #define CHAN_PRIORITY_DESCENDING    1   /* chan7 highest */
0065     u32     chan_priority;
0066     u32     block_size;
0067     u32     data_width[DW_DMA_MAX_NR_MASTERS];
0068     u32     multi_block[DW_DMA_MAX_NR_CHANNELS];
0069     u32     max_burst[DW_DMA_MAX_NR_CHANNELS];
0070 #define CHAN_PROTCTL_PRIVILEGED     BIT(0)
0071 #define CHAN_PROTCTL_BUFFERABLE     BIT(1)
0072 #define CHAN_PROTCTL_CACHEABLE      BIT(2)
0073 #define CHAN_PROTCTL_MASK       GENMASK(2, 0)
0074     u32     protctl;
0075 #define DW_DMA_QUIRK_XBAR_PRESENT   BIT(0)
0076     u32     quirks;
0077 };
0078
0079 #endif /* _PLATFORM_DATA_DMA_DW_H */