linux/platform_data/davinci_asp.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * TI DaVinci Audio Serial Port support
0004  *
0005  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007
0008 #ifndef __DAVINCI_ASP_H
0009 #define __DAVINCI_ASP_H
0010
0011 #include <linux/genalloc.h>
0012
0013 struct davinci_mcasp_pdata {
0014     u32 tx_dma_offset;
0015     u32 rx_dma_offset;
0016     int asp_chan_q; /* event queue number for ASP channel */
0017     int ram_chan_q; /* event queue number for RAM channel */
0018     /*
0019      * Allowing this is more efficient and eliminates left and right swaps
0020      * caused by underruns, but will swap the left and right channels
0021      * when compared to previous behavior.
0022      */
0023     unsigned enable_channel_combine:1;
0024     unsigned sram_size_playback;
0025     unsigned sram_size_capture;
0026     struct gen_pool *sram_pool;
0027
0028     /*
0029      * If McBSP peripheral gets the clock from an external pin,
0030      * there are three chooses, that are MCBSP_CLKX, MCBSP_CLKR
0031      * and MCBSP_CLKS.
0032      * Depending on different hardware connections it is possible
0033      * to use this setting to change the behaviour of McBSP
0034      * driver.
0035      */
0036     int clk_input_pin;
0037
0038     /*
0039      * This flag works when both clock and FS are outputs for the cpu
0040      * and makes clock more accurate (FS is not symmetrical and the
0041      * clock is very fast.
0042      * The clock becoming faster is named
0043      * i2s continuous serial clock (I2S_SCK) and it is an externally
0044      * visible bit clock.
0045      *
0046      * first line : WordSelect
0047      * second line : ContinuousSerialClock
0048      * third line: SerialData
0049      *
0050      * SYMMETRICAL APPROACH:
0051      *   _______________________          LEFT
0052      * _|         RIGHT         |______________________|
0053      *     _   _         _   _   _   _         _   _
0054      *   _| |_| |_ x16 _| |_| |_| |_| |_ x16 _| |_| |_
0055      *     _   _         _   _   _   _         _   _
0056      *   _/ \_/ \_ ... _/ \_/ \_/ \_/ \_ ... _/ \_/ \_
0057      *    \_/ \_/       \_/ \_/ \_/ \_/       \_/ \_/
0058      *
0059      * ACCURATE CLOCK APPROACH:
0060      *   ______________          LEFT
0061      * _|     RIGHT    |_______________________________|
0062      *     _         _   _         _   _   _   _   _   _
0063      *   _| |_ x16 _| |_| |_ x16 _| |_| |_| |_| |_| |_| |
0064      *     _         _   _          _      dummy cycles
0065      *   _/ \_ ... _/ \_/ \_  ... _/ \__________________
0066      *    \_/       \_/ \_/        \_/
0067      *
0068      */
0069     bool i2s_accurate_sck;
0070
0071     /* McASP specific fields */
0072     int tdm_slots;
0073     u8 op_mode;
0074     u8 dismod;
0075     u8 num_serializer;
0076     u8 *serial_dir;
0077     u8 version;
0078     u8 txnumevt;
0079     u8 rxnumevt;
0080     int tx_dma_channel;
0081     int rx_dma_channel;
0082 };
0083 /* TODO: Fix arch/arm/mach-davinci/ users and remove this define */
0084 #define snd_platform_data davinci_mcasp_pdata
0085
0086 enum {
0087     MCASP_VERSION_1 = 0,    /* DM646x */
0088     MCASP_VERSION_2,    /* DA8xx/OMAPL1x */
0089     MCASP_VERSION_3,        /* TI81xx/AM33xx */
0090     MCASP_VERSION_4,    /* DRA7xxx */
0091     MCASP_VERSION_OMAP, /* OMAP4/5 */
0092 };
0093
0094 enum mcbsp_clk_input_pin {
0095     MCBSP_CLKR = 0,     /* as in DM365 */
0096     MCBSP_CLKS,
0097 };
0098
0099 #define INACTIVE_MODE   0
0100 #define TX_MODE     1
0101 #define RX_MODE     2
0102
0103 #define DAVINCI_MCASP_IIS_MODE  0
0104 #define DAVINCI_MCASP_DIT_MODE  1
0105
0106 #endif