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0013 #ifndef __CROS_EC_COMMANDS_H
0014 #define __CROS_EC_COMMANDS_H
0015
0016 #include <linux/bits.h>
0017 #include <linux/types.h>
0018
0019 #define BUILD_ASSERT(_cond)
0020
0021
0022
0023
0024
0025
0026
0027
0028 #define EC_PROTO_VERSION 0x00000002
0029
0030
0031 #define EC_VER_MASK(version) BIT(version)
0032
0033
0034 #define EC_LPC_ADDR_ACPI_DATA 0x62
0035 #define EC_LPC_ADDR_ACPI_CMD 0x66
0036
0037
0038 #define EC_LPC_ADDR_HOST_DATA 0x200
0039 #define EC_LPC_ADDR_HOST_CMD 0x204
0040
0041
0042
0043 #define EC_LPC_ADDR_HOST_ARGS 0x800
0044 #define EC_LPC_ADDR_HOST_PARAM 0x804
0045
0046
0047
0048 #define EC_LPC_ADDR_HOST_PACKET 0x800
0049 #define EC_LPC_HOST_PACKET_SIZE 0x100
0050
0051
0052
0053
0054
0055
0056
0057
0058 #define EC_HOST_CMD_REGION0 0x800
0059 #define EC_HOST_CMD_REGION1 0x880
0060 #define EC_HOST_CMD_REGION_SIZE 0x80
0061 #define EC_HOST_CMD_MEC_REGION_SIZE 0x8
0062
0063
0064 #define EC_LPC_CMDR_DATA BIT(0)
0065 #define EC_LPC_CMDR_PENDING BIT(1)
0066 #define EC_LPC_CMDR_BUSY BIT(2)
0067 #define EC_LPC_CMDR_CMD BIT(3)
0068 #define EC_LPC_CMDR_ACPI_BRST BIT(4)
0069 #define EC_LPC_CMDR_SCI BIT(5)
0070 #define EC_LPC_CMDR_SMI BIT(6)
0071
0072 #define EC_LPC_ADDR_MEMMAP 0x900
0073 #define EC_MEMMAP_SIZE 255
0074 #define EC_MEMMAP_TEXT_MAX 8
0075
0076
0077 #define EC_MEMMAP_TEMP_SENSOR 0x00
0078 #define EC_MEMMAP_FAN 0x10
0079 #define EC_MEMMAP_TEMP_SENSOR_B 0x18
0080 #define EC_MEMMAP_ID 0x20
0081 #define EC_MEMMAP_ID_VERSION 0x22
0082 #define EC_MEMMAP_THERMAL_VERSION 0x23
0083 #define EC_MEMMAP_BATTERY_VERSION 0x24
0084 #define EC_MEMMAP_SWITCHES_VERSION 0x25
0085 #define EC_MEMMAP_EVENTS_VERSION 0x26
0086 #define EC_MEMMAP_HOST_CMD_FLAGS 0x27
0087
0088 #define EC_MEMMAP_SWITCHES 0x30
0089
0090 #define EC_MEMMAP_HOST_EVENTS 0x34
0091
0092 #define EC_MEMMAP_BATT_VOLT 0x40
0093 #define EC_MEMMAP_BATT_RATE 0x44
0094 #define EC_MEMMAP_BATT_CAP 0x48
0095 #define EC_MEMMAP_BATT_FLAG 0x4c
0096 #define EC_MEMMAP_BATT_COUNT 0x4d
0097 #define EC_MEMMAP_BATT_INDEX 0x4e
0098
0099 #define EC_MEMMAP_BATT_DCAP 0x50
0100 #define EC_MEMMAP_BATT_DVLT 0x54
0101 #define EC_MEMMAP_BATT_LFCC 0x58
0102 #define EC_MEMMAP_BATT_CCNT 0x5c
0103
0104 #define EC_MEMMAP_BATT_MFGR 0x60
0105 #define EC_MEMMAP_BATT_MODEL 0x68
0106 #define EC_MEMMAP_BATT_SERIAL 0x70
0107 #define EC_MEMMAP_BATT_TYPE 0x78
0108 #define EC_MEMMAP_ALS 0x80
0109
0110 #define EC_MEMMAP_ACC_STATUS 0x90
0111
0112 #define EC_MEMMAP_ACC_DATA 0x92
0113
0114
0115
0116 #define EC_MEMMAP_GYRO_DATA 0xa0
0117
0118
0119
0120
0121
0122
0123
0124 #define EC_MEMMAP_NO_ACPI 0xe0
0125
0126
0127 #define EC_MEMMAP_ACC_STATUS_SAMPLE_ID_MASK 0x0f
0128 #define EC_MEMMAP_ACC_STATUS_BUSY_BIT BIT(4)
0129 #define EC_MEMMAP_ACC_STATUS_PRESENCE_BIT BIT(7)
0130
0131
0132 #define EC_TEMP_SENSOR_ENTRIES 16
0133
0134
0135
0136
0137
0138 #define EC_TEMP_SENSOR_B_ENTRIES 8
0139
0140
0141 #define EC_TEMP_SENSOR_NOT_PRESENT 0xff
0142 #define EC_TEMP_SENSOR_ERROR 0xfe
0143 #define EC_TEMP_SENSOR_NOT_POWERED 0xfd
0144 #define EC_TEMP_SENSOR_NOT_CALIBRATED 0xfc
0145
0146
0147
0148
0149 #define EC_TEMP_SENSOR_OFFSET 200
0150
0151
0152
0153
0154 #define EC_ALS_ENTRIES 2
0155
0156
0157
0158
0159
0160
0161 #define EC_TEMP_SENSOR_DEFAULT (296 - EC_TEMP_SENSOR_OFFSET)
0162
0163 #define EC_FAN_SPEED_ENTRIES 4
0164 #define EC_FAN_SPEED_NOT_PRESENT 0xffff
0165 #define EC_FAN_SPEED_STALLED 0xfffe
0166
0167
0168 #define EC_BATT_FLAG_AC_PRESENT 0x01
0169 #define EC_BATT_FLAG_BATT_PRESENT 0x02
0170 #define EC_BATT_FLAG_DISCHARGING 0x04
0171 #define EC_BATT_FLAG_CHARGING 0x08
0172 #define EC_BATT_FLAG_LEVEL_CRITICAL 0x10
0173
0174 #define EC_BATT_FLAG_INVALID_DATA 0x20
0175
0176
0177 #define EC_SWITCH_LID_OPEN 0x01
0178 #define EC_SWITCH_POWER_BUTTON_PRESSED 0x02
0179 #define EC_SWITCH_WRITE_PROTECT_DISABLED 0x04
0180
0181 #define EC_SWITCH_IGNORE1 0x08
0182
0183 #define EC_SWITCH_DEDICATED_RECOVERY 0x10
0184
0185 #define EC_SWITCH_IGNORE0 0x20
0186
0187
0188
0189 #define EC_HOST_CMD_FLAG_LPC_ARGS_SUPPORTED 0x01
0190
0191 #define EC_HOST_CMD_FLAG_VERSION_3 0x02
0192
0193
0194 #define EC_WIRELESS_SWITCH_ALL ~0x00
0195 #define EC_WIRELESS_SWITCH_WLAN 0x01
0196 #define EC_WIRELESS_SWITCH_BLUETOOTH 0x02
0197 #define EC_WIRELESS_SWITCH_WWAN 0x04
0198 #define EC_WIRELESS_SWITCH_WLAN_POWER 0x08
0199
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0220 #define EC_CMD_ACPI_READ 0x0080
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0235 #define EC_CMD_ACPI_WRITE 0x0081
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0244 #define EC_CMD_ACPI_BURST_ENABLE 0x0082
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0250
0251
0252 #define EC_CMD_ACPI_BURST_DISABLE 0x0083
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0260
0261 #define EC_CMD_ACPI_QUERY_EVENT 0x0084
0262
0263
0264
0265
0266 #define EC_ACPI_MEM_VERSION 0x00
0267
0268
0269
0270
0271 #define EC_ACPI_MEM_TEST 0x01
0272
0273 #define EC_ACPI_MEM_TEST_COMPLIMENT 0x02
0274
0275
0276 #define EC_ACPI_MEM_KEYBOARD_BACKLIGHT 0x03
0277
0278 #define EC_ACPI_MEM_FAN_DUTY 0x04
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0295 #define EC_ACPI_MEM_TEMP_ID 0x05
0296 #define EC_ACPI_MEM_TEMP_THRESHOLD 0x06
0297 #define EC_ACPI_MEM_TEMP_COMMIT 0x07
0298
0299
0300
0301
0302
0303
0304 #define EC_ACPI_MEM_TEMP_COMMIT_SELECT_MASK BIT(0)
0305 #define EC_ACPI_MEM_TEMP_COMMIT_ENABLE_MASK BIT(1)
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0321
0322 #define EC_ACPI_MEM_CHARGING_LIMIT 0x08
0323
0324
0325 #define EC_ACPI_MEM_CHARGING_LIMIT_STEP_MA 64
0326
0327 #define EC_ACPI_MEM_CHARGING_LIMIT_DISABLED 0xff
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0338
0339 #define EC_ACPI_MEM_DEVICE_ORIENTATION 0x09
0340 #define EC_ACPI_MEM_TBMD_SHIFT 0
0341 #define EC_ACPI_MEM_TBMD_MASK 0x1
0342 #define EC_ACPI_MEM_DDPN_SHIFT 1
0343 #define EC_ACPI_MEM_DDPN_MASK 0x7
0344
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0356
0357 #define EC_ACPI_MEM_DEVICE_FEATURES0 0x0a
0358 #define EC_ACPI_MEM_DEVICE_FEATURES1 0x0b
0359 #define EC_ACPI_MEM_DEVICE_FEATURES2 0x0c
0360 #define EC_ACPI_MEM_DEVICE_FEATURES3 0x0d
0361 #define EC_ACPI_MEM_DEVICE_FEATURES4 0x0e
0362 #define EC_ACPI_MEM_DEVICE_FEATURES5 0x0f
0363 #define EC_ACPI_MEM_DEVICE_FEATURES6 0x10
0364 #define EC_ACPI_MEM_DEVICE_FEATURES7 0x11
0365
0366 #define EC_ACPI_MEM_BATTERY_INDEX 0x12
0367
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0374
0375 #define EC_ACPI_MEM_USB_PORT_POWER 0x13
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0380
0381 #define EC_ACPI_MEM_MAPPED_BEGIN 0x20
0382 #define EC_ACPI_MEM_MAPPED_SIZE 0xe0
0383
0384
0385 #define EC_ACPI_MEM_VERSION_CURRENT 2
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0427 #define __ec_align1 __packed
0428 #define __ec_align2 __packed
0429 #define __ec_align4 __packed
0430 #define __ec_align_size1 __packed
0431 #define __ec_align_offset1 __packed
0432 #define __ec_align_offset2 __packed
0433 #define __ec_todo_packed __packed
0434 #define __ec_todo_unpacked
0435
0436
0437
0438
0439 #define EC_LPC_STATUS_TO_HOST 0x01
0440
0441 #define EC_LPC_STATUS_FROM_HOST 0x02
0442
0443 #define EC_LPC_STATUS_PROCESSING 0x04
0444
0445 #define EC_LPC_STATUS_LAST_CMD 0x08
0446
0447 #define EC_LPC_STATUS_BURST_MODE 0x10
0448
0449 #define EC_LPC_STATUS_SCI_PENDING 0x20
0450
0451 #define EC_LPC_STATUS_SMI_PENDING 0x40
0452
0453 #define EC_LPC_STATUS_RESERVED 0x80
0454
0455
0456
0457
0458
0459 #define EC_LPC_STATUS_BUSY_MASK \
0460 (EC_LPC_STATUS_FROM_HOST | EC_LPC_STATUS_PROCESSING)
0461
0462
0463
0464
0465
0466 enum ec_status {
0467 EC_RES_SUCCESS = 0,
0468 EC_RES_INVALID_COMMAND = 1,
0469 EC_RES_ERROR = 2,
0470 EC_RES_INVALID_PARAM = 3,
0471 EC_RES_ACCESS_DENIED = 4,
0472 EC_RES_INVALID_RESPONSE = 5,
0473 EC_RES_INVALID_VERSION = 6,
0474 EC_RES_INVALID_CHECKSUM = 7,
0475 EC_RES_IN_PROGRESS = 8,
0476 EC_RES_UNAVAILABLE = 9,
0477 EC_RES_TIMEOUT = 10,
0478 EC_RES_OVERFLOW = 11,
0479 EC_RES_INVALID_HEADER = 12,
0480 EC_RES_REQUEST_TRUNCATED = 13,
0481 EC_RES_RESPONSE_TOO_BIG = 14,
0482 EC_RES_BUS_ERROR = 15,
0483 EC_RES_BUSY = 16,
0484 EC_RES_INVALID_HEADER_VERSION = 17,
0485 EC_RES_INVALID_HEADER_CRC = 18,
0486 EC_RES_INVALID_DATA_CRC = 19,
0487 EC_RES_DUP_UNAVAILABLE = 20,
0488 };
0489
0490
0491
0492
0493
0494
0495
0496
0497 enum host_event_code {
0498 EC_HOST_EVENT_LID_CLOSED = 1,
0499 EC_HOST_EVENT_LID_OPEN = 2,
0500 EC_HOST_EVENT_POWER_BUTTON = 3,
0501 EC_HOST_EVENT_AC_CONNECTED = 4,
0502 EC_HOST_EVENT_AC_DISCONNECTED = 5,
0503 EC_HOST_EVENT_BATTERY_LOW = 6,
0504 EC_HOST_EVENT_BATTERY_CRITICAL = 7,
0505 EC_HOST_EVENT_BATTERY = 8,
0506 EC_HOST_EVENT_THERMAL_THRESHOLD = 9,
0507
0508 EC_HOST_EVENT_DEVICE = 10,
0509 EC_HOST_EVENT_THERMAL = 11,
0510 EC_HOST_EVENT_USB_CHARGER = 12,
0511 EC_HOST_EVENT_KEY_PRESSED = 13,
0512
0513
0514
0515
0516
0517 EC_HOST_EVENT_INTERFACE_READY = 14,
0518
0519 EC_HOST_EVENT_KEYBOARD_RECOVERY = 15,
0520
0521
0522 EC_HOST_EVENT_THERMAL_SHUTDOWN = 16,
0523
0524 EC_HOST_EVENT_BATTERY_SHUTDOWN = 17,
0525
0526
0527 EC_HOST_EVENT_THROTTLE_START = 18,
0528
0529 EC_HOST_EVENT_THROTTLE_STOP = 19,
0530
0531
0532 EC_HOST_EVENT_HANG_DETECT = 20,
0533
0534 EC_HOST_EVENT_HANG_REBOOT = 21,
0535
0536
0537 EC_HOST_EVENT_PD_MCU = 22,
0538
0539
0540 EC_HOST_EVENT_BATTERY_STATUS = 23,
0541
0542
0543 EC_HOST_EVENT_PANIC = 24,
0544
0545
0546 EC_HOST_EVENT_KEYBOARD_FASTBOOT = 25,
0547
0548
0549 EC_HOST_EVENT_RTC = 26,
0550
0551
0552 EC_HOST_EVENT_MKBP = 27,
0553
0554
0555 EC_HOST_EVENT_USB_MUX = 28,
0556
0557
0558 EC_HOST_EVENT_MODE_CHANGE = 29,
0559
0560
0561 EC_HOST_EVENT_KEYBOARD_RECOVERY_HW_REINIT = 30,
0562
0563
0564 EC_HOST_EVENT_WOV = 31,
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0571
0572
0573 EC_HOST_EVENT_INVALID = 32
0574 };
0575
0576 #define EC_HOST_EVENT_MASK(event_code) BIT_ULL((event_code) - 1)
0577
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0585
0586 struct ec_lpc_host_args {
0587 uint8_t flags;
0588 uint8_t command_version;
0589 uint8_t data_size;
0590 uint8_t checksum;
0591 } __ec_align4;
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0603 #define EC_HOST_ARGS_FLAG_FROM_HOST 0x01
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0611 #define EC_HOST_ARGS_FLAG_TO_HOST 0x02
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0652
0653 #define EC_SPI_FRAME_START 0xec
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0657
0658 #define EC_SPI_PAST_END 0xed
0659
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0664
0665 #define EC_SPI_RX_READY 0xf8
0666
0667
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0670
0671 #define EC_SPI_RECEIVING 0xf9
0672
0673
0674 #define EC_SPI_PROCESSING 0xfa
0675
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0680 #define EC_SPI_RX_BAD_DATA 0xfb
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0687 #define EC_SPI_NOT_READY 0xfc
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0694 #define EC_SPI_OLD_READY 0xfd
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0714 #define EC_PROTO2_REQUEST_HEADER_BYTES 3
0715 #define EC_PROTO2_REQUEST_TRAILER_BYTES 1
0716 #define EC_PROTO2_REQUEST_OVERHEAD (EC_PROTO2_REQUEST_HEADER_BYTES + \
0717 EC_PROTO2_REQUEST_TRAILER_BYTES)
0718
0719 #define EC_PROTO2_RESPONSE_HEADER_BYTES 2
0720 #define EC_PROTO2_RESPONSE_TRAILER_BYTES 1
0721 #define EC_PROTO2_RESPONSE_OVERHEAD (EC_PROTO2_RESPONSE_HEADER_BYTES + \
0722 EC_PROTO2_RESPONSE_TRAILER_BYTES)
0723
0724
0725 #define EC_PROTO2_MAX_PARAM_SIZE 0xfc
0726
0727
0728 #define EC_PROTO2_MAX_REQUEST_SIZE (EC_PROTO2_REQUEST_OVERHEAD + \
0729 EC_PROTO2_MAX_PARAM_SIZE)
0730 #define EC_PROTO2_MAX_RESPONSE_SIZE (EC_PROTO2_RESPONSE_OVERHEAD + \
0731 EC_PROTO2_MAX_PARAM_SIZE)
0732
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0738
0739 #define EC_COMMAND_PROTOCOL_3 0xda
0740
0741 #define EC_HOST_REQUEST_VERSION 3
0742
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0755 struct ec_host_request {
0756 uint8_t struct_version;
0757 uint8_t checksum;
0758 uint16_t command;
0759 uint8_t command_version;
0760 uint8_t reserved;
0761 uint16_t data_len;
0762 } __ec_align4;
0763
0764 #define EC_HOST_RESPONSE_VERSION 3
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0774
0775 struct ec_host_response {
0776 uint8_t struct_version;
0777 uint8_t checksum;
0778 uint16_t result;
0779 uint16_t data_len;
0780 uint16_t reserved;
0781 } __ec_align4;
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0844 struct ec_host_request4 {
0845
0846
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0850
0851 uint8_t fields0;
0852
0853
0854
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0856
0857
0858 uint8_t fields1;
0859
0860
0861 uint16_t command;
0862
0863
0864 uint16_t data_len;
0865
0866
0867 uint8_t reserved;
0868
0869
0870 uint8_t header_crc;
0871 } __ec_align4;
0872
0873
0874 struct ec_host_response4 {
0875
0876
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0879
0880
0881 uint8_t fields0;
0882
0883
0884
0885
0886
0887 uint8_t fields1;
0888
0889
0890 uint16_t result;
0891
0892
0893 uint16_t data_len;
0894
0895
0896 uint8_t reserved;
0897
0898
0899 uint8_t header_crc;
0900 } __ec_align4;
0901
0902
0903 #define EC_PACKET4_0_STRUCT_VERSION_MASK 0x0f
0904 #define EC_PACKET4_0_IS_RESPONSE_MASK 0x10
0905 #define EC_PACKET4_0_SEQ_NUM_SHIFT 5
0906 #define EC_PACKET4_0_SEQ_NUM_MASK 0x60
0907 #define EC_PACKET4_0_SEQ_DUP_MASK 0x80
0908
0909
0910 #define EC_PACKET4_1_COMMAND_VERSION_MASK 0x1f
0911 #define EC_PACKET4_1_DATA_CRC_PRESENT_MASK 0x80
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0934
0935 #define EC_CMD_PROTO_VERSION 0x0000
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0940
0941 struct ec_response_proto_version {
0942 uint32_t version;
0943 } __ec_align4;
0944
0945
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0947
0948
0949 #define EC_CMD_HELLO 0x0001
0950
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0954
0955 struct ec_params_hello {
0956 uint32_t in_data;
0957 } __ec_align4;
0958
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0962
0963 struct ec_response_hello {
0964 uint32_t out_data;
0965 } __ec_align4;
0966
0967
0968 #define EC_CMD_GET_VERSION 0x0002
0969
0970 enum ec_current_image {
0971 EC_IMAGE_UNKNOWN = 0,
0972 EC_IMAGE_RO,
0973 EC_IMAGE_RW
0974 };
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0982
0983 struct ec_response_get_version {
0984 char version_string_ro[32];
0985 char version_string_rw[32];
0986 char reserved[32];
0987 uint32_t current_image;
0988 } __ec_align4;
0989
0990
0991 #define EC_CMD_READ_TEST 0x0003
0992
0993
0994
0995
0996
0997
0998 struct ec_params_read_test {
0999 uint32_t offset;
1000 uint32_t size;
1001 } __ec_align4;
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1007 struct ec_response_read_test {
1008 uint32_t data[32];
1009 } __ec_align4;
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1016 #define EC_CMD_GET_BUILD_INFO 0x0004
1017
1018
1019 #define EC_CMD_GET_CHIP_INFO 0x0005
1020
1021
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1025
1026
1027 struct ec_response_get_chip_info {
1028 char vendor[32];
1029 char name[32];
1030 char revision[32];
1031 } __ec_align4;
1032
1033
1034 #define EC_CMD_GET_BOARD_VERSION 0x0006
1035
1036
1037
1038
1039
1040 struct ec_response_board_version {
1041 uint16_t board_version;
1042 } __ec_align2;
1043
1044
1045
1046
1047
1048
1049
1050
1051
1052 #define EC_CMD_READ_MEMMAP 0x0007
1053
1054
1055
1056
1057
1058
1059 struct ec_params_read_memmap {
1060 uint8_t offset;
1061 uint8_t size;
1062 } __ec_align1;
1063
1064
1065 #define EC_CMD_GET_CMD_VERSIONS 0x0008
1066
1067
1068
1069
1070
1071 struct ec_params_get_cmd_versions {
1072 uint8_t cmd;
1073 } __ec_align1;
1074
1075
1076
1077
1078
1079
1080 struct ec_params_get_cmd_versions_v1 {
1081 uint16_t cmd;
1082 } __ec_align2;
1083
1084
1085
1086
1087
1088
1089 struct ec_response_get_cmd_versions {
1090 uint32_t version_mask;
1091 } __ec_align4;
1092
1093
1094
1095
1096
1097
1098
1099
1100 #define EC_CMD_GET_COMMS_STATUS 0x0009
1101
1102
1103 enum ec_comms_status {
1104 EC_COMMS_STATUS_PROCESSING = BIT(0),
1105 };
1106
1107
1108
1109
1110
1111
1112 struct ec_response_get_comms_status {
1113 uint32_t flags;
1114 } __ec_align4;
1115
1116
1117 #define EC_CMD_TEST_PROTOCOL 0x000A
1118
1119
1120 struct ec_params_test_protocol {
1121 uint32_t ec_result;
1122 uint32_t ret_len;
1123 uint8_t buf[32];
1124 } __ec_align4;
1125
1126
1127 struct ec_response_test_protocol {
1128 uint8_t buf[32];
1129 } __ec_align4;
1130
1131
1132 #define EC_CMD_GET_PROTOCOL_INFO 0x000B
1133
1134
1135
1136 #define EC_PROTOCOL_INFO_IN_PROGRESS_SUPPORTED BIT(0)
1137
1138
1139
1140
1141
1142
1143
1144
1145
1146 struct ec_response_get_protocol_info {
1147
1148 uint32_t protocol_versions;
1149 uint16_t max_request_packet_size;
1150 uint16_t max_response_packet_size;
1151 uint32_t flags;
1152 } __ec_align4;
1153
1154
1155
1156
1157
1158
1159 #define EC_GSV_SET 0x80000000
1160
1161
1162
1163
1164
1165 #define EC_GSV_PARAM_MASK 0x00ffffff
1166
1167 struct ec_params_get_set_value {
1168 uint32_t flags;
1169 uint32_t value;
1170 } __ec_align4;
1171
1172 struct ec_response_get_set_value {
1173 uint32_t flags;
1174 uint32_t value;
1175 } __ec_align4;
1176
1177
1178 #define EC_CMD_GSV_PAUSE_IN_S5 0x000C
1179
1180
1181
1182 #define EC_CMD_GET_FEATURES 0x000D
1183
1184
1185 enum ec_feature_code {
1186
1187
1188
1189
1190 EC_FEATURE_LIMITED = 0,
1191
1192
1193
1194
1195 EC_FEATURE_FLASH = 1,
1196
1197
1198
1199 EC_FEATURE_PWM_FAN = 2,
1200
1201
1202
1203 EC_FEATURE_PWM_KEYB = 3,
1204
1205
1206
1207 EC_FEATURE_LIGHTBAR = 4,
1208
1209 EC_FEATURE_LED = 5,
1210
1211
1212
1213
1214 EC_FEATURE_MOTION_SENSE = 6,
1215
1216 EC_FEATURE_KEYB = 7,
1217
1218 EC_FEATURE_PSTORE = 8,
1219
1220 EC_FEATURE_PORT80 = 9,
1221
1222
1223
1224
1225 EC_FEATURE_THERMAL = 10,
1226
1227 EC_FEATURE_BKLIGHT_SWITCH = 11,
1228
1229 EC_FEATURE_WIFI_SWITCH = 12,
1230
1231 EC_FEATURE_HOST_EVENTS = 13,
1232
1233 EC_FEATURE_GPIO = 14,
1234
1235 EC_FEATURE_I2C = 15,
1236
1237 EC_FEATURE_CHARGER = 16,
1238
1239 EC_FEATURE_BATTERY = 17,
1240
1241
1242
1243
1244 EC_FEATURE_SMART_BATTERY = 18,
1245
1246 EC_FEATURE_HANG_DETECT = 19,
1247
1248 EC_FEATURE_PMU = 20,
1249
1250 EC_FEATURE_SUB_MCU = 21,
1251
1252 EC_FEATURE_USB_PD = 22,
1253
1254 EC_FEATURE_USB_MUX = 23,
1255
1256 EC_FEATURE_MOTION_SENSE_FIFO = 24,
1257
1258 EC_FEATURE_VSTORE = 25,
1259
1260 EC_FEATURE_USBC_SS_MUX_VIRTUAL = 26,
1261
1262 EC_FEATURE_RTC = 27,
1263
1264 EC_FEATURE_FINGERPRINT = 28,
1265
1266 EC_FEATURE_TOUCHPAD = 29,
1267
1268 EC_FEATURE_RWSIG = 30,
1269
1270 EC_FEATURE_DEVICE_EVENT = 31,
1271
1272 EC_FEATURE_UNIFIED_WAKE_MASKS = 32,
1273
1274 EC_FEATURE_HOST_EVENT64 = 33,
1275
1276 EC_FEATURE_EXEC_IN_RAM = 34,
1277
1278 EC_FEATURE_CEC = 35,
1279
1280 EC_FEATURE_MOTION_SENSE_TIGHT_TIMESTAMPS = 36,
1281
1282
1283
1284
1285
1286 EC_FEATURE_REFINED_TABLET_MODE_HYSTERESIS = 37,
1287
1288 EC_FEATURE_SCP = 39,
1289
1290 EC_FEATURE_ISH = 40,
1291
1292 EC_FEATURE_TYPEC_CMD = 41,
1293
1294
1295
1296
1297 EC_FEATURE_TYPEC_REQUIRE_AP_MODE_ENTRY = 42,
1298
1299
1300
1301
1302 EC_FEATURE_TYPEC_MUX_REQUIRE_AP_ACK = 43,
1303
1304 EC_FEATURE_SCP_C1 = 45,
1305 };
1306
1307 #define EC_FEATURE_MASK_0(event_code) BIT(event_code % 32)
1308 #define EC_FEATURE_MASK_1(event_code) BIT(event_code - 32)
1309
1310 struct ec_response_get_features {
1311 uint32_t flags[2];
1312 } __ec_align4;
1313
1314
1315
1316 #define EC_CMD_GET_SKU_ID 0x000E
1317
1318
1319 #define EC_CMD_SET_SKU_ID 0x000F
1320
1321 struct ec_sku_id_info {
1322 uint32_t sku_id;
1323 } __ec_align4;
1324
1325
1326
1327
1328
1329 #define EC_CMD_FLASH_INFO 0x0010
1330 #define EC_VER_FLASH_INFO 2
1331
1332
1333
1334
1335
1336
1337
1338
1339
1340
1341
1342
1343
1344 struct ec_response_flash_info {
1345 uint32_t flash_size;
1346 uint32_t write_block_size;
1347 uint32_t erase_block_size;
1348 uint32_t protect_block_size;
1349 } __ec_align4;
1350
1351
1352
1353
1354
1355 #define EC_FLASH_INFO_ERASE_TO_0 BIT(0)
1356
1357
1358
1359
1360
1361
1362
1363
1364 #define EC_FLASH_INFO_SELECT_REQUIRED BIT(1)
1365
1366
1367
1368
1369
1370
1371
1372
1373
1374
1375
1376
1377
1378
1379
1380
1381
1382
1383
1384
1385
1386
1387
1388
1389
1390
1391
1392
1393
1394
1395 struct ec_response_flash_info_1 {
1396
1397 uint32_t flash_size;
1398 uint32_t write_block_size;
1399 uint32_t erase_block_size;
1400 uint32_t protect_block_size;
1401
1402
1403 uint32_t write_ideal_size;
1404 uint32_t flags;
1405 } __ec_align4;
1406
1407 struct ec_params_flash_info_2 {
1408
1409 uint16_t num_banks_desc;
1410
1411 uint8_t reserved[2];
1412 } __ec_align4;
1413
1414 struct ec_flash_bank {
1415
1416 uint16_t count;
1417
1418 uint8_t size_exp;
1419
1420 uint8_t write_size_exp;
1421
1422 uint8_t erase_size_exp;
1423
1424 uint8_t protect_size_exp;
1425
1426 uint8_t reserved[2];
1427 };
1428
1429 struct ec_response_flash_info_2 {
1430
1431 uint32_t flash_size;
1432
1433 uint32_t flags;
1434
1435 uint32_t write_ideal_size;
1436
1437 uint16_t num_banks_total;
1438
1439 uint16_t num_banks_desc;
1440 struct ec_flash_bank banks[];
1441 } __ec_align4;
1442
1443
1444
1445
1446
1447
1448 #define EC_CMD_FLASH_READ 0x0011
1449
1450
1451
1452
1453
1454
1455 struct ec_params_flash_read {
1456 uint32_t offset;
1457 uint32_t size;
1458 } __ec_align4;
1459
1460
1461 #define EC_CMD_FLASH_WRITE 0x0012
1462 #define EC_VER_FLASH_WRITE 1
1463
1464
1465 #define EC_FLASH_WRITE_VER0_SIZE 64
1466
1467
1468
1469
1470
1471
1472 struct ec_params_flash_write {
1473 uint32_t offset;
1474 uint32_t size;
1475
1476 } __ec_align4;
1477
1478
1479 #define EC_CMD_FLASH_ERASE 0x0013
1480
1481
1482
1483
1484
1485
1486 struct ec_params_flash_erase {
1487 uint32_t offset;
1488 uint32_t size;
1489 } __ec_align4;
1490
1491
1492
1493
1494
1495
1496
1497
1498
1499
1500
1501
1502
1503
1504
1505
1506
1507
1508 enum ec_flash_erase_cmd {
1509 FLASH_ERASE_SECTOR,
1510 FLASH_ERASE_SECTOR_ASYNC,
1511 FLASH_ERASE_GET_RESULT,
1512 };
1513
1514
1515
1516
1517
1518
1519
1520
1521 struct ec_params_flash_erase_v1 {
1522 uint8_t cmd;
1523 uint8_t reserved;
1524 uint16_t flag;
1525 struct ec_params_flash_erase params;
1526 } __ec_align4;
1527
1528
1529
1530
1531
1532
1533
1534
1535
1536
1537
1538 #define EC_CMD_FLASH_PROTECT 0x0015
1539 #define EC_VER_FLASH_PROTECT 1
1540
1541
1542
1543 #define EC_FLASH_PROTECT_RO_AT_BOOT BIT(0)
1544
1545
1546
1547
1548 #define EC_FLASH_PROTECT_RO_NOW BIT(1)
1549
1550 #define EC_FLASH_PROTECT_ALL_NOW BIT(2)
1551
1552 #define EC_FLASH_PROTECT_GPIO_ASSERTED BIT(3)
1553
1554 #define EC_FLASH_PROTECT_ERROR_STUCK BIT(4)
1555
1556
1557
1558
1559
1560 #define EC_FLASH_PROTECT_ERROR_INCONSISTENT BIT(5)
1561
1562 #define EC_FLASH_PROTECT_ALL_AT_BOOT BIT(6)
1563
1564 #define EC_FLASH_PROTECT_RW_AT_BOOT BIT(7)
1565
1566 #define EC_FLASH_PROTECT_RW_NOW BIT(8)
1567
1568 #define EC_FLASH_PROTECT_ROLLBACK_AT_BOOT BIT(9)
1569
1570 #define EC_FLASH_PROTECT_ROLLBACK_NOW BIT(10)
1571
1572
1573
1574
1575
1576
1577
1578 struct ec_params_flash_protect {
1579 uint32_t mask;
1580 uint32_t flags;
1581 } __ec_align4;
1582
1583
1584
1585
1586
1587
1588
1589
1590
1591
1592 struct ec_response_flash_protect {
1593 uint32_t flags;
1594 uint32_t valid_flags;
1595 uint32_t writable_flags;
1596 } __ec_align4;
1597
1598
1599
1600
1601
1602
1603
1604 #define EC_CMD_FLASH_REGION_INFO 0x0016
1605 #define EC_VER_FLASH_REGION_INFO 1
1606
1607 enum ec_flash_region {
1608
1609 EC_FLASH_REGION_RO = 0,
1610
1611
1612
1613
1614
1615
1616
1617
1618
1619 EC_FLASH_REGION_ACTIVE,
1620
1621
1622
1623
1624 EC_FLASH_REGION_WP_RO,
1625
1626 EC_FLASH_REGION_UPDATE,
1627
1628 EC_FLASH_REGION_COUNT,
1629 };
1630
1631
1632
1633
1634 #define EC_FLASH_REGION_RW EC_FLASH_REGION_ACTIVE
1635
1636
1637
1638
1639
1640
1641 struct ec_params_flash_region_info {
1642 uint32_t region;
1643 } __ec_align4;
1644
1645 struct ec_response_flash_region_info {
1646 uint32_t offset;
1647 uint32_t size;
1648 } __ec_align4;
1649
1650
1651 #define EC_CMD_VBNV_CONTEXT 0x0017
1652 #define EC_VER_VBNV_CONTEXT 1
1653 #define EC_VBNV_BLOCK_SIZE 16
1654
1655 enum ec_vbnvcontext_op {
1656 EC_VBNV_CONTEXT_OP_READ,
1657 EC_VBNV_CONTEXT_OP_WRITE,
1658 };
1659
1660 struct ec_params_vbnvcontext {
1661 uint32_t op;
1662 uint8_t block[EC_VBNV_BLOCK_SIZE];
1663 } __ec_align4;
1664
1665 struct ec_response_vbnvcontext {
1666 uint8_t block[EC_VBNV_BLOCK_SIZE];
1667 } __ec_align4;
1668
1669
1670
1671 #define EC_CMD_FLASH_SPI_INFO 0x0018
1672
1673 struct ec_response_flash_spi_info {
1674
1675 uint8_t jedec[3];
1676
1677
1678 uint8_t reserved0;
1679
1680
1681 uint8_t mfr_dev_id[2];
1682
1683
1684 uint8_t sr1, sr2;
1685 } __ec_align1;
1686
1687
1688
1689 #define EC_CMD_FLASH_SELECT 0x0019
1690
1691
1692
1693
1694
1695 struct ec_params_flash_select {
1696 uint8_t select;
1697 } __ec_align4;
1698
1699
1700
1701
1702
1703
1704 #define EC_CMD_PWM_GET_FAN_TARGET_RPM 0x0020
1705
1706 struct ec_response_pwm_get_fan_rpm {
1707 uint32_t rpm;
1708 } __ec_align4;
1709
1710
1711 #define EC_CMD_PWM_SET_FAN_TARGET_RPM 0x0021
1712
1713
1714 struct ec_params_pwm_set_fan_target_rpm_v0 {
1715 uint32_t rpm;
1716 } __ec_align4;
1717
1718
1719 struct ec_params_pwm_set_fan_target_rpm_v1 {
1720 uint32_t rpm;
1721 uint8_t fan_idx;
1722 } __ec_align_size1;
1723
1724
1725
1726 #define EC_CMD_PWM_GET_KEYBOARD_BACKLIGHT 0x0022
1727
1728 struct ec_response_pwm_get_keyboard_backlight {
1729 uint8_t percent;
1730 uint8_t enabled;
1731 } __ec_align1;
1732
1733
1734
1735 #define EC_CMD_PWM_SET_KEYBOARD_BACKLIGHT 0x0023
1736
1737 struct ec_params_pwm_set_keyboard_backlight {
1738 uint8_t percent;
1739 } __ec_align1;
1740
1741
1742 #define EC_CMD_PWM_SET_FAN_DUTY 0x0024
1743
1744
1745 struct ec_params_pwm_set_fan_duty_v0 {
1746 uint32_t percent;
1747 } __ec_align4;
1748
1749
1750 struct ec_params_pwm_set_fan_duty_v1 {
1751 uint32_t percent;
1752 uint8_t fan_idx;
1753 } __ec_align_size1;
1754
1755 #define EC_CMD_PWM_SET_DUTY 0x0025
1756
1757 #define EC_PWM_MAX_DUTY 0xffff
1758
1759 enum ec_pwm_type {
1760
1761 EC_PWM_TYPE_GENERIC = 0,
1762
1763 EC_PWM_TYPE_KB_LIGHT,
1764
1765 EC_PWM_TYPE_DISPLAY_LIGHT,
1766 EC_PWM_TYPE_COUNT,
1767 };
1768
1769 struct ec_params_pwm_set_duty {
1770 uint16_t duty;
1771 uint8_t pwm_type;
1772 uint8_t index;
1773 } __ec_align4;
1774
1775 #define EC_CMD_PWM_GET_DUTY 0x0026
1776
1777 struct ec_params_pwm_get_duty {
1778 uint8_t pwm_type;
1779 uint8_t index;
1780 } __ec_align1;
1781
1782 struct ec_response_pwm_get_duty {
1783 uint16_t duty;
1784 } __ec_align2;
1785
1786
1787
1788
1789
1790
1791
1792
1793 #define EC_CMD_LIGHTBAR_CMD 0x0028
1794
1795 struct rgb_s {
1796 uint8_t r, g, b;
1797 } __ec_todo_unpacked;
1798
1799 #define LB_BATTERY_LEVELS 4
1800
1801
1802
1803
1804
1805 struct lightbar_params_v0 {
1806
1807 int32_t google_ramp_up;
1808 int32_t google_ramp_down;
1809 int32_t s3s0_ramp_up;
1810 int32_t s0_tick_delay[2];
1811 int32_t s0a_tick_delay[2];
1812 int32_t s0s3_ramp_down;
1813 int32_t s3_sleep_for;
1814 int32_t s3_ramp_up;
1815 int32_t s3_ramp_down;
1816
1817
1818 uint8_t new_s0;
1819 uint8_t osc_min[2];
1820 uint8_t osc_max[2];
1821 uint8_t w_ofs[2];
1822
1823
1824 uint8_t bright_bl_off_fixed[2];
1825 uint8_t bright_bl_on_min[2];
1826 uint8_t bright_bl_on_max[2];
1827
1828
1829 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1830
1831
1832 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1833 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1834
1835
1836 struct rgb_s color[8];
1837 } __ec_todo_packed;
1838
1839 struct lightbar_params_v1 {
1840
1841 int32_t google_ramp_up;
1842 int32_t google_ramp_down;
1843 int32_t s3s0_ramp_up;
1844 int32_t s0_tick_delay[2];
1845 int32_t s0a_tick_delay[2];
1846 int32_t s0s3_ramp_down;
1847 int32_t s3_sleep_for;
1848 int32_t s3_ramp_up;
1849 int32_t s3_ramp_down;
1850 int32_t s5_ramp_up;
1851 int32_t s5_ramp_down;
1852 int32_t tap_tick_delay;
1853 int32_t tap_gate_delay;
1854 int32_t tap_display_time;
1855
1856
1857 uint8_t tap_pct_red;
1858 uint8_t tap_pct_green;
1859 uint8_t tap_seg_min_on;
1860 uint8_t tap_seg_max_on;
1861 uint8_t tap_seg_osc;
1862 uint8_t tap_idx[3];
1863
1864
1865 uint8_t osc_min[2];
1866 uint8_t osc_max[2];
1867 uint8_t w_ofs[2];
1868
1869
1870 uint8_t bright_bl_off_fixed[2];
1871 uint8_t bright_bl_on_min[2];
1872 uint8_t bright_bl_on_max[2];
1873
1874
1875 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1876
1877
1878 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1879 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1880
1881
1882 uint8_t s5_idx;
1883
1884
1885 struct rgb_s color[8];
1886 } __ec_todo_packed;
1887
1888
1889
1890
1891
1892
1893
1894
1895
1896
1897 struct lightbar_params_v2_timing {
1898
1899 int32_t google_ramp_up;
1900 int32_t google_ramp_down;
1901 int32_t s3s0_ramp_up;
1902 int32_t s0_tick_delay[2];
1903 int32_t s0a_tick_delay[2];
1904 int32_t s0s3_ramp_down;
1905 int32_t s3_sleep_for;
1906 int32_t s3_ramp_up;
1907 int32_t s3_ramp_down;
1908 int32_t s5_ramp_up;
1909 int32_t s5_ramp_down;
1910 int32_t tap_tick_delay;
1911 int32_t tap_gate_delay;
1912 int32_t tap_display_time;
1913 } __ec_todo_packed;
1914
1915 struct lightbar_params_v2_tap {
1916
1917 uint8_t tap_pct_red;
1918 uint8_t tap_pct_green;
1919 uint8_t tap_seg_min_on;
1920 uint8_t tap_seg_max_on;
1921 uint8_t tap_seg_osc;
1922 uint8_t tap_idx[3];
1923 } __ec_todo_packed;
1924
1925 struct lightbar_params_v2_oscillation {
1926
1927 uint8_t osc_min[2];
1928 uint8_t osc_max[2];
1929 uint8_t w_ofs[2];
1930 } __ec_todo_packed;
1931
1932 struct lightbar_params_v2_brightness {
1933
1934 uint8_t bright_bl_off_fixed[2];
1935 uint8_t bright_bl_on_min[2];
1936 uint8_t bright_bl_on_max[2];
1937 } __ec_todo_packed;
1938
1939 struct lightbar_params_v2_thresholds {
1940
1941 uint8_t battery_threshold[LB_BATTERY_LEVELS - 1];
1942 } __ec_todo_packed;
1943
1944 struct lightbar_params_v2_colors {
1945
1946 uint8_t s0_idx[2][LB_BATTERY_LEVELS];
1947 uint8_t s3_idx[2][LB_BATTERY_LEVELS];
1948
1949
1950 uint8_t s5_idx;
1951
1952
1953 struct rgb_s color[8];
1954 } __ec_todo_packed;
1955
1956
1957 #define EC_LB_PROG_LEN 192
1958 struct lightbar_program {
1959 uint8_t size;
1960 uint8_t data[EC_LB_PROG_LEN];
1961 } __ec_todo_unpacked;
1962
1963 struct ec_params_lightbar {
1964 uint8_t cmd;
1965 union {
1966
1967
1968
1969
1970
1971
1972
1973
1974
1975
1976
1977
1978 struct __ec_todo_unpacked {
1979 uint8_t num;
1980 } set_brightness, seq, demo;
1981
1982 struct __ec_todo_unpacked {
1983 uint8_t ctrl, reg, value;
1984 } reg;
1985
1986 struct __ec_todo_unpacked {
1987 uint8_t led, red, green, blue;
1988 } set_rgb;
1989
1990 struct __ec_todo_unpacked {
1991 uint8_t led;
1992 } get_rgb;
1993
1994 struct __ec_todo_unpacked {
1995 uint8_t enable;
1996 } manual_suspend_ctrl;
1997
1998 struct lightbar_params_v0 set_params_v0;
1999 struct lightbar_params_v1 set_params_v1;
2000
2001 struct lightbar_params_v2_timing set_v2par_timing;
2002 struct lightbar_params_v2_tap set_v2par_tap;
2003 struct lightbar_params_v2_oscillation set_v2par_osc;
2004 struct lightbar_params_v2_brightness set_v2par_bright;
2005 struct lightbar_params_v2_thresholds set_v2par_thlds;
2006 struct lightbar_params_v2_colors set_v2par_colors;
2007
2008 struct lightbar_program set_program;
2009 };
2010 } __ec_todo_packed;
2011
2012 struct ec_response_lightbar {
2013 union {
2014 struct __ec_todo_unpacked {
2015 struct __ec_todo_unpacked {
2016 uint8_t reg;
2017 uint8_t ic0;
2018 uint8_t ic1;
2019 } vals[23];
2020 } dump;
2021
2022 struct __ec_todo_unpacked {
2023 uint8_t num;
2024 } get_seq, get_brightness, get_demo;
2025
2026 struct lightbar_params_v0 get_params_v0;
2027 struct lightbar_params_v1 get_params_v1;
2028
2029
2030 struct lightbar_params_v2_timing get_params_v2_timing;
2031 struct lightbar_params_v2_tap get_params_v2_tap;
2032 struct lightbar_params_v2_oscillation get_params_v2_osc;
2033 struct lightbar_params_v2_brightness get_params_v2_bright;
2034 struct lightbar_params_v2_thresholds get_params_v2_thlds;
2035 struct lightbar_params_v2_colors get_params_v2_colors;
2036
2037 struct __ec_todo_unpacked {
2038 uint32_t num;
2039 uint32_t flags;
2040 } version;
2041
2042 struct __ec_todo_unpacked {
2043 uint8_t red, green, blue;
2044 } get_rgb;
2045
2046
2047
2048
2049
2050
2051
2052
2053
2054
2055 };
2056 } __ec_todo_packed;
2057
2058
2059 enum lightbar_command {
2060 LIGHTBAR_CMD_DUMP = 0,
2061 LIGHTBAR_CMD_OFF = 1,
2062 LIGHTBAR_CMD_ON = 2,
2063 LIGHTBAR_CMD_INIT = 3,
2064 LIGHTBAR_CMD_SET_BRIGHTNESS = 4,
2065 LIGHTBAR_CMD_SEQ = 5,
2066 LIGHTBAR_CMD_REG = 6,
2067 LIGHTBAR_CMD_SET_RGB = 7,
2068 LIGHTBAR_CMD_GET_SEQ = 8,
2069 LIGHTBAR_CMD_DEMO = 9,
2070 LIGHTBAR_CMD_GET_PARAMS_V0 = 10,
2071 LIGHTBAR_CMD_SET_PARAMS_V0 = 11,
2072 LIGHTBAR_CMD_VERSION = 12,
2073 LIGHTBAR_CMD_GET_BRIGHTNESS = 13,
2074 LIGHTBAR_CMD_GET_RGB = 14,
2075 LIGHTBAR_CMD_GET_DEMO = 15,
2076 LIGHTBAR_CMD_GET_PARAMS_V1 = 16,
2077 LIGHTBAR_CMD_SET_PARAMS_V1 = 17,
2078 LIGHTBAR_CMD_SET_PROGRAM = 18,
2079 LIGHTBAR_CMD_MANUAL_SUSPEND_CTRL = 19,
2080 LIGHTBAR_CMD_SUSPEND = 20,
2081 LIGHTBAR_CMD_RESUME = 21,
2082 LIGHTBAR_CMD_GET_PARAMS_V2_TIMING = 22,
2083 LIGHTBAR_CMD_SET_PARAMS_V2_TIMING = 23,
2084 LIGHTBAR_CMD_GET_PARAMS_V2_TAP = 24,
2085 LIGHTBAR_CMD_SET_PARAMS_V2_TAP = 25,
2086 LIGHTBAR_CMD_GET_PARAMS_V2_OSCILLATION = 26,
2087 LIGHTBAR_CMD_SET_PARAMS_V2_OSCILLATION = 27,
2088 LIGHTBAR_CMD_GET_PARAMS_V2_BRIGHTNESS = 28,
2089 LIGHTBAR_CMD_SET_PARAMS_V2_BRIGHTNESS = 29,
2090 LIGHTBAR_CMD_GET_PARAMS_V2_THRESHOLDS = 30,
2091 LIGHTBAR_CMD_SET_PARAMS_V2_THRESHOLDS = 31,
2092 LIGHTBAR_CMD_GET_PARAMS_V2_COLORS = 32,
2093 LIGHTBAR_CMD_SET_PARAMS_V2_COLORS = 33,
2094 LIGHTBAR_NUM_CMDS
2095 };
2096
2097
2098
2099
2100 #define EC_CMD_LED_CONTROL 0x0029
2101
2102 enum ec_led_id {
2103
2104 EC_LED_ID_BATTERY_LED = 0,
2105
2106
2107
2108
2109 EC_LED_ID_POWER_LED,
2110
2111 EC_LED_ID_ADAPTER_LED,
2112
2113 EC_LED_ID_LEFT_LED,
2114
2115 EC_LED_ID_RIGHT_LED,
2116
2117 EC_LED_ID_RECOVERY_HW_REINIT_LED,
2118
2119 EC_LED_ID_SYSRQ_DEBUG_LED,
2120
2121 EC_LED_ID_COUNT
2122 };
2123
2124
2125 #define EC_LED_FLAGS_QUERY BIT(0)
2126 #define EC_LED_FLAGS_AUTO BIT(1)
2127
2128 enum ec_led_colors {
2129 EC_LED_COLOR_RED = 0,
2130 EC_LED_COLOR_GREEN,
2131 EC_LED_COLOR_BLUE,
2132 EC_LED_COLOR_YELLOW,
2133 EC_LED_COLOR_WHITE,
2134 EC_LED_COLOR_AMBER,
2135
2136 EC_LED_COLOR_COUNT
2137 };
2138
2139 struct ec_params_led_control {
2140 uint8_t led_id;
2141 uint8_t flags;
2142
2143 uint8_t brightness[EC_LED_COLOR_COUNT];
2144 } __ec_align1;
2145
2146 struct ec_response_led_control {
2147
2148
2149
2150
2151
2152
2153
2154 uint8_t brightness_range[EC_LED_COLOR_COUNT];
2155 } __ec_align1;
2156
2157
2158
2159
2160
2161
2162
2163
2164
2165
2166 #define EC_CMD_VBOOT_HASH 0x002A
2167
2168 struct ec_params_vboot_hash {
2169 uint8_t cmd;
2170 uint8_t hash_type;
2171 uint8_t nonce_size;
2172 uint8_t reserved0;
2173 uint32_t offset;
2174 uint32_t size;
2175 uint8_t nonce_data[64];
2176 } __ec_align4;
2177
2178 struct ec_response_vboot_hash {
2179 uint8_t status;
2180 uint8_t hash_type;
2181 uint8_t digest_size;
2182 uint8_t reserved0;
2183 uint32_t offset;
2184 uint32_t size;
2185 uint8_t hash_digest[64];
2186 } __ec_align4;
2187
2188 enum ec_vboot_hash_cmd {
2189 EC_VBOOT_HASH_GET = 0,
2190 EC_VBOOT_HASH_ABORT = 1,
2191 EC_VBOOT_HASH_START = 2,
2192 EC_VBOOT_HASH_RECALC = 3,
2193 };
2194
2195 enum ec_vboot_hash_type {
2196 EC_VBOOT_HASH_TYPE_SHA256 = 0,
2197 };
2198
2199 enum ec_vboot_hash_status {
2200 EC_VBOOT_HASH_STATUS_NONE = 0,
2201 EC_VBOOT_HASH_STATUS_DONE = 1,
2202 EC_VBOOT_HASH_STATUS_BUSY = 2,
2203 };
2204
2205
2206
2207
2208
2209
2210 #define EC_VBOOT_HASH_OFFSET_RO 0xfffffffe
2211 #define EC_VBOOT_HASH_OFFSET_ACTIVE 0xfffffffd
2212 #define EC_VBOOT_HASH_OFFSET_UPDATE 0xfffffffc
2213
2214
2215
2216
2217
2218 #define EC_VBOOT_HASH_OFFSET_RW EC_VBOOT_HASH_OFFSET_ACTIVE
2219
2220
2221
2222
2223
2224
2225 #define EC_CMD_MOTION_SENSE_CMD 0x002B
2226
2227
2228 enum motionsense_command {
2229
2230
2231
2232
2233 MOTIONSENSE_CMD_DUMP = 0,
2234
2235
2236
2237
2238
2239
2240 MOTIONSENSE_CMD_INFO = 1,
2241
2242
2243
2244
2245
2246
2247
2248
2249
2250
2251
2252 MOTIONSENSE_CMD_EC_RATE = 2,
2253
2254
2255
2256
2257
2258 MOTIONSENSE_CMD_SENSOR_ODR = 3,
2259
2260
2261
2262
2263
2264 MOTIONSENSE_CMD_SENSOR_RANGE = 4,
2265
2266
2267
2268
2269
2270
2271
2272
2273 MOTIONSENSE_CMD_KB_WAKE_ANGLE = 5,
2274
2275
2276
2277
2278 MOTIONSENSE_CMD_DATA = 6,
2279
2280
2281
2282
2283 MOTIONSENSE_CMD_FIFO_INFO = 7,
2284
2285
2286
2287
2288
2289 MOTIONSENSE_CMD_FIFO_FLUSH = 8,
2290
2291
2292
2293
2294 MOTIONSENSE_CMD_FIFO_READ = 9,
2295
2296
2297
2298
2299
2300 MOTIONSENSE_CMD_PERFORM_CALIB = 10,
2301
2302
2303
2304
2305
2306
2307
2308 MOTIONSENSE_CMD_SENSOR_OFFSET = 11,
2309
2310
2311
2312
2313
2314 MOTIONSENSE_CMD_LIST_ACTIVITIES = 12,
2315
2316
2317
2318
2319
2320 MOTIONSENSE_CMD_SET_ACTIVITY = 13,
2321
2322
2323
2324
2325 MOTIONSENSE_CMD_LID_ANGLE = 14,
2326
2327
2328
2329
2330
2331
2332 MOTIONSENSE_CMD_FIFO_INT_ENABLE = 15,
2333
2334
2335
2336
2337
2338 MOTIONSENSE_CMD_SPOOF = 16,
2339
2340
2341 MOTIONSENSE_CMD_TABLET_MODE_LID_ANGLE = 17,
2342
2343
2344
2345
2346
2347 MOTIONSENSE_CMD_SENSOR_SCALE = 18,
2348
2349
2350 MOTIONSENSE_NUM_CMDS
2351 };
2352
2353
2354 enum motionsensor_type {
2355 MOTIONSENSE_TYPE_ACCEL = 0,
2356 MOTIONSENSE_TYPE_GYRO = 1,
2357 MOTIONSENSE_TYPE_MAG = 2,
2358 MOTIONSENSE_TYPE_PROX = 3,
2359 MOTIONSENSE_TYPE_LIGHT = 4,
2360 MOTIONSENSE_TYPE_ACTIVITY = 5,
2361 MOTIONSENSE_TYPE_BARO = 6,
2362 MOTIONSENSE_TYPE_SYNC = 7,
2363 MOTIONSENSE_TYPE_MAX,
2364 };
2365
2366
2367 enum motionsensor_location {
2368 MOTIONSENSE_LOC_BASE = 0,
2369 MOTIONSENSE_LOC_LID = 1,
2370 MOTIONSENSE_LOC_CAMERA = 2,
2371 MOTIONSENSE_LOC_MAX,
2372 };
2373
2374
2375 enum motionsensor_chip {
2376 MOTIONSENSE_CHIP_KXCJ9 = 0,
2377 MOTIONSENSE_CHIP_LSM6DS0 = 1,
2378 MOTIONSENSE_CHIP_BMI160 = 2,
2379 MOTIONSENSE_CHIP_SI1141 = 3,
2380 MOTIONSENSE_CHIP_SI1142 = 4,
2381 MOTIONSENSE_CHIP_SI1143 = 5,
2382 MOTIONSENSE_CHIP_KX022 = 6,
2383 MOTIONSENSE_CHIP_L3GD20H = 7,
2384 MOTIONSENSE_CHIP_BMA255 = 8,
2385 MOTIONSENSE_CHIP_BMP280 = 9,
2386 MOTIONSENSE_CHIP_OPT3001 = 10,
2387 MOTIONSENSE_CHIP_BH1730 = 11,
2388 MOTIONSENSE_CHIP_GPIO = 12,
2389 MOTIONSENSE_CHIP_LIS2DH = 13,
2390 MOTIONSENSE_CHIP_LSM6DSM = 14,
2391 MOTIONSENSE_CHIP_LIS2DE = 15,
2392 MOTIONSENSE_CHIP_LIS2MDL = 16,
2393 MOTIONSENSE_CHIP_LSM6DS3 = 17,
2394 MOTIONSENSE_CHIP_LSM6DSO = 18,
2395 MOTIONSENSE_CHIP_LNG2DM = 19,
2396 MOTIONSENSE_CHIP_MAX,
2397 };
2398
2399
2400 enum motionsensor_orientation {
2401 MOTIONSENSE_ORIENTATION_LANDSCAPE = 0,
2402 MOTIONSENSE_ORIENTATION_PORTRAIT = 1,
2403 MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_PORTRAIT = 2,
2404 MOTIONSENSE_ORIENTATION_UPSIDE_DOWN_LANDSCAPE = 3,
2405 MOTIONSENSE_ORIENTATION_UNKNOWN = 4,
2406 };
2407
2408 struct ec_response_motion_sensor_data {
2409
2410 uint8_t flags;
2411
2412 uint8_t sensor_num;
2413
2414 union {
2415 int16_t data[3];
2416 struct __ec_todo_packed {
2417 uint16_t reserved;
2418 uint32_t timestamp;
2419 };
2420 struct __ec_todo_unpacked {
2421 uint8_t activity;
2422 uint8_t state;
2423 int16_t add_info[2];
2424 };
2425 };
2426 } __ec_todo_packed;
2427
2428
2429 struct ec_response_motion_sense_fifo_info {
2430
2431 uint16_t size;
2432
2433 uint16_t count;
2434
2435
2436
2437 uint32_t timestamp;
2438
2439 uint16_t total_lost;
2440
2441 uint16_t lost[];
2442 } __ec_todo_packed;
2443
2444 struct ec_response_motion_sense_fifo_data {
2445 uint32_t number_data;
2446 struct ec_response_motion_sensor_data data[];
2447 } __ec_todo_packed;
2448
2449
2450 enum motionsensor_activity {
2451 MOTIONSENSE_ACTIVITY_RESERVED = 0,
2452 MOTIONSENSE_ACTIVITY_SIG_MOTION = 1,
2453 MOTIONSENSE_ACTIVITY_DOUBLE_TAP = 2,
2454 MOTIONSENSE_ACTIVITY_ORIENTATION = 3,
2455 };
2456
2457 struct ec_motion_sense_activity {
2458 uint8_t sensor_num;
2459 uint8_t activity;
2460 uint8_t enable;
2461 uint8_t reserved;
2462 uint16_t parameters[3];
2463 } __ec_todo_unpacked;
2464
2465
2466 #define MOTIONSENSE_MODULE_FLAG_ACTIVE BIT(0)
2467
2468
2469 #define MOTIONSENSE_SENSOR_FLAG_PRESENT BIT(0)
2470
2471
2472
2473
2474
2475 #define MOTIONSENSE_SENSOR_FLAG_FLUSH BIT(0)
2476 #define MOTIONSENSE_SENSOR_FLAG_TIMESTAMP BIT(1)
2477 #define MOTIONSENSE_SENSOR_FLAG_WAKEUP BIT(2)
2478 #define MOTIONSENSE_SENSOR_FLAG_TABLET_MODE BIT(3)
2479 #define MOTIONSENSE_SENSOR_FLAG_ODR BIT(4)
2480
2481
2482
2483
2484
2485
2486 #define EC_MOTION_SENSE_NO_VALUE -1
2487
2488 #define EC_MOTION_SENSE_INVALID_CALIB_TEMP 0x8000
2489
2490
2491
2492 #define MOTION_SENSE_SET_OFFSET BIT(0)
2493
2494
2495 #define MOTION_SENSE_DEFAULT_SCALE BIT(15)
2496
2497 #define LID_ANGLE_UNRELIABLE 500
2498
2499 enum motionsense_spoof_mode {
2500
2501 MOTIONSENSE_SPOOF_MODE_DISABLE = 0,
2502
2503
2504 MOTIONSENSE_SPOOF_MODE_CUSTOM,
2505
2506
2507 MOTIONSENSE_SPOOF_MODE_LOCK_CURRENT,
2508
2509
2510 MOTIONSENSE_SPOOF_MODE_QUERY,
2511 };
2512
2513 struct ec_params_motion_sense {
2514 uint8_t cmd;
2515 union {
2516
2517 struct __ec_todo_unpacked {
2518
2519
2520
2521
2522
2523 uint8_t max_sensor_count;
2524 } dump;
2525
2526
2527
2528
2529 struct __ec_todo_unpacked {
2530
2531
2532
2533 int16_t data;
2534 } kb_wake_angle;
2535
2536
2537
2538
2539
2540 struct __ec_todo_unpacked {
2541 uint8_t sensor_num;
2542 } info, info_3, data, fifo_flush, perform_calib,
2543 list_activities;
2544
2545
2546
2547
2548
2549 struct __ec_todo_unpacked {
2550 uint8_t sensor_num;
2551
2552
2553 uint8_t roundup;
2554
2555 uint16_t reserved;
2556
2557
2558 int32_t data;
2559 } ec_rate, sensor_odr, sensor_range;
2560
2561
2562 struct __ec_todo_packed {
2563 uint8_t sensor_num;
2564
2565
2566
2567
2568
2569
2570 uint16_t flags;
2571
2572
2573
2574
2575
2576
2577
2578 int16_t temp;
2579
2580
2581
2582
2583
2584
2585
2586
2587 int16_t offset[3];
2588 } sensor_offset;
2589
2590
2591 struct __ec_todo_packed {
2592 uint8_t sensor_num;
2593
2594
2595
2596
2597
2598
2599 uint16_t flags;
2600
2601
2602
2603
2604
2605
2606
2607 int16_t temp;
2608
2609
2610
2611
2612
2613
2614
2615
2616 uint16_t scale[3];
2617 } sensor_scale;
2618
2619
2620
2621
2622
2623
2624 struct __ec_todo_unpacked {
2625
2626
2627
2628
2629 uint32_t max_data_vector;
2630 } fifo_read;
2631
2632 struct ec_motion_sense_activity set_activity;
2633
2634
2635
2636
2637
2638 struct __ec_todo_unpacked {
2639
2640
2641
2642
2643 int8_t enable;
2644 } fifo_int_enable;
2645
2646
2647 struct __ec_todo_packed {
2648 uint8_t sensor_id;
2649
2650
2651 uint8_t spoof_enable;
2652
2653
2654 uint8_t reserved;
2655
2656
2657 int16_t components[3];
2658 } spoof;
2659
2660
2661 struct __ec_todo_unpacked {
2662
2663
2664
2665
2666 int16_t lid_angle;
2667
2668
2669
2670
2671
2672
2673
2674
2675 int16_t hys_degree;
2676 } tablet_mode_threshold;
2677 };
2678 } __ec_todo_packed;
2679
2680 struct ec_response_motion_sense {
2681 union {
2682
2683 struct __ec_todo_unpacked {
2684
2685 uint8_t module_flags;
2686
2687
2688 uint8_t sensor_count;
2689
2690
2691
2692
2693
2694 struct ec_response_motion_sensor_data sensor[0];
2695 } dump;
2696
2697
2698 struct __ec_todo_unpacked {
2699
2700 uint8_t type;
2701
2702
2703 uint8_t location;
2704
2705
2706 uint8_t chip;
2707 } info;
2708
2709
2710 struct __ec_todo_unpacked {
2711
2712 uint8_t type;
2713
2714
2715 uint8_t location;
2716
2717
2718 uint8_t chip;
2719
2720
2721 uint32_t min_frequency;
2722
2723
2724 uint32_t max_frequency;
2725
2726
2727 uint32_t fifo_max_event_count;
2728 } info_3;
2729
2730
2731 struct ec_response_motion_sensor_data data;
2732
2733
2734
2735
2736
2737
2738
2739
2740 struct __ec_todo_unpacked {
2741
2742 int32_t ret;
2743 } ec_rate, sensor_odr, sensor_range, kb_wake_angle,
2744 fifo_int_enable, spoof;
2745
2746
2747
2748
2749
2750 struct __ec_todo_unpacked {
2751 int16_t temp;
2752 int16_t offset[3];
2753 } sensor_offset, perform_calib;
2754
2755
2756 struct __ec_todo_unpacked {
2757 int16_t temp;
2758 uint16_t scale[3];
2759 } sensor_scale;
2760
2761 struct ec_response_motion_sense_fifo_info fifo_info, fifo_flush;
2762
2763 struct ec_response_motion_sense_fifo_data fifo_read;
2764
2765 struct __ec_todo_packed {
2766 uint16_t reserved;
2767 uint32_t enabled;
2768 uint32_t disabled;
2769 } list_activities;
2770
2771
2772
2773
2774 struct __ec_todo_unpacked {
2775
2776
2777
2778
2779 uint16_t value;
2780 } lid_angle;
2781
2782
2783 struct __ec_todo_unpacked {
2784
2785
2786
2787
2788 uint16_t lid_angle;
2789
2790
2791 uint16_t hys_degree;
2792 } tablet_mode_threshold;
2793
2794 };
2795 } __ec_todo_packed;
2796
2797
2798
2799
2800
2801 #define EC_CMD_FORCE_LID_OPEN 0x002C
2802
2803 struct ec_params_force_lid_open {
2804 uint8_t enabled;
2805 } __ec_align1;
2806
2807
2808
2809 #define EC_CMD_CONFIG_POWER_BUTTON 0x002D
2810
2811 enum ec_config_power_button_flags {
2812
2813 EC_POWER_BUTTON_ENABLE_PULSE = BIT(0),
2814 };
2815
2816 struct ec_params_config_power_button {
2817
2818 uint8_t flags;
2819 } __ec_align1;
2820
2821
2822
2823
2824
2825 #define EC_CMD_USB_CHARGE_SET_MODE 0x0030
2826
2827 struct ec_params_usb_charge_set_mode {
2828 uint8_t usb_port_id;
2829 uint8_t mode:7;
2830 uint8_t inhibit_charge:1;
2831 } __ec_align1;
2832
2833
2834
2835
2836
2837 #define EC_PSTORE_SIZE_MAX 64
2838
2839
2840 #define EC_CMD_PSTORE_INFO 0x0040
2841
2842 struct ec_response_pstore_info {
2843
2844 uint32_t pstore_size;
2845
2846 uint32_t access_size;
2847 } __ec_align4;
2848
2849
2850
2851
2852
2853
2854 #define EC_CMD_PSTORE_READ 0x0041
2855
2856 struct ec_params_pstore_read {
2857 uint32_t offset;
2858 uint32_t size;
2859 } __ec_align4;
2860
2861
2862 #define EC_CMD_PSTORE_WRITE 0x0042
2863
2864 struct ec_params_pstore_write {
2865 uint32_t offset;
2866 uint32_t size;
2867 uint8_t data[EC_PSTORE_SIZE_MAX];
2868 } __ec_align4;
2869
2870
2871
2872
2873
2874 struct ec_params_rtc {
2875 uint32_t time;
2876 } __ec_align4;
2877
2878 struct ec_response_rtc {
2879 uint32_t time;
2880 } __ec_align4;
2881
2882
2883 #define EC_CMD_RTC_GET_VALUE 0x0044
2884 #define EC_CMD_RTC_GET_ALARM 0x0045
2885
2886
2887 #define EC_CMD_RTC_SET_VALUE 0x0046
2888 #define EC_CMD_RTC_SET_ALARM 0x0047
2889
2890
2891 #define EC_RTC_ALARM_CLEAR 0
2892
2893
2894
2895
2896
2897 #define EC_PORT80_SIZE_MAX 32
2898
2899
2900 #define EC_CMD_PORT80_LAST_BOOT 0x0048
2901 #define EC_CMD_PORT80_READ 0x0048
2902
2903 enum ec_port80_subcmd {
2904 EC_PORT80_GET_INFO = 0,
2905 EC_PORT80_READ_BUFFER,
2906 };
2907
2908 struct ec_params_port80_read {
2909 uint16_t subcmd;
2910 union {
2911 struct __ec_todo_unpacked {
2912 uint32_t offset;
2913 uint32_t num_entries;
2914 } read_buffer;
2915 };
2916 } __ec_todo_packed;
2917
2918 struct ec_response_port80_read {
2919 union {
2920 struct __ec_todo_unpacked {
2921 uint32_t writes;
2922 uint32_t history_size;
2923 uint32_t last_boot;
2924 } get_info;
2925 struct __ec_todo_unpacked {
2926 uint16_t codes[EC_PORT80_SIZE_MAX];
2927 } data;
2928 };
2929 } __ec_todo_packed;
2930
2931 struct ec_response_port80_last_boot {
2932 uint16_t code;
2933 } __ec_align2;
2934
2935
2936
2937
2938
2939 #define EC_VSTORE_SLOT_SIZE 64
2940
2941
2942 #define EC_VSTORE_SLOT_MAX 32
2943
2944
2945 #define EC_CMD_VSTORE_INFO 0x0049
2946 struct ec_response_vstore_info {
2947
2948 uint32_t slot_locked;
2949
2950 uint8_t slot_count;
2951 } __ec_align_size1;
2952
2953
2954
2955
2956
2957
2958 #define EC_CMD_VSTORE_READ 0x004A
2959
2960 struct ec_params_vstore_read {
2961 uint8_t slot;
2962 } __ec_align1;
2963
2964 struct ec_response_vstore_read {
2965 uint8_t data[EC_VSTORE_SLOT_SIZE];
2966 } __ec_align1;
2967
2968
2969
2970
2971 #define EC_CMD_VSTORE_WRITE 0x004B
2972
2973 struct ec_params_vstore_write {
2974 uint8_t slot;
2975 uint8_t data[EC_VSTORE_SLOT_SIZE];
2976 } __ec_align1;
2977
2978
2979
2980
2981
2982
2983
2984
2985 #define EC_CMD_THERMAL_SET_THRESHOLD 0x0050
2986 #define EC_CMD_THERMAL_GET_THRESHOLD 0x0051
2987
2988
2989
2990
2991
2992
2993 struct ec_params_thermal_set_threshold {
2994 uint8_t sensor_type;
2995 uint8_t threshold_id;
2996 uint16_t value;
2997 } __ec_align2;
2998
2999
3000 struct ec_params_thermal_get_threshold {
3001 uint8_t sensor_type;
3002 uint8_t threshold_id;
3003 } __ec_align1;
3004
3005 struct ec_response_thermal_get_threshold {
3006 uint16_t value;
3007 } __ec_align2;
3008
3009
3010
3011 enum ec_temp_thresholds {
3012 EC_TEMP_THRESH_WARN = 0,
3013 EC_TEMP_THRESH_HIGH,
3014 EC_TEMP_THRESH_HALT,
3015
3016 EC_TEMP_THRESH_COUNT
3017 };
3018
3019
3020
3021
3022
3023
3024
3025
3026
3027
3028
3029
3030
3031
3032
3033
3034
3035
3036
3037
3038
3039
3040
3041 struct ec_thermal_config {
3042 uint32_t temp_host[EC_TEMP_THRESH_COUNT];
3043 uint32_t temp_host_release[EC_TEMP_THRESH_COUNT];
3044 uint32_t temp_fan_off;
3045 uint32_t temp_fan_max;
3046 } __ec_align4;
3047
3048
3049 struct ec_params_thermal_get_threshold_v1 {
3050 uint32_t sensor_num;
3051 } __ec_align4;
3052
3053
3054
3055
3056
3057
3058 struct ec_params_thermal_set_threshold_v1 {
3059 uint32_t sensor_num;
3060 struct ec_thermal_config cfg;
3061 } __ec_align4;
3062
3063
3064
3065
3066
3067 #define EC_CMD_THERMAL_AUTO_FAN_CTRL 0x0052
3068
3069
3070 struct ec_params_auto_fan_ctrl_v1 {
3071 uint8_t fan_idx;
3072 } __ec_align1;
3073
3074
3075 #define EC_CMD_TMP006_GET_CALIBRATION 0x0053
3076 #define EC_CMD_TMP006_SET_CALIBRATION 0x0054
3077
3078
3079
3080
3081
3082
3083
3084
3085
3086
3087
3088 struct ec_params_tmp006_get_calibration {
3089 uint8_t index;
3090 } __ec_align1;
3091
3092
3093 struct ec_response_tmp006_get_calibration_v0 {
3094 float s0;
3095 float b0;
3096 float b1;
3097 float b2;
3098 } __ec_align4;
3099
3100 struct ec_params_tmp006_set_calibration_v0 {
3101 uint8_t index;
3102 uint8_t reserved[3];
3103 float s0;
3104 float b0;
3105 float b1;
3106 float b2;
3107 } __ec_align4;
3108
3109
3110 struct ec_response_tmp006_get_calibration_v1 {
3111 uint8_t algorithm;
3112 uint8_t num_params;
3113 uint8_t reserved[2];
3114 float val[];
3115 } __ec_align4;
3116
3117 struct ec_params_tmp006_set_calibration_v1 {
3118 uint8_t index;
3119 uint8_t algorithm;
3120 uint8_t num_params;
3121 uint8_t reserved;
3122 float val[];
3123 } __ec_align4;
3124
3125
3126
3127 #define EC_CMD_TMP006_GET_RAW 0x0055
3128
3129 struct ec_params_tmp006_get_raw {
3130 uint8_t index;
3131 } __ec_align1;
3132
3133 struct ec_response_tmp006_get_raw {
3134 int32_t t;
3135 int32_t v;
3136 } __ec_align4;
3137
3138
3139
3140
3141
3142
3143
3144
3145
3146
3147
3148
3149
3150
3151 #define EC_CMD_MKBP_STATE 0x0060
3152
3153
3154
3155
3156 #define EC_CMD_MKBP_INFO 0x0061
3157
3158 struct ec_response_mkbp_info {
3159 uint32_t rows;
3160 uint32_t cols;
3161
3162 uint8_t reserved;
3163 } __ec_align_size1;
3164
3165 struct ec_params_mkbp_info {
3166 uint8_t info_type;
3167 uint8_t event_type;
3168 } __ec_align1;
3169
3170 enum ec_mkbp_info_type {
3171
3172
3173
3174
3175
3176 EC_MKBP_INFO_KBD = 0,
3177
3178
3179
3180
3181
3182
3183
3184
3185
3186
3187 EC_MKBP_INFO_SUPPORTED = 1,
3188
3189
3190
3191
3192
3193
3194
3195
3196
3197
3198
3199
3200
3201
3202
3203
3204
3205
3206 EC_MKBP_INFO_CURRENT = 2,
3207 };
3208
3209
3210 #define EC_CMD_MKBP_SIMULATE_KEY 0x0062
3211
3212 struct ec_params_mkbp_simulate_key {
3213 uint8_t col;
3214 uint8_t row;
3215 uint8_t pressed;
3216 } __ec_align1;
3217
3218 #define EC_CMD_GET_KEYBOARD_ID 0x0063
3219
3220 struct ec_response_keyboard_id {
3221 uint32_t keyboard_id;
3222 } __ec_align4;
3223
3224 enum keyboard_id {
3225 KEYBOARD_ID_UNSUPPORTED = 0,
3226 KEYBOARD_ID_UNREADABLE = 0xffffffff,
3227 };
3228
3229
3230 #define EC_CMD_MKBP_SET_CONFIG 0x0064
3231 #define EC_CMD_MKBP_GET_CONFIG 0x0065
3232
3233
3234 enum mkbp_config_flags {
3235 EC_MKBP_FLAGS_ENABLE = 1,
3236 };
3237
3238 enum mkbp_config_valid {
3239 EC_MKBP_VALID_SCAN_PERIOD = BIT(0),
3240 EC_MKBP_VALID_POLL_TIMEOUT = BIT(1),
3241 EC_MKBP_VALID_MIN_POST_SCAN_DELAY = BIT(3),
3242 EC_MKBP_VALID_OUTPUT_SETTLE = BIT(4),
3243 EC_MKBP_VALID_DEBOUNCE_DOWN = BIT(5),
3244 EC_MKBP_VALID_DEBOUNCE_UP = BIT(6),
3245 EC_MKBP_VALID_FIFO_MAX_DEPTH = BIT(7),
3246 };
3247
3248
3249
3250
3251
3252
3253
3254 struct ec_mkbp_config {
3255 uint32_t valid_mask;
3256 uint8_t flags;
3257 uint8_t valid_flags;
3258 uint16_t scan_period_us;
3259
3260 uint32_t poll_timeout_us;
3261
3262
3263
3264
3265
3266 uint16_t min_post_scan_delay_us;
3267
3268 uint16_t output_settle_us;
3269 uint16_t debounce_down_us;
3270 uint16_t debounce_up_us;
3271
3272 uint8_t fifo_max_depth;
3273 } __ec_align_size1;
3274
3275 struct ec_params_mkbp_set_config {
3276 struct ec_mkbp_config config;
3277 } __ec_align_size1;
3278
3279 struct ec_response_mkbp_get_config {
3280 struct ec_mkbp_config config;
3281 } __ec_align_size1;
3282
3283
3284 #define EC_CMD_KEYSCAN_SEQ_CTRL 0x0066
3285
3286 enum ec_keyscan_seq_cmd {
3287 EC_KEYSCAN_SEQ_STATUS = 0,
3288 EC_KEYSCAN_SEQ_CLEAR = 1,
3289 EC_KEYSCAN_SEQ_ADD = 2,
3290 EC_KEYSCAN_SEQ_START = 3,
3291 EC_KEYSCAN_SEQ_COLLECT = 4,
3292 };
3293
3294 enum ec_collect_flags {
3295
3296
3297
3298
3299 EC_KEYSCAN_SEQ_FLAG_DONE = BIT(0),
3300 };
3301
3302 struct ec_collect_item {
3303 uint8_t flags;
3304 } __ec_align1;
3305
3306 struct ec_params_keyscan_seq_ctrl {
3307 uint8_t cmd;
3308 union {
3309 struct __ec_align1 {
3310 uint8_t active;
3311 uint8_t num_items;
3312
3313 uint8_t cur_item;
3314 } status;
3315 struct __ec_todo_unpacked {
3316
3317
3318
3319
3320 uint32_t time_us;
3321 uint8_t scan[0];
3322 } add;
3323 struct __ec_align1 {
3324 uint8_t start_item;
3325 uint8_t num_items;
3326 } collect;
3327 };
3328 } __ec_todo_packed;
3329
3330 struct ec_result_keyscan_seq_ctrl {
3331 union {
3332 struct __ec_todo_unpacked {
3333 uint8_t num_items;
3334
3335 struct ec_collect_item item[0];
3336 } collect;
3337 };
3338 } __ec_todo_packed;
3339
3340
3341
3342
3343
3344
3345 #define EC_CMD_GET_NEXT_EVENT 0x0067
3346
3347 #define EC_MKBP_HAS_MORE_EVENTS_SHIFT 7
3348
3349
3350
3351
3352
3353 #define EC_MKBP_HAS_MORE_EVENTS BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT)
3354
3355
3356 #define EC_MKBP_EVENT_TYPE_MASK (BIT(EC_MKBP_HAS_MORE_EVENTS_SHIFT) - 1)
3357
3358 enum ec_mkbp_event {
3359
3360 EC_MKBP_EVENT_KEY_MATRIX = 0,
3361
3362
3363 EC_MKBP_EVENT_HOST_EVENT = 1,
3364
3365
3366 EC_MKBP_EVENT_SENSOR_FIFO = 2,
3367
3368
3369 EC_MKBP_EVENT_BUTTON = 3,
3370
3371
3372 EC_MKBP_EVENT_SWITCH = 4,
3373
3374
3375 EC_MKBP_EVENT_FINGERPRINT = 5,
3376
3377
3378
3379
3380
3381 EC_MKBP_EVENT_SYSRQ = 6,
3382
3383
3384
3385
3386
3387 EC_MKBP_EVENT_HOST_EVENT64 = 7,
3388
3389
3390 EC_MKBP_EVENT_CEC_EVENT = 8,
3391
3392
3393 EC_MKBP_EVENT_CEC_MESSAGE = 9,
3394
3395
3396 EC_MKBP_EVENT_PCHG = 12,
3397
3398
3399 EC_MKBP_EVENT_COUNT,
3400 };
3401 BUILD_ASSERT(EC_MKBP_EVENT_COUNT <= EC_MKBP_EVENT_TYPE_MASK);
3402
3403 union __ec_align_offset1 ec_response_get_next_data {
3404 uint8_t key_matrix[13];
3405
3406
3407 uint32_t host_event;
3408 uint64_t host_event64;
3409
3410 struct __ec_todo_unpacked {
3411
3412 uint8_t reserved[3];
3413 struct ec_response_motion_sense_fifo_info info;
3414 } sensor_fifo;
3415
3416 uint32_t buttons;
3417
3418 uint32_t switches;
3419
3420 uint32_t fp_events;
3421
3422 uint32_t sysrq;
3423
3424
3425 uint32_t cec_events;
3426 };
3427
3428 union __ec_align_offset1 ec_response_get_next_data_v1 {
3429 uint8_t key_matrix[16];
3430
3431
3432 uint32_t host_event;
3433 uint64_t host_event64;
3434
3435 struct __ec_todo_unpacked {
3436
3437 uint8_t reserved[3];
3438 struct ec_response_motion_sense_fifo_info info;
3439 } sensor_fifo;
3440
3441 uint32_t buttons;
3442
3443 uint32_t switches;
3444
3445 uint32_t fp_events;
3446
3447 uint32_t sysrq;
3448
3449
3450 uint32_t cec_events;
3451
3452 uint8_t cec_message[16];
3453 };
3454 BUILD_ASSERT(sizeof(union ec_response_get_next_data_v1) == 16);
3455
3456 struct ec_response_get_next_event {
3457 uint8_t event_type;
3458
3459 union ec_response_get_next_data data;
3460 } __ec_align1;
3461
3462 struct ec_response_get_next_event_v1 {
3463 uint8_t event_type;
3464
3465 union ec_response_get_next_data_v1 data;
3466 } __ec_align1;
3467
3468
3469
3470 #define EC_MKBP_POWER_BUTTON 0
3471 #define EC_MKBP_VOL_UP 1
3472 #define EC_MKBP_VOL_DOWN 2
3473 #define EC_MKBP_RECOVERY 3
3474
3475
3476 #define EC_MKBP_LID_OPEN 0
3477 #define EC_MKBP_TABLET_MODE 1
3478 #define EC_MKBP_BASE_ATTACHED 2
3479 #define EC_MKBP_FRONT_PROXIMITY 3
3480
3481
3482 #define EC_CMD_KEYBOARD_FACTORY_TEST 0x0068
3483
3484 struct ec_response_keyboard_factory_test {
3485 uint16_t shorted;
3486 } __ec_align2;
3487
3488
3489 #define EC_MKBP_FP_RAW_EVENT(fp_events) ((fp_events) & 0x00FFFFFF)
3490 #define EC_MKBP_FP_ERRCODE(fp_events) ((fp_events) & 0x0000000F)
3491 #define EC_MKBP_FP_ENROLL_PROGRESS_OFFSET 4
3492 #define EC_MKBP_FP_ENROLL_PROGRESS(fpe) (((fpe) & 0x00000FF0) \
3493 >> EC_MKBP_FP_ENROLL_PROGRESS_OFFSET)
3494 #define EC_MKBP_FP_MATCH_IDX_OFFSET 12
3495 #define EC_MKBP_FP_MATCH_IDX_MASK 0x0000F000
3496 #define EC_MKBP_FP_MATCH_IDX(fpe) (((fpe) & EC_MKBP_FP_MATCH_IDX_MASK) \
3497 >> EC_MKBP_FP_MATCH_IDX_OFFSET)
3498 #define EC_MKBP_FP_ENROLL BIT(27)
3499 #define EC_MKBP_FP_MATCH BIT(28)
3500 #define EC_MKBP_FP_FINGER_DOWN BIT(29)
3501 #define EC_MKBP_FP_FINGER_UP BIT(30)
3502 #define EC_MKBP_FP_IMAGE_READY BIT(31)
3503
3504 #define EC_MKBP_FP_ERR_ENROLL_OK 0
3505 #define EC_MKBP_FP_ERR_ENROLL_LOW_QUALITY 1
3506 #define EC_MKBP_FP_ERR_ENROLL_IMMOBILE 2
3507 #define EC_MKBP_FP_ERR_ENROLL_LOW_COVERAGE 3
3508 #define EC_MKBP_FP_ERR_ENROLL_INTERNAL 5
3509
3510 #define EC_MKBP_FP_ERR_ENROLL_PROBLEM_MASK 1
3511
3512 #define EC_MKBP_FP_ERR_MATCH_NO 0
3513 #define EC_MKBP_FP_ERR_MATCH_NO_INTERNAL 6
3514 #define EC_MKBP_FP_ERR_MATCH_NO_TEMPLATES 7
3515 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_QUALITY 2
3516 #define EC_MKBP_FP_ERR_MATCH_NO_LOW_COVERAGE 4
3517 #define EC_MKBP_FP_ERR_MATCH_YES 1
3518 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATED 3
3519 #define EC_MKBP_FP_ERR_MATCH_YES_UPDATE_FAILED 5
3520
3521
3522
3523
3524
3525
3526 #define EC_CMD_TEMP_SENSOR_GET_INFO 0x0070
3527
3528 struct ec_params_temp_sensor_get_info {
3529 uint8_t id;
3530 } __ec_align1;
3531
3532 struct ec_response_temp_sensor_get_info {
3533 char sensor_name[32];
3534 uint8_t sensor_type;
3535 } __ec_align1;
3536
3537
3538
3539
3540
3541
3542
3543
3544
3545
3546
3547
3548
3549
3550
3551
3552
3553
3554 struct ec_params_host_event_mask {
3555 uint32_t mask;
3556 } __ec_align4;
3557
3558 struct ec_response_host_event_mask {
3559 uint32_t mask;
3560 } __ec_align4;
3561
3562
3563 #define EC_CMD_HOST_EVENT_GET_B 0x0087
3564 #define EC_CMD_HOST_EVENT_GET_SMI_MASK 0x0088
3565 #define EC_CMD_HOST_EVENT_GET_SCI_MASK 0x0089
3566 #define EC_CMD_HOST_EVENT_GET_WAKE_MASK 0x008D
3567
3568
3569 #define EC_CMD_HOST_EVENT_SET_SMI_MASK 0x008A
3570 #define EC_CMD_HOST_EVENT_SET_SCI_MASK 0x008B
3571 #define EC_CMD_HOST_EVENT_CLEAR 0x008C
3572 #define EC_CMD_HOST_EVENT_SET_WAKE_MASK 0x008E
3573 #define EC_CMD_HOST_EVENT_CLEAR_B 0x008F
3574
3575
3576
3577
3578
3579
3580 struct ec_params_host_event {
3581
3582
3583 uint8_t action;
3584
3585
3586
3587
3588
3589 uint8_t mask_type;
3590
3591
3592 uint16_t reserved;
3593
3594
3595 uint64_t value;
3596 } __ec_align4;
3597
3598
3599
3600
3601
3602
3603 struct ec_response_host_event {
3604
3605
3606 uint64_t value;
3607 } __ec_align4;
3608
3609 enum ec_host_event_action {
3610
3611
3612
3613
3614 EC_HOST_EVENT_GET,
3615
3616
3617 EC_HOST_EVENT_SET,
3618
3619
3620 EC_HOST_EVENT_CLEAR,
3621 };
3622
3623 enum ec_host_event_mask_type {
3624
3625
3626 EC_HOST_EVENT_MAIN,
3627
3628
3629 EC_HOST_EVENT_B,
3630
3631
3632 EC_HOST_EVENT_SCI_MASK,
3633
3634
3635 EC_HOST_EVENT_SMI_MASK,
3636
3637
3638 EC_HOST_EVENT_ALWAYS_REPORT_MASK,
3639
3640
3641 EC_HOST_EVENT_ACTIVE_WAKE_MASK,
3642
3643
3644 EC_HOST_EVENT_LAZY_WAKE_MASK_S0IX,
3645
3646
3647 EC_HOST_EVENT_LAZY_WAKE_MASK_S3,
3648
3649
3650 EC_HOST_EVENT_LAZY_WAKE_MASK_S5,
3651 };
3652
3653 #define EC_CMD_HOST_EVENT 0x00A4
3654
3655
3656
3657
3658
3659 #define EC_CMD_SWITCH_ENABLE_BKLIGHT 0x0090
3660
3661 struct ec_params_switch_enable_backlight {
3662 uint8_t enabled;
3663 } __ec_align1;
3664
3665
3666 #define EC_CMD_SWITCH_ENABLE_WIRELESS 0x0091
3667 #define EC_VER_SWITCH_ENABLE_WIRELESS 1
3668
3669
3670 struct ec_params_switch_enable_wireless_v0 {
3671 uint8_t enabled;
3672 } __ec_align1;
3673
3674
3675 struct ec_params_switch_enable_wireless_v1 {
3676
3677 uint8_t now_flags;
3678
3679
3680 uint8_t now_mask;
3681
3682
3683
3684
3685
3686
3687 uint8_t suspend_flags;
3688
3689
3690 uint8_t suspend_mask;
3691 } __ec_align1;
3692
3693
3694 struct ec_response_switch_enable_wireless_v1 {
3695
3696 uint8_t now_flags;
3697
3698
3699 uint8_t suspend_flags;
3700 } __ec_align1;
3701
3702
3703
3704
3705
3706 #define EC_CMD_GPIO_SET 0x0092
3707
3708 struct ec_params_gpio_set {
3709 char name[32];
3710 uint8_t val;
3711 } __ec_align1;
3712
3713
3714 #define EC_CMD_GPIO_GET 0x0093
3715
3716
3717 struct ec_params_gpio_get {
3718 char name[32];
3719 } __ec_align1;
3720
3721 struct ec_response_gpio_get {
3722 uint8_t val;
3723 } __ec_align1;
3724
3725
3726 struct ec_params_gpio_get_v1 {
3727 uint8_t subcmd;
3728 union {
3729 struct __ec_align1 {
3730 char name[32];
3731 } get_value_by_name;
3732 struct __ec_align1 {
3733 uint8_t index;
3734 } get_info;
3735 };
3736 } __ec_align1;
3737
3738 struct ec_response_gpio_get_v1 {
3739 union {
3740 struct __ec_align1 {
3741 uint8_t val;
3742 } get_value_by_name, get_count;
3743 struct __ec_todo_unpacked {
3744 uint8_t val;
3745 char name[32];
3746 uint32_t flags;
3747 } get_info;
3748 };
3749 } __ec_todo_packed;
3750
3751 enum gpio_get_subcmd {
3752 EC_GPIO_GET_BY_NAME = 0,
3753 EC_GPIO_GET_COUNT = 1,
3754 EC_GPIO_GET_INFO = 2,
3755 };
3756
3757
3758
3759
3760
3761
3762
3763
3764
3765
3766
3767
3768 #define EC_CMD_I2C_READ 0x0094
3769
3770 struct ec_params_i2c_read {
3771 uint16_t addr;
3772 uint8_t read_size;
3773 uint8_t port;
3774 uint8_t offset;
3775 } __ec_align_size1;
3776
3777 struct ec_response_i2c_read {
3778 uint16_t data;
3779 } __ec_align2;
3780
3781
3782 #define EC_CMD_I2C_WRITE 0x0095
3783
3784 struct ec_params_i2c_write {
3785 uint16_t data;
3786 uint16_t addr;
3787 uint8_t write_size;
3788 uint8_t port;
3789 uint8_t offset;
3790 } __ec_align_size1;
3791
3792
3793
3794
3795
3796
3797
3798 #define EC_CMD_CHARGE_CONTROL 0x0096
3799 #define EC_VER_CHARGE_CONTROL 1
3800
3801 enum ec_charge_control_mode {
3802 CHARGE_CONTROL_NORMAL = 0,
3803 CHARGE_CONTROL_IDLE,
3804 CHARGE_CONTROL_DISCHARGE,
3805 };
3806
3807 struct ec_params_charge_control {
3808 uint32_t mode;
3809 } __ec_align4;
3810
3811
3812
3813
3814 #define EC_CMD_CONSOLE_SNAPSHOT 0x0097
3815
3816
3817
3818
3819
3820
3821
3822
3823
3824
3825
3826
3827
3828 #define EC_CMD_CONSOLE_READ 0x0098
3829
3830 enum ec_console_read_subcmd {
3831 CONSOLE_READ_NEXT = 0,
3832 CONSOLE_READ_RECENT
3833 };
3834
3835 struct ec_params_console_read_v1 {
3836 uint8_t subcmd;
3837 } __ec_align1;
3838
3839
3840
3841
3842
3843
3844
3845
3846
3847
3848 #define EC_CMD_BATTERY_CUT_OFF 0x0099
3849
3850 #define EC_BATTERY_CUTOFF_FLAG_AT_SHUTDOWN BIT(0)
3851
3852 struct ec_params_battery_cutoff {
3853 uint8_t flags;
3854 } __ec_align1;
3855
3856
3857
3858
3859
3860
3861
3862 #define EC_CMD_USB_MUX 0x009A
3863
3864 struct ec_params_usb_mux {
3865 uint8_t mux;
3866 } __ec_align1;
3867
3868
3869
3870
3871 enum ec_ldo_state {
3872 EC_LDO_STATE_OFF = 0,
3873 EC_LDO_STATE_ON = 1,
3874 };
3875
3876
3877
3878
3879 #define EC_CMD_LDO_SET 0x009B
3880
3881 struct ec_params_ldo_set {
3882 uint8_t index;
3883 uint8_t state;
3884 } __ec_align1;
3885
3886
3887
3888
3889 #define EC_CMD_LDO_GET 0x009C
3890
3891 struct ec_params_ldo_get {
3892 uint8_t index;
3893 } __ec_align1;
3894
3895 struct ec_response_ldo_get {
3896 uint8_t state;
3897 } __ec_align1;
3898
3899
3900
3901
3902
3903
3904
3905 #define EC_CMD_POWER_INFO 0x009D
3906
3907 struct ec_response_power_info {
3908 uint32_t usb_dev_type;
3909 uint16_t voltage_ac;
3910 uint16_t voltage_system;
3911 uint16_t current_system;
3912 uint16_t usb_current_limit;
3913 } __ec_align4;
3914
3915
3916
3917
3918 #define EC_CMD_I2C_PASSTHRU 0x009E
3919
3920
3921 #define EC_I2C_FLAG_READ BIT(15)
3922
3923
3924 #define EC_I2C_ADDR_MASK 0x3ff
3925
3926 #define EC_I2C_STATUS_NAK BIT(0)
3927 #define EC_I2C_STATUS_TIMEOUT BIT(1)
3928
3929
3930 #define EC_I2C_STATUS_ERROR (EC_I2C_STATUS_NAK | EC_I2C_STATUS_TIMEOUT)
3931
3932 struct ec_params_i2c_passthru_msg {
3933 uint16_t addr_flags;
3934 uint16_t len;
3935 } __ec_align2;
3936
3937 struct ec_params_i2c_passthru {
3938 uint8_t port;
3939 uint8_t num_msgs;
3940 struct ec_params_i2c_passthru_msg msg[];
3941
3942 } __ec_align2;
3943
3944 struct ec_response_i2c_passthru {
3945 uint8_t i2c_status;
3946 uint8_t num_msgs;
3947 uint8_t data[];
3948 } __ec_align1;
3949
3950
3951
3952
3953 #define EC_CMD_HANG_DETECT 0x009F
3954
3955
3956
3957 #define EC_HANG_START_ON_POWER_PRESS BIT(0)
3958
3959
3960 #define EC_HANG_START_ON_LID_CLOSE BIT(1)
3961
3962
3963 #define EC_HANG_START_ON_LID_OPEN BIT(2)
3964
3965
3966 #define EC_HANG_START_ON_RESUME BIT(3)
3967
3968
3969
3970
3971 #define EC_HANG_STOP_ON_POWER_RELEASE BIT(8)
3972
3973
3974 #define EC_HANG_STOP_ON_HOST_COMMAND BIT(9)
3975
3976
3977 #define EC_HANG_STOP_ON_SUSPEND BIT(10)
3978
3979
3980
3981
3982
3983
3984
3985 #define EC_HANG_START_NOW BIT(30)
3986
3987
3988
3989
3990
3991
3992 #define EC_HANG_STOP_NOW BIT(31)
3993
3994 struct ec_params_hang_detect {
3995
3996 uint32_t flags;
3997
3998
3999 uint16_t host_event_timeout_msec;
4000
4001
4002 uint16_t warm_reboot_timeout_msec;
4003 } __ec_align4;
4004
4005
4006
4007
4008
4009
4010
4011
4012 #define EC_CMD_CHARGE_STATE 0x00A0
4013
4014
4015 enum charge_state_command {
4016 CHARGE_STATE_CMD_GET_STATE,
4017 CHARGE_STATE_CMD_GET_PARAM,
4018 CHARGE_STATE_CMD_SET_PARAM,
4019 CHARGE_STATE_NUM_CMDS
4020 };
4021
4022
4023
4024
4025
4026 enum charge_state_params {
4027 CS_PARAM_CHG_VOLTAGE,
4028 CS_PARAM_CHG_CURRENT,
4029 CS_PARAM_CHG_INPUT_CURRENT,
4030 CS_PARAM_CHG_STATUS,
4031 CS_PARAM_CHG_OPTION,
4032 CS_PARAM_LIMIT_POWER,
4033
4034
4035
4036
4037
4038 CS_NUM_BASE_PARAMS,
4039
4040
4041 CS_PARAM_CUSTOM_PROFILE_MIN = 0x10000,
4042 CS_PARAM_CUSTOM_PROFILE_MAX = 0x1ffff,
4043
4044
4045 CS_PARAM_DEBUG_MIN = 0x20000,
4046 CS_PARAM_DEBUG_CTL_MODE = 0x20000,
4047 CS_PARAM_DEBUG_MANUAL_MODE,
4048 CS_PARAM_DEBUG_SEEMS_DEAD,
4049 CS_PARAM_DEBUG_SEEMS_DISCONNECTED,
4050 CS_PARAM_DEBUG_BATT_REMOVED,
4051 CS_PARAM_DEBUG_MANUAL_CURRENT,
4052 CS_PARAM_DEBUG_MANUAL_VOLTAGE,
4053 CS_PARAM_DEBUG_MAX = 0x2ffff,
4054
4055
4056 };
4057
4058 struct ec_params_charge_state {
4059 uint8_t cmd;
4060 union {
4061
4062
4063 struct __ec_todo_unpacked {
4064 uint32_t param;
4065 } get_param;
4066
4067 struct __ec_todo_unpacked {
4068 uint32_t param;
4069 uint32_t value;
4070 } set_param;
4071 };
4072 } __ec_todo_packed;
4073
4074 struct ec_response_charge_state {
4075 union {
4076 struct __ec_align4 {
4077 int ac;
4078 int chg_voltage;
4079 int chg_current;
4080 int chg_input_current;
4081 int batt_state_of_charge;
4082 } get_state;
4083
4084 struct __ec_align4 {
4085 uint32_t value;
4086 } get_param;
4087
4088
4089 };
4090 } __ec_align4;
4091
4092
4093
4094
4095
4096 #define EC_CMD_CHARGE_CURRENT_LIMIT 0x00A1
4097
4098 struct ec_params_current_limit {
4099 uint32_t limit;
4100 } __ec_align4;
4101
4102
4103
4104
4105 #define EC_CMD_EXTERNAL_POWER_LIMIT 0x00A2
4106
4107
4108 struct ec_params_external_power_limit_v1 {
4109 uint16_t current_lim;
4110 uint16_t voltage_lim;
4111 } __ec_align2;
4112
4113 #define EC_POWER_LIMIT_NONE 0xffff
4114
4115
4116
4117
4118 #define EC_CMD_OVERRIDE_DEDICATED_CHARGER_LIMIT 0x00A3
4119
4120 struct ec_params_dedicated_charger_limit {
4121 uint16_t current_lim;
4122 uint16_t voltage_lim;
4123 } __ec_align2;
4124
4125
4126
4127
4128
4129 #define EC_CMD_HIBERNATION_DELAY 0x00A8
4130
4131 struct ec_params_hibernation_delay {
4132
4133
4134
4135
4136 uint32_t seconds;
4137 } __ec_align4;
4138
4139 struct ec_response_hibernation_delay {
4140
4141
4142
4143
4144 uint32_t time_g3;
4145
4146
4147
4148
4149
4150 uint32_t time_remaining;
4151
4152
4153
4154
4155
4156 uint32_t hibernate_delay;
4157 } __ec_align4;
4158
4159
4160 #define EC_CMD_HOST_SLEEP_EVENT 0x00A9
4161
4162 enum host_sleep_event {
4163 HOST_SLEEP_EVENT_S3_SUSPEND = 1,
4164 HOST_SLEEP_EVENT_S3_RESUME = 2,
4165 HOST_SLEEP_EVENT_S0IX_SUSPEND = 3,
4166 HOST_SLEEP_EVENT_S0IX_RESUME = 4,
4167
4168 HOST_SLEEP_EVENT_S3_WAKEABLE_SUSPEND = 5,
4169 };
4170
4171 struct ec_params_host_sleep_event {
4172 uint8_t sleep_event;
4173 } __ec_align1;
4174
4175
4176
4177
4178
4179 #define EC_HOST_SLEEP_TIMEOUT_DEFAULT 0
4180
4181
4182 #define EC_HOST_SLEEP_TIMEOUT_INFINITE 0xFFFF
4183
4184 struct ec_params_host_sleep_event_v1 {
4185
4186 uint8_t sleep_event;
4187
4188
4189 uint8_t reserved;
4190 union {
4191
4192 struct {
4193
4194
4195
4196
4197
4198
4199 uint16_t sleep_timeout_ms;
4200 } suspend_params;
4201
4202
4203 };
4204 } __ec_align2;
4205
4206
4207 #define EC_HOST_RESUME_SLEEP_TIMEOUT 0x80000000
4208
4209
4210
4211
4212
4213
4214 #define EC_HOST_RESUME_SLEEP_TRANSITIONS_MASK 0x7FFFFFFF
4215
4216 struct ec_response_host_sleep_event_v1 {
4217 union {
4218
4219 struct {
4220
4221
4222
4223
4224
4225 uint32_t sleep_transitions;
4226 } resume_response;
4227
4228
4229 };
4230 } __ec_align4;
4231
4232
4233
4234 #define EC_CMD_DEVICE_EVENT 0x00AA
4235
4236 enum ec_device_event {
4237 EC_DEVICE_EVENT_TRACKPAD,
4238 EC_DEVICE_EVENT_DSP,
4239 EC_DEVICE_EVENT_WIFI,
4240 EC_DEVICE_EVENT_WLC,
4241 };
4242
4243 enum ec_device_event_param {
4244
4245 EC_DEVICE_EVENT_PARAM_GET_CURRENT_EVENTS,
4246
4247 EC_DEVICE_EVENT_PARAM_GET_ENABLED_EVENTS,
4248
4249 EC_DEVICE_EVENT_PARAM_SET_ENABLED_EVENTS,
4250 };
4251
4252 #define EC_DEVICE_EVENT_MASK(event_code) BIT(event_code % 32)
4253
4254 struct ec_params_device_event {
4255 uint32_t event_mask;
4256 uint8_t param;
4257 } __ec_align_size1;
4258
4259 struct ec_response_device_event {
4260 uint32_t event_mask;
4261 } __ec_align4;
4262
4263
4264
4265
4266
4267 #define EC_CMD_SB_READ_WORD 0x00B0
4268 #define EC_CMD_SB_WRITE_WORD 0x00B1
4269
4270
4271
4272
4273 #define EC_CMD_SB_READ_BLOCK 0x00B2
4274 #define EC_CMD_SB_WRITE_BLOCK 0x00B3
4275
4276 struct ec_params_sb_rd {
4277 uint8_t reg;
4278 } __ec_align1;
4279
4280 struct ec_response_sb_rd_word {
4281 uint16_t value;
4282 } __ec_align2;
4283
4284 struct ec_params_sb_wr_word {
4285 uint8_t reg;
4286 uint16_t value;
4287 } __ec_align1;
4288
4289 struct ec_response_sb_rd_block {
4290 uint8_t data[32];
4291 } __ec_align1;
4292
4293 struct ec_params_sb_wr_block {
4294 uint8_t reg;
4295 uint16_t data[32];
4296 } __ec_align1;
4297
4298
4299
4300
4301
4302
4303
4304
4305
4306
4307 #define EC_CMD_BATTERY_VENDOR_PARAM 0x00B4
4308
4309 enum ec_battery_vendor_param_mode {
4310 BATTERY_VENDOR_PARAM_MODE_GET = 0,
4311 BATTERY_VENDOR_PARAM_MODE_SET,
4312 };
4313
4314 struct ec_params_battery_vendor_param {
4315 uint32_t param;
4316 uint32_t value;
4317 uint8_t mode;
4318 } __ec_align_size1;
4319
4320 struct ec_response_battery_vendor_param {
4321 uint32_t value;
4322 } __ec_align4;
4323
4324
4325
4326
4327
4328 #define EC_CMD_SB_FW_UPDATE 0x00B5
4329
4330 enum ec_sb_fw_update_subcmd {
4331 EC_SB_FW_UPDATE_PREPARE = 0x0,
4332 EC_SB_FW_UPDATE_INFO = 0x1,
4333 EC_SB_FW_UPDATE_BEGIN = 0x2,
4334 EC_SB_FW_UPDATE_WRITE = 0x3,
4335 EC_SB_FW_UPDATE_END = 0x4,
4336 EC_SB_FW_UPDATE_STATUS = 0x5,
4337 EC_SB_FW_UPDATE_PROTECT = 0x6,
4338 EC_SB_FW_UPDATE_MAX = 0x7,
4339 };
4340
4341 #define SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE 32
4342 #define SB_FW_UPDATE_CMD_STATUS_SIZE 2
4343 #define SB_FW_UPDATE_CMD_INFO_SIZE 8
4344
4345 struct ec_sb_fw_update_header {
4346 uint16_t subcmd;
4347 uint16_t fw_id;
4348 } __ec_align4;
4349
4350 struct ec_params_sb_fw_update {
4351 struct ec_sb_fw_update_header hdr;
4352 union {
4353
4354
4355
4356
4357
4358
4359
4360
4361
4362 struct __ec_align4 {
4363 uint8_t data[SB_FW_UPDATE_CMD_WRITE_BLOCK_SIZE];
4364 } write;
4365 };
4366 } __ec_align4;
4367
4368 struct ec_response_sb_fw_update {
4369 union {
4370
4371 struct __ec_align1 {
4372 uint8_t data[SB_FW_UPDATE_CMD_INFO_SIZE];
4373 } info;
4374
4375
4376 struct __ec_align1 {
4377 uint8_t data[SB_FW_UPDATE_CMD_STATUS_SIZE];
4378 } status;
4379 };
4380 } __ec_align1;
4381
4382
4383
4384
4385
4386
4387 #define EC_CMD_ENTERING_MODE 0x00B6
4388
4389 struct ec_params_entering_mode {
4390 int vboot_mode;
4391 } __ec_align4;
4392
4393 #define VBOOT_MODE_NORMAL 0
4394 #define VBOOT_MODE_DEVELOPER 1
4395 #define VBOOT_MODE_RECOVERY 2
4396
4397
4398
4399
4400
4401
4402 #define EC_CMD_I2C_PASSTHRU_PROTECT 0x00B7
4403
4404 enum ec_i2c_passthru_protect_subcmd {
4405 EC_CMD_I2C_PASSTHRU_PROTECT_STATUS = 0x0,
4406 EC_CMD_I2C_PASSTHRU_PROTECT_ENABLE = 0x1,
4407 };
4408
4409 struct ec_params_i2c_passthru_protect {
4410 uint8_t subcmd;
4411 uint8_t port;
4412 } __ec_align1;
4413
4414 struct ec_response_i2c_passthru_protect {
4415 uint8_t status;
4416 } __ec_align1;
4417
4418
4419
4420
4421
4422
4423
4424
4425
4426 #define MAX_CEC_MSG_LEN 16
4427
4428
4429 #define EC_CMD_CEC_WRITE_MSG 0x00B8
4430
4431
4432
4433
4434
4435 struct ec_params_cec_write {
4436 uint8_t msg[MAX_CEC_MSG_LEN];
4437 } __ec_align1;
4438
4439
4440 #define EC_CMD_CEC_SET 0x00BA
4441
4442
4443
4444
4445
4446
4447
4448
4449
4450 struct ec_params_cec_set {
4451 uint8_t cmd;
4452 uint8_t val;
4453 } __ec_align1;
4454
4455
4456 #define EC_CMD_CEC_GET 0x00BB
4457
4458
4459
4460
4461
4462 struct ec_params_cec_get {
4463 uint8_t cmd;
4464 } __ec_align1;
4465
4466
4467
4468
4469
4470
4471
4472
4473 struct ec_response_cec_get {
4474 uint8_t val;
4475 } __ec_align1;
4476
4477
4478 enum cec_command {
4479
4480 CEC_CMD_ENABLE,
4481
4482 CEC_CMD_LOGICAL_ADDRESS,
4483 };
4484
4485
4486 enum mkbp_cec_event {
4487
4488 EC_MKBP_CEC_SEND_OK = BIT(0),
4489
4490 EC_MKBP_CEC_SEND_FAILED = BIT(1),
4491 };
4492
4493
4494
4495
4496 #define EC_CMD_EC_CODEC 0x00BC
4497
4498 enum ec_codec_subcmd {
4499 EC_CODEC_GET_CAPABILITIES = 0x0,
4500 EC_CODEC_GET_SHM_ADDR = 0x1,
4501 EC_CODEC_SET_SHM_ADDR = 0x2,
4502 EC_CODEC_SUBCMD_COUNT,
4503 };
4504
4505 enum ec_codec_cap {
4506 EC_CODEC_CAP_WOV_AUDIO_SHM = 0,
4507 EC_CODEC_CAP_WOV_LANG_SHM = 1,
4508 EC_CODEC_CAP_LAST = 32,
4509 };
4510
4511 enum ec_codec_shm_id {
4512 EC_CODEC_SHM_ID_WOV_AUDIO = 0x0,
4513 EC_CODEC_SHM_ID_WOV_LANG = 0x1,
4514 EC_CODEC_SHM_ID_LAST,
4515 };
4516
4517 enum ec_codec_shm_type {
4518 EC_CODEC_SHM_TYPE_EC_RAM = 0x0,
4519 EC_CODEC_SHM_TYPE_SYSTEM_RAM = 0x1,
4520 };
4521
4522 struct __ec_align1 ec_param_ec_codec_get_shm_addr {
4523 uint8_t shm_id;
4524 uint8_t reserved[3];
4525 };
4526
4527 struct __ec_align4 ec_param_ec_codec_set_shm_addr {
4528 uint64_t phys_addr;
4529 uint32_t len;
4530 uint8_t shm_id;
4531 uint8_t reserved[3];
4532 };
4533
4534 struct __ec_align4 ec_param_ec_codec {
4535 uint8_t cmd;
4536 uint8_t reserved[3];
4537
4538 union {
4539 struct ec_param_ec_codec_get_shm_addr
4540 get_shm_addr_param;
4541 struct ec_param_ec_codec_set_shm_addr
4542 set_shm_addr_param;
4543 };
4544 };
4545
4546 struct __ec_align4 ec_response_ec_codec_get_capabilities {
4547 uint32_t capabilities;
4548 };
4549
4550 struct __ec_align4 ec_response_ec_codec_get_shm_addr {
4551 uint64_t phys_addr;
4552 uint32_t len;
4553 uint8_t type;
4554 uint8_t reserved[3];
4555 };
4556
4557
4558
4559
4560 #define EC_CMD_EC_CODEC_DMIC 0x00BD
4561
4562 enum ec_codec_dmic_subcmd {
4563 EC_CODEC_DMIC_GET_MAX_GAIN = 0x0,
4564 EC_CODEC_DMIC_SET_GAIN_IDX = 0x1,
4565 EC_CODEC_DMIC_GET_GAIN_IDX = 0x2,
4566 EC_CODEC_DMIC_SUBCMD_COUNT,
4567 };
4568
4569 enum ec_codec_dmic_channel {
4570 EC_CODEC_DMIC_CHANNEL_0 = 0x0,
4571 EC_CODEC_DMIC_CHANNEL_1 = 0x1,
4572 EC_CODEC_DMIC_CHANNEL_2 = 0x2,
4573 EC_CODEC_DMIC_CHANNEL_3 = 0x3,
4574 EC_CODEC_DMIC_CHANNEL_4 = 0x4,
4575 EC_CODEC_DMIC_CHANNEL_5 = 0x5,
4576 EC_CODEC_DMIC_CHANNEL_6 = 0x6,
4577 EC_CODEC_DMIC_CHANNEL_7 = 0x7,
4578 EC_CODEC_DMIC_CHANNEL_COUNT,
4579 };
4580
4581 struct __ec_align1 ec_param_ec_codec_dmic_set_gain_idx {
4582 uint8_t channel;
4583 uint8_t gain;
4584 uint8_t reserved[2];
4585 };
4586
4587 struct __ec_align1 ec_param_ec_codec_dmic_get_gain_idx {
4588 uint8_t channel;
4589 uint8_t reserved[3];
4590 };
4591
4592 struct __ec_align4 ec_param_ec_codec_dmic {
4593 uint8_t cmd;
4594 uint8_t reserved[3];
4595
4596 union {
4597 struct ec_param_ec_codec_dmic_set_gain_idx
4598 set_gain_idx_param;
4599 struct ec_param_ec_codec_dmic_get_gain_idx
4600 get_gain_idx_param;
4601 };
4602 };
4603
4604 struct __ec_align1 ec_response_ec_codec_dmic_get_max_gain {
4605 uint8_t max_gain;
4606 };
4607
4608 struct __ec_align1 ec_response_ec_codec_dmic_get_gain_idx {
4609 uint8_t gain;
4610 };
4611
4612
4613
4614
4615
4616 #define EC_CMD_EC_CODEC_I2S_RX 0x00BE
4617
4618 enum ec_codec_i2s_rx_subcmd {
4619 EC_CODEC_I2S_RX_ENABLE = 0x0,
4620 EC_CODEC_I2S_RX_DISABLE = 0x1,
4621 EC_CODEC_I2S_RX_SET_SAMPLE_DEPTH = 0x2,
4622 EC_CODEC_I2S_RX_SET_DAIFMT = 0x3,
4623 EC_CODEC_I2S_RX_SET_BCLK = 0x4,
4624 EC_CODEC_I2S_RX_RESET = 0x5,
4625 EC_CODEC_I2S_RX_SUBCMD_COUNT,
4626 };
4627
4628 enum ec_codec_i2s_rx_sample_depth {
4629 EC_CODEC_I2S_RX_SAMPLE_DEPTH_16 = 0x0,
4630 EC_CODEC_I2S_RX_SAMPLE_DEPTH_24 = 0x1,
4631 EC_CODEC_I2S_RX_SAMPLE_DEPTH_COUNT,
4632 };
4633
4634 enum ec_codec_i2s_rx_daifmt {
4635 EC_CODEC_I2S_RX_DAIFMT_I2S = 0x0,
4636 EC_CODEC_I2S_RX_DAIFMT_RIGHT_J = 0x1,
4637 EC_CODEC_I2S_RX_DAIFMT_LEFT_J = 0x2,
4638 EC_CODEC_I2S_RX_DAIFMT_COUNT,
4639 };
4640
4641 struct __ec_align1 ec_param_ec_codec_i2s_rx_set_sample_depth {
4642 uint8_t depth;
4643 uint8_t reserved[3];
4644 };
4645
4646 struct __ec_align1 ec_param_ec_codec_i2s_rx_set_gain {
4647 uint8_t left;
4648 uint8_t right;
4649 uint8_t reserved[2];
4650 };
4651
4652 struct __ec_align1 ec_param_ec_codec_i2s_rx_set_daifmt {
4653 uint8_t daifmt;
4654 uint8_t reserved[3];
4655 };
4656
4657 struct __ec_align4 ec_param_ec_codec_i2s_rx_set_bclk {
4658 uint32_t bclk;
4659 };
4660
4661 struct __ec_align4 ec_param_ec_codec_i2s_rx {
4662 uint8_t cmd;
4663 uint8_t reserved[3];
4664
4665 union {
4666 struct ec_param_ec_codec_i2s_rx_set_sample_depth
4667 set_sample_depth_param;
4668 struct ec_param_ec_codec_i2s_rx_set_daifmt
4669 set_daifmt_param;
4670 struct ec_param_ec_codec_i2s_rx_set_bclk
4671 set_bclk_param;
4672 };
4673 };
4674
4675
4676
4677
4678 #define EC_CMD_EC_CODEC_WOV 0x00BF
4679
4680 enum ec_codec_wov_subcmd {
4681 EC_CODEC_WOV_SET_LANG = 0x0,
4682 EC_CODEC_WOV_SET_LANG_SHM = 0x1,
4683 EC_CODEC_WOV_GET_LANG = 0x2,
4684 EC_CODEC_WOV_ENABLE = 0x3,
4685 EC_CODEC_WOV_DISABLE = 0x4,
4686 EC_CODEC_WOV_READ_AUDIO = 0x5,
4687 EC_CODEC_WOV_READ_AUDIO_SHM = 0x6,
4688 EC_CODEC_WOV_SUBCMD_COUNT,
4689 };
4690
4691
4692
4693
4694
4695
4696
4697
4698 struct __ec_align4 ec_param_ec_codec_wov_set_lang {
4699 uint8_t hash[32];
4700 uint32_t total_len;
4701 uint32_t offset;
4702 uint8_t buf[128];
4703 uint32_t len;
4704 };
4705
4706 struct __ec_align4 ec_param_ec_codec_wov_set_lang_shm {
4707 uint8_t hash[32];
4708 uint32_t total_len;
4709 };
4710
4711 struct __ec_align4 ec_param_ec_codec_wov {
4712 uint8_t cmd;
4713 uint8_t reserved[3];
4714
4715 union {
4716 struct ec_param_ec_codec_wov_set_lang
4717 set_lang_param;
4718 struct ec_param_ec_codec_wov_set_lang_shm
4719 set_lang_shm_param;
4720 };
4721 };
4722
4723 struct __ec_align4 ec_response_ec_codec_wov_get_lang {
4724 uint8_t hash[32];
4725 };
4726
4727 struct __ec_align4 ec_response_ec_codec_wov_read_audio {
4728 uint8_t buf[128];
4729 uint32_t len;
4730 };
4731
4732 struct __ec_align4 ec_response_ec_codec_wov_read_audio_shm {
4733 uint32_t offset;
4734 uint32_t len;
4735 };
4736
4737
4738
4739
4740
4741
4742
4743
4744 #define EC_CMD_REBOOT_EC 0x00D2
4745
4746
4747 enum ec_reboot_cmd {
4748 EC_REBOOT_CANCEL = 0,
4749 EC_REBOOT_JUMP_RO = 1,
4750 EC_REBOOT_JUMP_RW = 2,
4751
4752 EC_REBOOT_COLD = 4,
4753 EC_REBOOT_DISABLE_JUMP = 5,
4754 EC_REBOOT_HIBERNATE = 6,
4755 EC_REBOOT_HIBERNATE_CLEAR_AP_OFF = 7,
4756 EC_REBOOT_COLD_AP_OFF = 8,
4757 };
4758
4759
4760 #define EC_REBOOT_FLAG_RESERVED0 BIT(0)
4761 #define EC_REBOOT_FLAG_ON_AP_SHUTDOWN BIT(1)
4762 #define EC_REBOOT_FLAG_SWITCH_RW_SLOT BIT(2)
4763
4764 struct ec_params_reboot_ec {
4765 uint8_t cmd;
4766 uint8_t flags;
4767 } __ec_align1;
4768
4769
4770
4771
4772
4773
4774
4775 #define EC_CMD_GET_PANIC_INFO 0x00D3
4776
4777
4778
4779
4780
4781
4782
4783
4784
4785
4786
4787
4788
4789
4790
4791
4792
4793
4794 #define EC_CMD_REBOOT 0x00D1
4795
4796
4797
4798
4799
4800
4801
4802
4803 #define EC_CMD_RESEND_RESPONSE 0x00DB
4804
4805
4806
4807
4808
4809
4810
4811
4812
4813
4814
4815 #define EC_CMD_VERSION0 0x00DC
4816
4817
4818
4819
4820
4821
4822
4823
4824
4825 #define EC_CMD_PD_EXCHANGE_STATUS 0x0100
4826 #define EC_VER_PD_EXCHANGE_STATUS 2
4827
4828 enum pd_charge_state {
4829 PD_CHARGE_NO_CHANGE = 0,
4830 PD_CHARGE_NONE,
4831 PD_CHARGE_5V,
4832 PD_CHARGE_MAX
4833 };
4834
4835
4836 #define EC_STATUS_HIBERNATING BIT(0)
4837
4838 struct ec_params_pd_status {
4839 uint8_t status;
4840 int8_t batt_soc;
4841 uint8_t charge_state;
4842 } __ec_align1;
4843
4844
4845 #define PD_STATUS_HOST_EVENT BIT(0)
4846 #define PD_STATUS_IN_RW BIT(1)
4847 #define PD_STATUS_JUMPED_TO_IMAGE BIT(2)
4848 #define PD_STATUS_TCPC_ALERT_0 BIT(3)
4849 #define PD_STATUS_TCPC_ALERT_1 BIT(4)
4850 #define PD_STATUS_TCPC_ALERT_2 BIT(5)
4851 #define PD_STATUS_TCPC_ALERT_3 BIT(6)
4852 #define PD_STATUS_EC_INT_ACTIVE (PD_STATUS_TCPC_ALERT_0 | \
4853 PD_STATUS_TCPC_ALERT_1 | \
4854 PD_STATUS_HOST_EVENT)
4855 struct ec_response_pd_status {
4856 uint32_t curr_lim_ma;
4857 uint16_t status;
4858 int8_t active_charge_port;
4859 } __ec_align_size1;
4860
4861
4862 #define EC_CMD_PD_HOST_EVENT_STATUS 0x0104
4863
4864
4865 #define PD_EVENT_UPDATE_DEVICE BIT(0)
4866 #define PD_EVENT_POWER_CHANGE BIT(1)
4867 #define PD_EVENT_IDENTITY_RECEIVED BIT(2)
4868 #define PD_EVENT_DATA_SWAP BIT(3)
4869 struct ec_response_host_event_status {
4870 uint32_t status;
4871 } __ec_align4;
4872
4873
4874 #define EC_CMD_USB_PD_CONTROL 0x0101
4875
4876 enum usb_pd_control_role {
4877 USB_PD_CTRL_ROLE_NO_CHANGE = 0,
4878 USB_PD_CTRL_ROLE_TOGGLE_ON = 1,
4879 USB_PD_CTRL_ROLE_TOGGLE_OFF = 2,
4880 USB_PD_CTRL_ROLE_FORCE_SINK = 3,
4881 USB_PD_CTRL_ROLE_FORCE_SOURCE = 4,
4882 USB_PD_CTRL_ROLE_FREEZE = 5,
4883 USB_PD_CTRL_ROLE_COUNT
4884 };
4885
4886 enum usb_pd_control_mux {
4887 USB_PD_CTRL_MUX_NO_CHANGE = 0,
4888 USB_PD_CTRL_MUX_NONE = 1,
4889 USB_PD_CTRL_MUX_USB = 2,
4890 USB_PD_CTRL_MUX_DP = 3,
4891 USB_PD_CTRL_MUX_DOCK = 4,
4892 USB_PD_CTRL_MUX_AUTO = 5,
4893 USB_PD_CTRL_MUX_COUNT
4894 };
4895
4896 enum usb_pd_control_swap {
4897 USB_PD_CTRL_SWAP_NONE = 0,
4898 USB_PD_CTRL_SWAP_DATA = 1,
4899 USB_PD_CTRL_SWAP_POWER = 2,
4900 USB_PD_CTRL_SWAP_VCONN = 3,
4901 USB_PD_CTRL_SWAP_COUNT
4902 };
4903
4904 struct ec_params_usb_pd_control {
4905 uint8_t port;
4906 uint8_t role;
4907 uint8_t mux;
4908 uint8_t swap;
4909 } __ec_align1;
4910
4911 #define PD_CTRL_RESP_ENABLED_COMMS BIT(0)
4912 #define PD_CTRL_RESP_ENABLED_CONNECTED BIT(1)
4913 #define PD_CTRL_RESP_ENABLED_PD_CAPABLE BIT(2)
4914
4915 #define PD_CTRL_RESP_ROLE_POWER BIT(0)
4916 #define PD_CTRL_RESP_ROLE_DATA BIT(1)
4917 #define PD_CTRL_RESP_ROLE_VCONN BIT(2)
4918 #define PD_CTRL_RESP_ROLE_DR_POWER BIT(3)
4919 #define PD_CTRL_RESP_ROLE_DR_DATA BIT(4)
4920 #define PD_CTRL_RESP_ROLE_USB_COMM BIT(5)
4921 #define PD_CTRL_RESP_ROLE_EXT_POWERED BIT(6)
4922
4923 struct ec_response_usb_pd_control {
4924 uint8_t enabled;
4925 uint8_t role;
4926 uint8_t polarity;
4927 uint8_t state;
4928 } __ec_align1;
4929
4930 struct ec_response_usb_pd_control_v1 {
4931 uint8_t enabled;
4932 uint8_t role;
4933 uint8_t polarity;
4934 char state[32];
4935 } __ec_align1;
4936
4937
4938 #define USBC_PD_CC_NONE 0
4939 #define USBC_PD_CC_NO_UFP 1
4940 #define USBC_PD_CC_AUDIO_ACC 2
4941 #define USBC_PD_CC_DEBUG_ACC 3
4942 #define USBC_PD_CC_UFP_ATTACHED 4
4943 #define USBC_PD_CC_DFP_ATTACHED 5
4944
4945
4946 #define USB_PD_CTRL_ACTIVE_CABLE BIT(0)
4947
4948 #define USB_PD_CTRL_OPTICAL_CABLE BIT(1)
4949
4950 #define USB_PD_CTRL_TBT_LEGACY_ADAPTER BIT(2)
4951
4952 #define USB_PD_CTRL_ACTIVE_LINK_UNIDIR BIT(3)
4953
4954 struct ec_response_usb_pd_control_v2 {
4955 uint8_t enabled;
4956 uint8_t role;
4957 uint8_t polarity;
4958 char state[32];
4959 uint8_t cc_state;
4960 uint8_t dp_mode;
4961 uint8_t reserved;
4962 uint8_t control_flags;
4963 uint8_t cable_speed;
4964 uint8_t cable_gen;
4965 } __ec_align1;
4966
4967 #define EC_CMD_USB_PD_PORTS 0x0102
4968
4969
4970 #define EC_USB_PD_MAX_PORTS 8
4971
4972 struct ec_response_usb_pd_ports {
4973 uint8_t num_ports;
4974 } __ec_align1;
4975
4976 #define EC_CMD_USB_PD_POWER_INFO 0x0103
4977
4978 #define PD_POWER_CHARGING_PORT 0xff
4979 struct ec_params_usb_pd_power_info {
4980 uint8_t port;
4981 } __ec_align1;
4982
4983 enum usb_chg_type {
4984 USB_CHG_TYPE_NONE,
4985 USB_CHG_TYPE_PD,
4986 USB_CHG_TYPE_C,
4987 USB_CHG_TYPE_PROPRIETARY,
4988 USB_CHG_TYPE_BC12_DCP,
4989 USB_CHG_TYPE_BC12_CDP,
4990 USB_CHG_TYPE_BC12_SDP,
4991 USB_CHG_TYPE_OTHER,
4992 USB_CHG_TYPE_VBUS,
4993 USB_CHG_TYPE_UNKNOWN,
4994 USB_CHG_TYPE_DEDICATED,
4995 };
4996 enum usb_power_roles {
4997 USB_PD_PORT_POWER_DISCONNECTED,
4998 USB_PD_PORT_POWER_SOURCE,
4999 USB_PD_PORT_POWER_SINK,
5000 USB_PD_PORT_POWER_SINK_NOT_CHARGING,
5001 };
5002
5003 struct usb_chg_measures {
5004 uint16_t voltage_max;
5005 uint16_t voltage_now;
5006 uint16_t current_max;
5007 uint16_t current_lim;
5008 } __ec_align2;
5009
5010 struct ec_response_usb_pd_power_info {
5011 uint8_t role;
5012 uint8_t type;
5013 uint8_t dualrole;
5014 uint8_t reserved1;
5015 struct usb_chg_measures meas;
5016 uint32_t max_power;
5017 } __ec_align4;
5018
5019
5020
5021
5022
5023
5024
5025 #define EC_CMD_CHARGE_PORT_COUNT 0x0105
5026 struct ec_response_charge_port_count {
5027 uint8_t port_count;
5028 } __ec_align1;
5029
5030
5031 #define EC_CMD_USB_PD_FW_UPDATE 0x0110
5032
5033 enum usb_pd_fw_update_cmds {
5034 USB_PD_FW_REBOOT,
5035 USB_PD_FW_FLASH_ERASE,
5036 USB_PD_FW_FLASH_WRITE,
5037 USB_PD_FW_ERASE_SIG,
5038 };
5039
5040 struct ec_params_usb_pd_fw_update {
5041 uint16_t dev_id;
5042 uint8_t cmd;
5043 uint8_t port;
5044 uint32_t size;
5045
5046 } __ec_align4;
5047
5048
5049 #define EC_CMD_USB_PD_RW_HASH_ENTRY 0x0111
5050
5051 #define PD_RW_HASH_SIZE 20
5052 struct ec_params_usb_pd_rw_hash_entry {
5053 uint16_t dev_id;
5054 uint8_t dev_rw_hash[PD_RW_HASH_SIZE];
5055 uint8_t reserved;
5056
5057
5058
5059
5060 uint32_t current_image;
5061 } __ec_align1;
5062
5063
5064 #define EC_CMD_USB_PD_DEV_INFO 0x0112
5065
5066 struct ec_params_usb_pd_info_request {
5067 uint8_t port;
5068 } __ec_align1;
5069
5070
5071 #define EC_CMD_USB_PD_DISCOVERY 0x0113
5072 struct ec_params_usb_pd_discovery_entry {
5073 uint16_t vid;
5074 uint16_t pid;
5075 uint8_t ptype;
5076 } __ec_align_size1;
5077
5078
5079 #define EC_CMD_PD_CHARGE_PORT_OVERRIDE 0x0114
5080
5081
5082 enum usb_pd_override_ports {
5083 OVERRIDE_DONT_CHARGE = -2,
5084 OVERRIDE_OFF = -1,
5085
5086 };
5087
5088 struct ec_params_charge_port_override {
5089 int16_t override_port;
5090 } __ec_align2;
5091
5092
5093
5094
5095
5096
5097 #define EC_CMD_PD_GET_LOG_ENTRY 0x0115
5098
5099 struct ec_response_pd_log {
5100 uint32_t timestamp;
5101 uint8_t type;
5102 uint8_t size_port;
5103 uint16_t data;
5104 uint8_t payload[];
5105 } __ec_align4;
5106
5107
5108 #define PD_LOG_TIMESTAMP_SHIFT 10
5109
5110 #define PD_LOG_SIZE_MASK 0x1f
5111 #define PD_LOG_PORT_MASK 0xe0
5112 #define PD_LOG_PORT_SHIFT 5
5113 #define PD_LOG_PORT_SIZE(port, size) (((port) << PD_LOG_PORT_SHIFT) | \
5114 ((size) & PD_LOG_SIZE_MASK))
5115 #define PD_LOG_PORT(size_port) ((size_port) >> PD_LOG_PORT_SHIFT)
5116 #define PD_LOG_SIZE(size_port) ((size_port) & PD_LOG_SIZE_MASK)
5117
5118
5119
5120 #define PD_EVENT_MCU_BASE 0x00
5121 #define PD_EVENT_MCU_CHARGE (PD_EVENT_MCU_BASE+0)
5122 #define PD_EVENT_MCU_CONNECT (PD_EVENT_MCU_BASE+1)
5123
5124 #define PD_EVENT_MCU_BOARD_CUSTOM (PD_EVENT_MCU_BASE+2)
5125
5126 #define PD_EVENT_ACC_BASE 0x20
5127 #define PD_EVENT_ACC_RW_FAIL (PD_EVENT_ACC_BASE+0)
5128 #define PD_EVENT_ACC_RW_ERASE (PD_EVENT_ACC_BASE+1)
5129
5130 #define PD_EVENT_PS_BASE 0x40
5131 #define PD_EVENT_PS_FAULT (PD_EVENT_PS_BASE+0)
5132
5133 #define PD_EVENT_VIDEO_BASE 0x60
5134 #define PD_EVENT_VIDEO_DP_MODE (PD_EVENT_VIDEO_BASE+0)
5135 #define PD_EVENT_VIDEO_CODEC (PD_EVENT_VIDEO_BASE+1)
5136
5137 #define PD_EVENT_NO_ENTRY 0xff
5138
5139
5140
5141
5142
5143
5144
5145 #define CHARGE_FLAGS_DUAL_ROLE BIT(15)
5146
5147 #define CHARGE_FLAGS_DELAYED_OVERRIDE BIT(14)
5148
5149 #define CHARGE_FLAGS_OVERRIDE BIT(13)
5150
5151 #define CHARGE_FLAGS_TYPE_SHIFT 3
5152 #define CHARGE_FLAGS_TYPE_MASK (0xf << CHARGE_FLAGS_TYPE_SHIFT)
5153
5154 #define CHARGE_FLAGS_ROLE_MASK (7 << 0)
5155
5156
5157
5158
5159 #define PS_FAULT_OCP 1
5160 #define PS_FAULT_FAST_OCP 2
5161 #define PS_FAULT_OVP 3
5162 #define PS_FAULT_DISCH 4
5163
5164
5165
5166
5167 struct mcdp_version {
5168 uint8_t major;
5169 uint8_t minor;
5170 uint16_t build;
5171 } __ec_align4;
5172
5173 struct mcdp_info {
5174 uint8_t family[2];
5175 uint8_t chipid[2];
5176 struct mcdp_version irom;
5177 struct mcdp_version fw;
5178 } __ec_align4;
5179
5180
5181 #define MCDP_CHIPID(chipid) ((chipid[0] << 8) | chipid[1])
5182 #define MCDP_FAMILY(family) ((family[0] << 8) | family[1])
5183
5184
5185 #define EC_CMD_USB_PD_GET_AMODE 0x0116
5186 struct ec_params_usb_pd_get_mode_request {
5187 uint16_t svid_idx;
5188 uint8_t port;
5189 } __ec_align_size1;
5190
5191 struct ec_params_usb_pd_get_mode_response {
5192 uint16_t svid;
5193 uint16_t opos;
5194 uint32_t vdo[6];
5195 } __ec_align4;
5196
5197 #define EC_CMD_USB_PD_SET_AMODE 0x0117
5198
5199 enum pd_mode_cmd {
5200 PD_EXIT_MODE = 0,
5201 PD_ENTER_MODE = 1,
5202
5203 PD_MODE_CMD_COUNT,
5204 };
5205
5206 struct ec_params_usb_pd_set_mode_request {
5207 uint32_t cmd;
5208 uint16_t svid;
5209 uint8_t opos;
5210 uint8_t port;
5211 } __ec_align4;
5212
5213
5214 #define EC_CMD_PD_WRITE_LOG_ENTRY 0x0118
5215
5216 struct ec_params_pd_write_log_entry {
5217 uint8_t type;
5218 uint8_t port;
5219 } __ec_align1;
5220
5221
5222
5223 #define EC_CMD_PD_CONTROL 0x0119
5224
5225 enum ec_pd_control_cmd {
5226 PD_SUSPEND = 0,
5227 PD_RESUME,
5228 PD_RESET,
5229 PD_CONTROL_DISABLE,
5230 PD_CHIP_ON,
5231 };
5232
5233 struct ec_params_pd_control {
5234 uint8_t chip;
5235 uint8_t subcmd;
5236 } __ec_align1;
5237
5238
5239 #define EC_CMD_USB_PD_MUX_INFO 0x011A
5240
5241 struct ec_params_usb_pd_mux_info {
5242 uint8_t port;
5243 } __ec_align1;
5244
5245
5246 #define USB_PD_MUX_NONE 0
5247 #define USB_PD_MUX_USB_ENABLED BIT(0)
5248 #define USB_PD_MUX_DP_ENABLED BIT(1)
5249 #define USB_PD_MUX_POLARITY_INVERTED BIT(2)
5250 #define USB_PD_MUX_HPD_IRQ BIT(3)
5251 #define USB_PD_MUX_HPD_LVL BIT(4)
5252 #define USB_PD_MUX_SAFE_MODE BIT(5)
5253 #define USB_PD_MUX_TBT_COMPAT_ENABLED BIT(6)
5254 #define USB_PD_MUX_USB4_ENABLED BIT(7)
5255
5256 struct ec_response_usb_pd_mux_info {
5257 uint8_t flags;
5258 } __ec_align1;
5259
5260 #define EC_CMD_PD_CHIP_INFO 0x011B
5261
5262 struct ec_params_pd_chip_info {
5263 uint8_t port;
5264 uint8_t renew;
5265 } __ec_align1;
5266
5267 struct ec_response_pd_chip_info {
5268 uint16_t vendor_id;
5269 uint16_t product_id;
5270 uint16_t device_id;
5271 union {
5272 uint8_t fw_version_string[8];
5273 uint64_t fw_version_number;
5274 };
5275 } __ec_align2;
5276
5277 struct ec_response_pd_chip_info_v1 {
5278 uint16_t vendor_id;
5279 uint16_t product_id;
5280 uint16_t device_id;
5281 union {
5282 uint8_t fw_version_string[8];
5283 uint64_t fw_version_number;
5284 };
5285 union {
5286 uint8_t min_req_fw_version_string[8];
5287 uint64_t min_req_fw_version_number;
5288 };
5289 } __ec_align2;
5290
5291
5292 #define EC_CMD_RWSIG_CHECK_STATUS 0x011C
5293
5294 struct ec_response_rwsig_check_status {
5295 uint32_t status;
5296 } __ec_align4;
5297
5298
5299 #define EC_CMD_RWSIG_ACTION 0x011D
5300
5301 enum rwsig_action {
5302 RWSIG_ACTION_ABORT = 0,
5303 RWSIG_ACTION_CONTINUE = 1,
5304 };
5305
5306 struct ec_params_rwsig_action {
5307 uint32_t action;
5308 } __ec_align4;
5309
5310
5311 #define EC_CMD_EFS_VERIFY 0x011E
5312
5313 struct ec_params_efs_verify {
5314 uint8_t region;
5315 } __ec_align1;
5316
5317
5318
5319
5320
5321
5322 #define EC_CMD_GET_CROS_BOARD_INFO 0x011F
5323
5324
5325
5326
5327 #define EC_CMD_SET_CROS_BOARD_INFO 0x0120
5328
5329 enum cbi_data_tag {
5330 CBI_TAG_BOARD_VERSION = 0,
5331 CBI_TAG_OEM_ID = 1,
5332 CBI_TAG_SKU_ID = 2,
5333 CBI_TAG_DRAM_PART_NUM = 3,
5334 CBI_TAG_OEM_NAME = 4,
5335 CBI_TAG_MODEL_ID = 5,
5336 CBI_TAG_COUNT,
5337 };
5338
5339
5340
5341
5342
5343
5344
5345 #define CBI_GET_RELOAD BIT(0)
5346
5347 struct ec_params_get_cbi {
5348 uint32_t tag;
5349 uint32_t flag;
5350 } __ec_align4;
5351
5352
5353
5354
5355
5356
5357
5358
5359
5360 #define CBI_SET_NO_SYNC BIT(0)
5361 #define CBI_SET_INIT BIT(1)
5362
5363 struct ec_params_set_cbi {
5364 uint32_t tag;
5365 uint32_t flag;
5366 uint32_t size;
5367 uint8_t data[];
5368 } __ec_align1;
5369
5370
5371
5372
5373 #define EC_CMD_GET_UPTIME_INFO 0x0121
5374
5375 struct ec_response_uptime_info {
5376
5377
5378
5379
5380
5381
5382
5383
5384 uint32_t time_since_ec_boot_ms;
5385
5386
5387
5388
5389
5390
5391
5392 uint32_t ap_resets_since_ec_boot;
5393
5394
5395
5396
5397
5398 uint32_t ec_reset_flags;
5399
5400
5401 struct ap_reset_log_entry {
5402
5403
5404
5405
5406 uint16_t reset_cause;
5407
5408
5409 uint16_t reserved;
5410
5411
5412
5413
5414
5415
5416 uint32_t reset_time_ms;
5417 } recent_ap_reset[4];
5418 } __ec_align4;
5419
5420
5421
5422
5423
5424
5425
5426 #define EC_CMD_ADD_ENTROPY 0x0122
5427
5428 enum add_entropy_action {
5429
5430 ADD_ENTROPY_ASYNC = 0,
5431
5432
5433
5434
5435
5436 ADD_ENTROPY_RESET_ASYNC = 1,
5437
5438 ADD_ENTROPY_GET_RESULT = 2,
5439 };
5440
5441 struct ec_params_rollback_add_entropy {
5442 uint8_t action;
5443 } __ec_align1;
5444
5445
5446
5447
5448 #define EC_CMD_ADC_READ 0x0123
5449
5450 struct ec_params_adc_read {
5451 uint8_t adc_channel;
5452 } __ec_align1;
5453
5454 struct ec_response_adc_read {
5455 int32_t adc_value;
5456 } __ec_align4;
5457
5458
5459
5460
5461 #define EC_CMD_ROLLBACK_INFO 0x0124
5462
5463 struct ec_response_rollback_info {
5464 int32_t id;
5465 int32_t rollback_min_version;
5466 int32_t rw_rollback_version;
5467 } __ec_align4;
5468
5469
5470
5471 #define EC_CMD_AP_RESET 0x0125
5472
5473
5474
5475
5476 #define EC_CMD_PCHG_COUNT 0x0134
5477
5478 #define EC_PCHG_MAX_PORTS 8
5479
5480 struct ec_response_pchg_count {
5481 uint8_t port_count;
5482 } __ec_align1;
5483
5484
5485
5486
5487 #define EC_CMD_PCHG 0x0135
5488
5489 struct ec_params_pchg {
5490 uint8_t port;
5491 } __ec_align1;
5492
5493 struct ec_response_pchg {
5494 uint32_t error;
5495 uint8_t state;
5496 uint8_t battery_percentage;
5497 uint8_t unused0;
5498 uint8_t unused1;
5499
5500 uint32_t fw_version;
5501 uint32_t dropped_event_count;
5502 } __ec_align2;
5503
5504 enum pchg_state {
5505
5506 PCHG_STATE_RESET = 0,
5507
5508 PCHG_STATE_INITIALIZED,
5509
5510 PCHG_STATE_ENABLED,
5511
5512 PCHG_STATE_DETECTED,
5513
5514 PCHG_STATE_CHARGING,
5515
5516 PCHG_STATE_FULL,
5517
5518 PCHG_STATE_DOWNLOAD,
5519
5520 PCHG_STATE_DOWNLOADING,
5521
5522 PCHG_STATE_CONNECTED,
5523
5524 PCHG_STATE_COUNT,
5525 };
5526
5527 #define EC_PCHG_STATE_TEXT { \
5528 [PCHG_STATE_RESET] = "RESET", \
5529 [PCHG_STATE_INITIALIZED] = "INITIALIZED", \
5530 [PCHG_STATE_ENABLED] = "ENABLED", \
5531 [PCHG_STATE_DETECTED] = "DETECTED", \
5532 [PCHG_STATE_CHARGING] = "CHARGING", \
5533 [PCHG_STATE_FULL] = "FULL", \
5534 [PCHG_STATE_DOWNLOAD] = "DOWNLOAD", \
5535 [PCHG_STATE_DOWNLOADING] = "DOWNLOADING", \
5536 [PCHG_STATE_CONNECTED] = "CONNECTED", \
5537 }
5538
5539
5540
5541
5542 #define EC_CMD_PCHG_UPDATE 0x0136
5543
5544
5545 #define EC_MKBP_PCHG_PORT_SHIFT 28
5546
5547 #define EC_MKBP_PCHG_EVENT_TO_PORT(e) (((e) >> EC_MKBP_PCHG_PORT_SHIFT) & 0xf)
5548
5549 #define EC_MKBP_PCHG_EVENT_MASK(e) ((e) \
5550 & GENMASK(EC_MKBP_PCHG_PORT_SHIFT-1, 0))
5551
5552 #define EC_MKBP_PCHG_UPDATE_OPENED BIT(0)
5553 #define EC_MKBP_PCHG_WRITE_COMPLETE BIT(1)
5554 #define EC_MKBP_PCHG_UPDATE_CLOSED BIT(2)
5555 #define EC_MKBP_PCHG_UPDATE_ERROR BIT(3)
5556 #define EC_MKBP_PCHG_DEVICE_EVENT BIT(4)
5557
5558 enum ec_pchg_update_cmd {
5559
5560 EC_PCHG_UPDATE_CMD_RESET_TO_NORMAL = 0,
5561
5562 EC_PCHG_UPDATE_CMD_OPEN,
5563
5564 EC_PCHG_UPDATE_CMD_WRITE,
5565
5566 EC_PCHG_UPDATE_CMD_CLOSE,
5567
5568 EC_PCHG_UPDATE_CMD_COUNT,
5569 };
5570
5571 struct ec_params_pchg_update {
5572
5573 uint8_t port;
5574
5575 uint8_t cmd;
5576
5577 uint8_t reserved0;
5578 uint8_t reserved1;
5579
5580 uint32_t version;
5581
5582 uint32_t crc32;
5583
5584 uint32_t addr;
5585
5586 uint32_t size;
5587
5588 uint8_t data[];
5589 } __ec_align4;
5590
5591 BUILD_ASSERT(EC_PCHG_UPDATE_CMD_COUNT
5592 < BIT(sizeof(((struct ec_params_pchg_update *)0)->cmd)*8));
5593
5594 struct ec_response_pchg_update {
5595
5596 uint32_t block_size;
5597 } __ec_align4;
5598
5599
5600
5601
5602
5603
5604
5605
5606
5607
5608 #define EC_CMD_REGULATOR_GET_INFO 0x012C
5609
5610
5611 #define EC_REGULATOR_NAME_MAX_LEN 16
5612
5613
5614 #define EC_REGULATOR_VOLTAGE_MAX_COUNT 16
5615
5616 struct ec_params_regulator_get_info {
5617 uint32_t index;
5618 } __ec_align4;
5619
5620 struct ec_response_regulator_get_info {
5621 char name[EC_REGULATOR_NAME_MAX_LEN];
5622 uint16_t num_voltages;
5623 uint16_t voltages_mv[EC_REGULATOR_VOLTAGE_MAX_COUNT];
5624 } __ec_align2;
5625
5626
5627
5628
5629 #define EC_CMD_REGULATOR_ENABLE 0x012D
5630
5631 struct ec_params_regulator_enable {
5632 uint32_t index;
5633 uint8_t enable;
5634 } __ec_align4;
5635
5636
5637
5638
5639
5640
5641 #define EC_CMD_REGULATOR_IS_ENABLED 0x012E
5642
5643 struct ec_params_regulator_is_enabled {
5644 uint32_t index;
5645 } __ec_align4;
5646
5647 struct ec_response_regulator_is_enabled {
5648 uint8_t enabled;
5649 } __ec_align1;
5650
5651
5652
5653
5654
5655
5656
5657
5658
5659 #define EC_CMD_REGULATOR_SET_VOLTAGE 0x012F
5660
5661 struct ec_params_regulator_set_voltage {
5662 uint32_t index;
5663 uint32_t min_mv;
5664 uint32_t max_mv;
5665 } __ec_align4;
5666
5667
5668
5669
5670
5671
5672
5673 #define EC_CMD_REGULATOR_GET_VOLTAGE 0x0130
5674
5675 struct ec_params_regulator_get_voltage {
5676 uint32_t index;
5677 } __ec_align4;
5678
5679 struct ec_response_regulator_get_voltage {
5680 uint32_t voltage_mv;
5681 } __ec_align4;
5682
5683
5684
5685
5686
5687
5688
5689
5690
5691
5692
5693
5694 #define EC_CMD_TYPEC_DISCOVERY 0x0131
5695
5696 enum typec_partner_type {
5697 TYPEC_PARTNER_SOP = 0,
5698 TYPEC_PARTNER_SOP_PRIME = 1,
5699 };
5700
5701 struct ec_params_typec_discovery {
5702 uint8_t port;
5703 uint8_t partner_type;
5704 } __ec_align1;
5705
5706 struct svid_mode_info {
5707 uint16_t svid;
5708 uint16_t mode_count;
5709 uint32_t mode_vdo[6];
5710 };
5711
5712 struct ec_response_typec_discovery {
5713 uint8_t identity_count;
5714 uint8_t svid_count;
5715 uint16_t reserved;
5716 uint32_t discovery_vdo[6];
5717 struct svid_mode_info svids[];
5718 } __ec_align1;
5719
5720
5721 #define EC_CMD_TYPEC_CONTROL 0x0132
5722
5723 enum typec_control_command {
5724 TYPEC_CONTROL_COMMAND_EXIT_MODES,
5725 TYPEC_CONTROL_COMMAND_CLEAR_EVENTS,
5726 TYPEC_CONTROL_COMMAND_ENTER_MODE,
5727 };
5728
5729 struct ec_params_typec_control {
5730 uint8_t port;
5731 uint8_t command;
5732 uint16_t reserved;
5733
5734
5735
5736
5737
5738
5739 union {
5740 uint32_t clear_events_mask;
5741 uint8_t mode_to_enter;
5742 uint8_t placeholder[128];
5743 };
5744 } __ec_align1;
5745
5746
5747
5748
5749
5750
5751
5752
5753
5754
5755
5756 #define EC_CMD_TYPEC_STATUS 0x0133
5757
5758
5759
5760
5761
5762
5763
5764
5765 enum pd_power_role {
5766 PD_ROLE_SINK = 0,
5767 PD_ROLE_SOURCE = 1
5768 };
5769
5770
5771
5772
5773
5774
5775
5776
5777 enum pd_data_role {
5778 PD_ROLE_UFP = 0,
5779 PD_ROLE_DFP = 1,
5780 PD_ROLE_DISCONNECTED = 2,
5781 };
5782
5783 enum pd_vconn_role {
5784 PD_ROLE_VCONN_OFF = 0,
5785 PD_ROLE_VCONN_SRC = 1,
5786 };
5787
5788
5789
5790
5791
5792 enum tcpc_cc_polarity {
5793
5794
5795
5796
5797
5798 POLARITY_CC1 = 0,
5799 POLARITY_CC2 = 1,
5800
5801
5802
5803
5804
5805 POLARITY_CC1_DTS = 2,
5806 POLARITY_CC2_DTS = 3,
5807
5808
5809
5810
5811
5812
5813
5814 POLARITY_COUNT
5815 };
5816
5817 #define PD_STATUS_EVENT_SOP_DISC_DONE BIT(0)
5818 #define PD_STATUS_EVENT_SOP_PRIME_DISC_DONE BIT(1)
5819 #define PD_STATUS_EVENT_HARD_RESET BIT(2)
5820
5821 struct ec_params_typec_status {
5822 uint8_t port;
5823 } __ec_align1;
5824
5825 struct ec_response_typec_status {
5826 uint8_t pd_enabled;
5827 uint8_t dev_connected;
5828 uint8_t sop_connected;
5829 uint8_t source_cap_count;
5830
5831 uint8_t power_role;
5832 uint8_t data_role;
5833 uint8_t vconn_role;
5834 uint8_t sink_cap_count;
5835
5836 uint8_t polarity;
5837 uint8_t cc_state;
5838 uint8_t dp_pin;
5839 uint8_t mux_state;
5840
5841 char tc_state[32];
5842
5843 uint32_t events;
5844
5845
5846
5847
5848
5849
5850
5851
5852
5853
5854
5855 uint16_t sop_revision;
5856 uint16_t sop_prime_revision;
5857
5858 uint32_t source_cap_pdos[7];
5859
5860 uint32_t sink_cap_pdos[7];
5861 } __ec_align1;
5862
5863
5864
5865
5866
5867
5868
5869
5870 #define EC_CMD_CR51_BASE 0x0300
5871 #define EC_CMD_CR51_LAST 0x03FF
5872
5873
5874
5875
5876
5877 #define EC_CMD_FP_PASSTHRU 0x0400
5878
5879 #define EC_FP_FLAG_NOT_COMPLETE 0x1
5880
5881 struct ec_params_fp_passthru {
5882 uint16_t len;
5883 uint16_t flags;
5884 uint8_t data[];
5885 } __ec_align2;
5886
5887
5888 #define EC_CMD_FP_MODE 0x0402
5889
5890
5891 #define FP_MODE_DEEPSLEEP BIT(0)
5892
5893 #define FP_MODE_FINGER_DOWN BIT(1)
5894
5895 #define FP_MODE_FINGER_UP BIT(2)
5896
5897 #define FP_MODE_CAPTURE BIT(3)
5898
5899 #define FP_MODE_ENROLL_SESSION BIT(4)
5900
5901 #define FP_MODE_ENROLL_IMAGE BIT(5)
5902
5903 #define FP_MODE_MATCH BIT(6)
5904
5905 #define FP_MODE_RESET_SENSOR BIT(7)
5906
5907 #define FP_MODE_DONT_CHANGE BIT(31)
5908
5909 #define FP_VALID_MODES (FP_MODE_DEEPSLEEP | \
5910 FP_MODE_FINGER_DOWN | \
5911 FP_MODE_FINGER_UP | \
5912 FP_MODE_CAPTURE | \
5913 FP_MODE_ENROLL_SESSION | \
5914 FP_MODE_ENROLL_IMAGE | \
5915 FP_MODE_MATCH | \
5916 FP_MODE_RESET_SENSOR | \
5917 FP_MODE_DONT_CHANGE)
5918
5919
5920 #define FP_MODE_CAPTURE_TYPE_SHIFT 28
5921 #define FP_MODE_CAPTURE_TYPE_MASK (0x7 << FP_MODE_CAPTURE_TYPE_SHIFT)
5922
5923
5924
5925
5926 enum fp_capture_type {
5927
5928 FP_CAPTURE_VENDOR_FORMAT = 0,
5929
5930 FP_CAPTURE_SIMPLE_IMAGE = 1,
5931
5932 FP_CAPTURE_PATTERN0 = 2,
5933
5934 FP_CAPTURE_PATTERN1 = 3,
5935
5936 FP_CAPTURE_QUALITY_TEST = 4,
5937
5938 FP_CAPTURE_RESET_TEST = 5,
5939 FP_CAPTURE_TYPE_MAX,
5940 };
5941
5942 #define FP_CAPTURE_TYPE(mode) (((mode) & FP_MODE_CAPTURE_TYPE_MASK) \
5943 >> FP_MODE_CAPTURE_TYPE_SHIFT)
5944
5945 struct ec_params_fp_mode {
5946 uint32_t mode;
5947 } __ec_align4;
5948
5949 struct ec_response_fp_mode {
5950 uint32_t mode;
5951 } __ec_align4;
5952
5953
5954 #define EC_CMD_FP_INFO 0x0403
5955
5956
5957 #define FP_ERROR_DEAD_PIXELS(errors) ((errors) & 0x3FF)
5958
5959 #define FP_ERROR_DEAD_PIXELS_UNKNOWN (0x3FF)
5960
5961 #define FP_ERROR_NO_IRQ BIT(12)
5962
5963 #define FP_ERROR_SPI_COMM BIT(13)
5964
5965 #define FP_ERROR_BAD_HWID BIT(14)
5966
5967 #define FP_ERROR_INIT_FAIL BIT(15)
5968
5969 struct ec_response_fp_info_v0 {
5970
5971 uint32_t vendor_id;
5972 uint32_t product_id;
5973 uint32_t model_id;
5974 uint32_t version;
5975
5976 uint32_t frame_size;
5977 uint32_t pixel_format;
5978 uint16_t width;
5979 uint16_t height;
5980 uint16_t bpp;
5981 uint16_t errors;
5982 } __ec_align4;
5983
5984 struct ec_response_fp_info {
5985
5986 uint32_t vendor_id;
5987 uint32_t product_id;
5988 uint32_t model_id;
5989 uint32_t version;
5990
5991 uint32_t frame_size;
5992 uint32_t pixel_format;
5993 uint16_t width;
5994 uint16_t height;
5995 uint16_t bpp;
5996 uint16_t errors;
5997
5998 uint32_t template_size;
5999 uint16_t template_max;
6000 uint16_t template_valid;
6001 uint32_t template_dirty;
6002 uint32_t template_version;
6003 } __ec_align4;
6004
6005
6006 #define EC_CMD_FP_FRAME 0x0404
6007
6008
6009 #define FP_FRAME_INDEX_SHIFT 28
6010
6011 #define FP_FRAME_INDEX_RAW_IMAGE 0
6012
6013 #define FP_FRAME_INDEX_TEMPLATE 1
6014 #define FP_FRAME_GET_BUFFER_INDEX(offset) ((offset) >> FP_FRAME_INDEX_SHIFT)
6015 #define FP_FRAME_OFFSET_MASK 0x0FFFFFFF
6016
6017
6018 #define FP_TEMPLATE_FORMAT_VERSION 3
6019
6020
6021 #define FP_CONTEXT_NONCE_BYTES 12
6022 #define FP_CONTEXT_USERID_WORDS (32 / sizeof(uint32_t))
6023 #define FP_CONTEXT_TAG_BYTES 16
6024 #define FP_CONTEXT_SALT_BYTES 16
6025 #define FP_CONTEXT_TPM_BYTES 32
6026
6027 struct ec_fp_template_encryption_metadata {
6028
6029
6030
6031 uint16_t struct_version;
6032
6033 uint16_t reserved;
6034
6035
6036
6037
6038 uint8_t nonce[FP_CONTEXT_NONCE_BYTES];
6039 uint8_t salt[FP_CONTEXT_SALT_BYTES];
6040 uint8_t tag[FP_CONTEXT_TAG_BYTES];
6041 };
6042
6043 struct ec_params_fp_frame {
6044
6045
6046
6047
6048
6049 uint32_t offset;
6050 uint32_t size;
6051 } __ec_align4;
6052
6053
6054 #define EC_CMD_FP_TEMPLATE 0x0405
6055
6056
6057 #define FP_TEMPLATE_COMMIT 0x80000000
6058
6059 struct ec_params_fp_template {
6060 uint32_t offset;
6061 uint32_t size;
6062 uint8_t data[];
6063 } __ec_align4;
6064
6065
6066 #define EC_CMD_FP_CONTEXT 0x0406
6067
6068 struct ec_params_fp_context {
6069 uint32_t userid[FP_CONTEXT_USERID_WORDS];
6070 } __ec_align4;
6071
6072 #define EC_CMD_FP_STATS 0x0407
6073
6074 #define FPSTATS_CAPTURE_INV BIT(0)
6075 #define FPSTATS_MATCHING_INV BIT(1)
6076
6077 struct ec_response_fp_stats {
6078 uint32_t capture_time_us;
6079 uint32_t matching_time_us;
6080 uint32_t overall_time_us;
6081 struct {
6082 uint32_t lo;
6083 uint32_t hi;
6084 } overall_t0;
6085 uint8_t timestamps_invalid;
6086 int8_t template_matched;
6087 } __ec_align2;
6088
6089 #define EC_CMD_FP_SEED 0x0408
6090 struct ec_params_fp_seed {
6091
6092
6093
6094 uint16_t struct_version;
6095
6096 uint16_t reserved;
6097
6098 uint8_t seed[FP_CONTEXT_TPM_BYTES];
6099 } __ec_align4;
6100
6101 #define EC_CMD_FP_ENC_STATUS 0x0409
6102
6103
6104 #define FP_ENC_STATUS_SEED_SET BIT(0)
6105
6106 struct ec_response_fp_encryption_status {
6107
6108 uint32_t valid_flags;
6109
6110 uint32_t status;
6111 } __ec_align4;
6112
6113
6114
6115
6116
6117 #define EC_CMD_TP_SELF_TEST 0x0500
6118
6119
6120 #define EC_CMD_TP_FRAME_INFO 0x0501
6121
6122 struct ec_response_tp_frame_info {
6123 uint32_t n_frames;
6124 uint32_t frame_sizes[];
6125 } __ec_align4;
6126
6127
6128 #define EC_CMD_TP_FRAME_SNAPSHOT 0x0502
6129
6130
6131 #define EC_CMD_TP_FRAME_GET 0x0503
6132
6133 struct ec_params_tp_frame_get {
6134 uint32_t frame_index;
6135 uint32_t offset;
6136 uint32_t size;
6137 } __ec_align4;
6138
6139
6140
6141
6142 #define EC_COMM_TEXT_MAX 8
6143
6144
6145
6146
6147
6148 #define EC_CMD_BATTERY_GET_STATIC 0x0600
6149
6150
6151
6152
6153
6154 struct ec_params_battery_static_info {
6155 uint8_t index;
6156 } __ec_align_size1;
6157
6158
6159
6160
6161
6162
6163
6164
6165
6166
6167
6168 struct ec_response_battery_static_info {
6169 uint16_t design_capacity;
6170 uint16_t design_voltage;
6171 char manufacturer[EC_COMM_TEXT_MAX];
6172 char model[EC_COMM_TEXT_MAX];
6173 char serial[EC_COMM_TEXT_MAX];
6174 char type[EC_COMM_TEXT_MAX];
6175
6176 uint32_t cycle_count;
6177 } __ec_align4;
6178
6179
6180
6181
6182
6183 #define EC_CMD_BATTERY_GET_DYNAMIC 0x0601
6184
6185
6186
6187
6188
6189 struct ec_params_battery_dynamic_info {
6190 uint8_t index;
6191 } __ec_align_size1;
6192
6193
6194
6195
6196
6197
6198
6199
6200
6201
6202
6203 struct ec_response_battery_dynamic_info {
6204 int16_t actual_voltage;
6205 int16_t actual_current;
6206 int16_t remaining_capacity;
6207 int16_t full_capacity;
6208 int16_t flags;
6209 int16_t desired_voltage;
6210 int16_t desired_current;
6211 } __ec_align2;
6212
6213
6214
6215
6216 #define EC_CMD_CHARGER_CONTROL 0x0602
6217
6218
6219
6220
6221
6222
6223
6224
6225
6226
6227
6228 struct ec_params_charger_control {
6229 int16_t max_current;
6230 uint16_t otg_voltage;
6231 uint8_t allow_charging;
6232 } __ec_align_size1;
6233
6234
6235 #define EC_CMD_USB_PD_MUX_ACK 0x0603
6236
6237 struct ec_params_usb_pd_mux_ack {
6238 uint8_t port;
6239 } __ec_align1;
6240
6241
6242
6243
6244
6245
6246
6247
6248
6249
6250
6251
6252
6253
6254
6255
6256
6257
6258
6259
6260
6261
6262
6263
6264
6265
6266
6267 #define EC_CMD_BOARD_SPECIFIC_BASE 0x3E00
6268 #define EC_CMD_BOARD_SPECIFIC_LAST 0x3FFF
6269
6270
6271
6272
6273
6274 #define EC_PRIVATE_HOST_COMMAND_VALUE(command) \
6275 (EC_CMD_BOARD_SPECIFIC_BASE + (command))
6276
6277
6278
6279
6280
6281
6282
6283
6284
6285
6286
6287
6288
6289
6290
6291
6292
6293
6294
6295
6296
6297
6298
6299
6300
6301 #define EC_CMD_PASSTHRU_OFFSET(n) (0x4000 * (n))
6302 #define EC_CMD_PASSTHRU_MAX(n) (EC_CMD_PASSTHRU_OFFSET(n) + 0x3fff)
6303
6304
6305
6306
6307
6308
6309
6310
6311 #define EC_HOST_PARAM_SIZE EC_PROTO2_MAX_PARAM_SIZE
6312 #define EC_LPC_ADDR_OLD_PARAM EC_HOST_CMD_REGION1
6313 #define EC_OLD_PARAM_SIZE EC_HOST_CMD_REGION_SIZE
6314
6315
6316
6317 #endif