linux/phy/phy-mipi-dphy.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2018 Cadence Design Systems Inc.
0004  */
0005
0006 #ifndef __PHY_MIPI_DPHY_H_
0007 #define __PHY_MIPI_DPHY_H_
0008
0009 /**
0010  * struct phy_configure_opts_mipi_dphy - MIPI D-PHY configuration set
0011  *
0012  * This structure is used to represent the configuration state of a
0013  * MIPI D-PHY phy.
0014  */
0015 struct phy_configure_opts_mipi_dphy {
0016     /**
0017      * @clk_miss:
0018      *
0019      * Timeout, in picoseconds, for receiver to detect absence of
0020      * Clock transitions and disable the Clock Lane HS-RX.
0021      *
0022      * Maximum value: 60000 ps
0023      */
0024     unsigned int        clk_miss;
0025
0026     /**
0027      * @clk_post:
0028      *
0029      * Time, in picoseconds, that the transmitter continues to
0030      * send HS clock after the last associated Data Lane has
0031      * transitioned to LP Mode. Interval is defined as the period
0032      * from the end of @hs_trail to the beginning of @clk_trail.
0033      *
0034      * Minimum value: 60000 ps + 52 * @hs_clk_rate period in ps
0035      */
0036     unsigned int        clk_post;
0037
0038     /**
0039      * @clk_pre:
0040      *
0041      * Time, in UI, that the HS clock shall be driven by
0042      * the transmitter prior to any associated Data Lane beginning
0043      * the transition from LP to HS mode.
0044      *
0045      * Minimum value: 8 UI
0046      */
0047     unsigned int        clk_pre;
0048
0049     /**
0050      * @clk_prepare:
0051      *
0052      * Time, in picoseconds, that the transmitter drives the Clock
0053      * Lane LP-00 Line state immediately before the HS-0 Line
0054      * state starting the HS transmission.
0055      *
0056      * Minimum value: 38000 ps
0057      * Maximum value: 95000 ps
0058      */
0059     unsigned int        clk_prepare;
0060
0061     /**
0062      * @clk_settle:
0063      *
0064      * Time interval, in picoseconds, during which the HS receiver
0065      * should ignore any Clock Lane HS transitions, starting from
0066      * the beginning of @clk_prepare.
0067      *
0068      * Minimum value: 95000 ps
0069      * Maximum value: 300000 ps
0070      */
0071     unsigned int        clk_settle;
0072
0073     /**
0074      * @clk_term_en:
0075      *
0076      * Time, in picoseconds, for the Clock Lane receiver to enable
0077      * the HS line termination.
0078      *
0079      * Maximum value: 38000 ps
0080      */
0081     unsigned int        clk_term_en;
0082
0083     /**
0084      * @clk_trail:
0085      *
0086      * Time, in picoseconds, that the transmitter drives the HS-0
0087      * state after the last payload clock bit of a HS transmission
0088      * burst.
0089      *
0090      * Minimum value: 60000 ps
0091      */
0092     unsigned int        clk_trail;
0093
0094     /**
0095      * @clk_zero:
0096      *
0097      * Time, in picoseconds, that the transmitter drives the HS-0
0098      * state prior to starting the Clock.
0099      */
0100     unsigned int        clk_zero;
0101
0102     /**
0103      * @d_term_en:
0104      *
0105      * Time, in picoseconds, for the Data Lane receiver to enable
0106      * the HS line termination.
0107      *
0108      * Maximum value: 35000 ps + 4 * @hs_clk_rate period in ps
0109      */
0110     unsigned int        d_term_en;
0111
0112     /**
0113      * @eot:
0114      *
0115      * Transmitted time interval, in picoseconds, from the start
0116      * of @hs_trail or @clk_trail, to the start of the LP- 11
0117      * state following a HS burst.
0118      *
0119      * Maximum value: 105000 ps + 12 * @hs_clk_rate period in ps
0120      */
0121     unsigned int        eot;
0122
0123     /**
0124      * @hs_exit:
0125      *
0126      * Time, in picoseconds, that the transmitter drives LP-11
0127      * following a HS burst.
0128      *
0129      * Minimum value: 100000 ps
0130      */
0131     unsigned int        hs_exit;
0132
0133     /**
0134      * @hs_prepare:
0135      *
0136      * Time, in picoseconds, that the transmitter drives the Data
0137      * Lane LP-00 Line state immediately before the HS-0 Line
0138      * state starting the HS transmission.
0139      *
0140      * Minimum value: 40000 ps + 4 * @hs_clk_rate period in ps
0141      * Maximum value: 85000 ps + 6 * @hs_clk_rate period in ps
0142      */
0143     unsigned int        hs_prepare;
0144
0145     /**
0146      * @hs_settle:
0147      *
0148      * Time interval, in picoseconds, during which the HS receiver
0149      * shall ignore any Data Lane HS transitions, starting from
0150      * the beginning of @hs_prepare.
0151      *
0152      * Minimum value: 85000 ps + 6 * @hs_clk_rate period in ps
0153      * Maximum value: 145000 ps + 10 * @hs_clk_rate period in ps
0154      */
0155     unsigned int        hs_settle;
0156
0157     /**
0158      * @hs_skip:
0159      *
0160      * Time interval, in picoseconds, during which the HS-RX
0161      * should ignore any transitions on the Data Lane, following a
0162      * HS burst. The end point of the interval is defined as the
0163      * beginning of the LP-11 state following the HS burst.
0164      *
0165      * Minimum value: 40000 ps
0166      * Maximum value: 55000 ps + 4 * @hs_clk_rate period in ps
0167      */
0168     unsigned int        hs_skip;
0169
0170     /**
0171      * @hs_trail:
0172      *
0173      * Time, in picoseconds, that the transmitter drives the
0174      * flipped differential state after last payload data bit of a
0175      * HS transmission burst
0176      *
0177      * Minimum value: max(8 * @hs_clk_rate period in ps,
0178      *            60000 ps + 4 * @hs_clk_rate period in ps)
0179      */
0180     unsigned int        hs_trail;
0181
0182     /**
0183      * @hs_zero:
0184      *
0185      * Time, in picoseconds, that the transmitter drives the HS-0
0186      * state prior to transmitting the Sync sequence.
0187      */
0188     unsigned int        hs_zero;
0189
0190     /**
0191      * @init:
0192      *
0193      * Time, in microseconds for the initialization period to
0194      * complete.
0195      *
0196      * Minimum value: 100 us
0197      */
0198     unsigned int        init;
0199
0200     /**
0201      * @lpx:
0202      *
0203      * Transmitted length, in picoseconds, of any Low-Power state
0204      * period.
0205      *
0206      * Minimum value: 50000 ps
0207      */
0208     unsigned int        lpx;
0209
0210     /**
0211      * @ta_get:
0212      *
0213      * Time, in picoseconds, that the new transmitter drives the
0214      * Bridge state (LP-00) after accepting control during a Link
0215      * Turnaround.
0216      *
0217      * Value: 5 * @lpx
0218      */
0219     unsigned int        ta_get;
0220
0221     /**
0222      * @ta_go:
0223      *
0224      * Time, in picoseconds, that the transmitter drives the
0225      * Bridge state (LP-00) before releasing control during a Link
0226      * Turnaround.
0227      *
0228      * Value: 4 * @lpx
0229      */
0230     unsigned int        ta_go;
0231
0232     /**
0233      * @ta_sure:
0234      *
0235      * Time, in picoseconds, that the new transmitter waits after
0236      * the LP-10 state before transmitting the Bridge state
0237      * (LP-00) during a Link Turnaround.
0238      *
0239      * Minimum value: @lpx
0240      * Maximum value: 2 * @lpx
0241      */
0242     unsigned int        ta_sure;
0243
0244     /**
0245      * @wakeup:
0246      *
0247      * Time, in microseconds, that a transmitter drives a Mark-1
0248      * state prior to a Stop state in order to initiate an exit
0249      * from ULPS.
0250      *
0251      * Minimum value: 1000 us
0252      */
0253     unsigned int        wakeup;
0254
0255     /**
0256      * @hs_clk_rate:
0257      *
0258      * Clock rate, in Hertz, of the high-speed clock.
0259      */
0260     unsigned long       hs_clk_rate;
0261
0262     /**
0263      * @lp_clk_rate:
0264      *
0265      * Clock rate, in Hertz, of the low-power clock.
0266      */
0267     unsigned long       lp_clk_rate;
0268
0269     /**
0270      * @lanes:
0271      *
0272      * Number of active, consecutive, data lanes, starting from
0273      * lane 0, used for the transmissions.
0274      */
0275     unsigned char       lanes;
0276 };
0277
0278 int phy_mipi_dphy_get_default_config(unsigned long pixel_clock,
0279                      unsigned int bpp,
0280                      unsigned int lanes,
0281                      struct phy_configure_opts_mipi_dphy *cfg);
0282 int phy_mipi_dphy_config_validate(struct phy_configure_opts_mipi_dphy *cfg);
0283
0284 #endif /* __PHY_MIPI_DPHY_H_ */