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OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2020,2022 NXP
0004  */
0005 
0006 #ifndef __PHY_LVDS_H_
0007 #define __PHY_LVDS_H_
0008 
0009 /**
0010  * struct phy_configure_opts_lvds - LVDS configuration set
0011  * @bits_per_lane_and_dclk_cycle:   Number of bits per lane per differential
0012  *                  clock cycle.
0013  * @differential_clk_rate:      Clock rate, in Hertz, of the LVDS
0014  *                  differential clock.
0015  * @lanes:              Number of active, consecutive,
0016  *                  data lanes, starting from lane 0,
0017  *                  used for the transmissions.
0018  * @is_slave:               Boolean, true if the phy is a slave
0019  *                  which works together with a master
0020  *                  phy to support dual link transmission,
0021  *                  otherwise a regular phy or a master phy.
0022  *
0023  * This structure is used to represent the configuration state of a LVDS phy.
0024  */
0025 struct phy_configure_opts_lvds {
0026     unsigned int    bits_per_lane_and_dclk_cycle;
0027     unsigned long   differential_clk_rate;
0028     unsigned int    lanes;
0029     bool        is_slave;
0030 };
0031 
0032 #endif /* __PHY_LVDS_H_ */