linux/phy/phy-dp.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2019 Cadence Design Systems Inc.
0004  */
0005
0006 #ifndef __PHY_DP_H_
0007 #define __PHY_DP_H_
0008
0009 #include <linux/types.h>
0010
0011 /**
0012  * struct phy_configure_opts_dp - DisplayPort PHY configuration set
0013  *
0014  * This structure is used to represent the configuration state of a
0015  * DisplayPort phy.
0016  */
0017 struct phy_configure_opts_dp {
0018     /**
0019      * @link_rate:
0020      *
0021      * Link Rate, in Mb/s, of the main link.
0022      *
0023      * Allowed values: 1620, 2160, 2430, 2700, 3240, 4320, 5400, 8100 Mb/s
0024      */
0025     unsigned int link_rate;
0026
0027     /**
0028      * @lanes:
0029      *
0030      * Number of active, consecutive, data lanes, starting from
0031      * lane 0, used for the transmissions on main link.
0032      *
0033      * Allowed values: 1, 2, 4
0034      */
0035     unsigned int lanes;
0036
0037     /**
0038      * @voltage:
0039      *
0040      * Voltage swing levels, as specified by DisplayPort specification,
0041      * to be used by particular lanes. One value per lane.
0042      * voltage[0] is for lane 0, voltage[1] is for lane 1, etc.
0043      *
0044      * Maximum value: 3
0045      */
0046     unsigned int voltage[4];
0047
0048     /**
0049      * @pre:
0050      *
0051      * Pre-emphasis levels, as specified by DisplayPort specification, to be
0052      * used by particular lanes. One value per lane.
0053      *
0054      * Maximum value: 3
0055      */
0056     unsigned int pre[4];
0057
0058     /**
0059      * @ssc:
0060      *
0061      * Flag indicating, whether or not to enable spread-spectrum clocking.
0062      *
0063      */
0064     u8 ssc : 1;
0065
0066     /**
0067      * @set_rate:
0068      *
0069      * Flag indicating, whether or not reconfigure link rate and SSC to
0070      * requested values.
0071      *
0072      */
0073     u8 set_rate : 1;
0074
0075     /**
0076      * @set_lanes:
0077      *
0078      * Flag indicating, whether or not reconfigure lane count to
0079      * requested value.
0080      *
0081      */
0082     u8 set_lanes : 1;
0083
0084     /**
0085      * @set_voltages:
0086      *
0087      * Flag indicating, whether or not reconfigure voltage swing
0088      * and pre-emphasis to requested values. Only lanes specified
0089      * by "lanes" parameter will be affected.
0090      *
0091      */
0092     u8 set_voltages : 1;
0093 };
0094
0095 #endif /* __PHY_DP_H_ */