linux/phy/omap_control_phy.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * omap_control_phy.h - Header file for the PHY part of control module.
0004  *
0005  * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com
0006  * Author: Kishon Vijay Abraham I <kishon@ti.com>
0007  */
0008
0009 #ifndef __OMAP_CONTROL_PHY_H__
0010 #define __OMAP_CONTROL_PHY_H__
0011
0012 enum omap_control_phy_type {
0013     OMAP_CTRL_TYPE_OTGHS = 1,   /* Mailbox OTGHS_CONTROL */
0014     OMAP_CTRL_TYPE_USB2,    /* USB2_PHY, power down in CONTROL_DEV_CONF */
0015     OMAP_CTRL_TYPE_PIPE3,   /* PIPE3 PHY, DPLL & seperate Rx/Tx power */
0016     OMAP_CTRL_TYPE_PCIE,    /* RX TX control of ACSPCIE */
0017     OMAP_CTRL_TYPE_DRA7USB2, /* USB2 PHY, power and power_aux e.g. DRA7 */
0018     OMAP_CTRL_TYPE_AM437USB2, /* USB2 PHY, power e.g. AM437x */
0019 };
0020
0021 struct omap_control_phy {
0022     struct device *dev;
0023
0024     u32 __iomem *otghs_control;
0025     u32 __iomem *power;
0026     u32 __iomem *power_aux;
0027     u32 __iomem *pcie_pcs;
0028
0029     struct clk *sys_clk;
0030
0031     enum omap_control_phy_type type;
0032 };
0033
0034 enum omap_control_usb_mode {
0035     USB_MODE_UNDEFINED = 0,
0036     USB_MODE_HOST,
0037     USB_MODE_DEVICE,
0038     USB_MODE_DISCONNECT,
0039 };
0040
0041 #define OMAP_CTRL_DEV_PHY_PD        BIT(0)
0042
0043 #define OMAP_CTRL_DEV_AVALID        BIT(0)
0044 #define OMAP_CTRL_DEV_BVALID        BIT(1)
0045 #define OMAP_CTRL_DEV_VBUSVALID     BIT(2)
0046 #define OMAP_CTRL_DEV_SESSEND       BIT(3)
0047 #define OMAP_CTRL_DEV_IDDIG     BIT(4)
0048
0049 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_MASK     0x003FC000
0050 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_CMD_SHIFT    0xE
0051
0052 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_MASK    0xFFC00000
0053 #define OMAP_CTRL_PIPE3_PHY_PWRCTL_CLK_FREQ_SHIFT   0x16
0054
0055 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWERON   0x3
0056 #define OMAP_CTRL_PIPE3_PHY_TX_RX_POWEROFF  0x0
0057
0058 #define OMAP_CTRL_PCIE_PCS_MASK         0xff
0059 #define OMAP_CTRL_PCIE_PCS_DELAY_COUNT_SHIFT    16
0060
0061 #define OMAP_CTRL_USB2_PHY_PD       BIT(28)
0062
0063 #define AM437X_CTRL_USB2_PHY_PD     BIT(0)
0064 #define AM437X_CTRL_USB2_OTG_PD     BIT(1)
0065 #define AM437X_CTRL_USB2_OTGVDET_EN BIT(19)
0066 #define AM437X_CTRL_USB2_OTGSESSEND_EN  BIT(20)
0067
0068 #if IS_ENABLED(CONFIG_OMAP_CONTROL_PHY)
0069 void omap_control_phy_power(struct device *dev, int on);
0070 void omap_control_usb_set_mode(struct device *dev,
0071                    enum omap_control_usb_mode mode);
0072 void omap_control_pcie_pcs(struct device *dev, u8 delay);
0073 #else
0074
0075 static inline void omap_control_phy_power(struct device *dev, int on)
0076 {
0077 }
0078
0079 static inline void omap_control_usb_set_mode(struct device *dev,
0080     enum omap_control_usb_mode mode)
0081 {
0082 }
0083
0084 static inline void omap_control_pcie_pcs(struct device *dev, u8 delay)
0085 {
0086 }
0087 #endif
0088
0089 #endif  /* __OMAP_CONTROL_PHY_H__ */