linux/perf/riscv_pmu.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2018 SiFive
0004  * Copyright (C) 2018 Andes Technology Corporation
0005  * Copyright (C) 2021 Western Digital Corporation or its affiliates.
0006  *
0007  */
0008
0009 #ifndef _ASM_RISCV_PERF_EVENT_H
0010 #define _ASM_RISCV_PERF_EVENT_H
0011
0012 #include <linux/perf_event.h>
0013 #include <linux/ptrace.h>
0014 #include <linux/interrupt.h>
0015
0016 #ifdef CONFIG_RISCV_PMU
0017
0018 /*
0019  * The RISCV_MAX_COUNTERS parameter should be specified.
0020  */
0021
0022 #define RISCV_MAX_COUNTERS  64
0023 #define RISCV_OP_UNSUPP     (-EOPNOTSUPP)
0024 #define RISCV_PMU_PDEV_NAME "riscv-pmu"
0025 #define RISCV_PMU_LEGACY_PDEV_NAME  "riscv-pmu-legacy"
0026
0027 #define RISCV_PMU_STOP_FLAG_RESET 1
0028
0029 struct cpu_hw_events {
0030     /* currently enabled events */
0031     int         n_events;
0032     /* Counter overflow interrupt */
0033     int     irq;
0034     /* currently enabled events */
0035     struct perf_event   *events[RISCV_MAX_COUNTERS];
0036     /* currently enabled hardware counters */
0037     DECLARE_BITMAP(used_hw_ctrs, RISCV_MAX_COUNTERS);
0038     /* currently enabled firmware counters */
0039     DECLARE_BITMAP(used_fw_ctrs, RISCV_MAX_COUNTERS);
0040 };
0041
0042 struct riscv_pmu {
0043     struct pmu  pmu;
0044     char        *name;
0045
0046     irqreturn_t (*handle_irq)(int irq_num, void *dev);
0047
0048     int     num_counters;
0049     u64     (*ctr_read)(struct perf_event *event);
0050     int     (*ctr_get_idx)(struct perf_event *event);
0051     int     (*ctr_get_width)(int idx);
0052     void        (*ctr_clear_idx)(struct perf_event *event);
0053     void        (*ctr_start)(struct perf_event *event, u64 init_val);
0054     void        (*ctr_stop)(struct perf_event *event, unsigned long flag);
0055     int     (*event_map)(struct perf_event *event, u64 *config);
0056
0057     struct cpu_hw_events    __percpu *hw_events;
0058     struct hlist_node   node;
0059     struct notifier_block   riscv_pm_nb;
0060 };
0061
0062 #define to_riscv_pmu(p) (container_of(p, struct riscv_pmu, pmu))
0063
0064 void riscv_pmu_start(struct perf_event *event, int flags);
0065 void riscv_pmu_stop(struct perf_event *event, int flags);
0066 unsigned long riscv_pmu_ctr_read_csr(unsigned long csr);
0067 int riscv_pmu_event_set_period(struct perf_event *event);
0068 uint64_t riscv_pmu_ctr_get_width_mask(struct perf_event *event);
0069 u64 riscv_pmu_event_update(struct perf_event *event);
0070 #ifdef CONFIG_RISCV_PMU_LEGACY
0071 void riscv_pmu_legacy_skip_init(void);
0072 #else
0073 static inline void riscv_pmu_legacy_skip_init(void) {};
0074 #endif
0075 struct riscv_pmu *riscv_pmu_alloc(void);
0076
0077 #endif /* CONFIG_RISCV_PMU */
0078
0079 #endif /* _ASM_RISCV_PERF_EVENT_H */