linux/perf/arm_pmu.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/arch/arm/include/asm/pmu.h
0004  *
0005  *  Copyright (C) 2009 picoChip Designs Ltd, Jamie Iles
0006  */
0007
0008 #ifndef __ARM_PMU_H__
0009 #define __ARM_PMU_H__
0010
0011 #include <linux/interrupt.h>
0012 #include <linux/perf_event.h>
0013 #include <linux/platform_device.h>
0014 #include <linux/sysfs.h>
0015 #include <asm/cputype.h>
0016
0017 #ifdef CONFIG_ARM_PMU
0018
0019 /*
0020  * The ARMv7 CPU PMU supports up to 32 event counters.
0021  */
0022 #define ARMPMU_MAX_HWEVENTS     32
0023
0024 /*
0025  * ARM PMU hw_event flags
0026  */
0027 /* Event uses a 64bit counter */
0028 #define ARMPMU_EVT_64BIT        1
0029 /* Event uses a 47bit counter */
0030 #define ARMPMU_EVT_47BIT        2
0031
0032 #define HW_OP_UNSUPPORTED       0xFFFF
0033 #define C(_x)               PERF_COUNT_HW_CACHE_##_x
0034 #define CACHE_OP_UNSUPPORTED        0xFFFF
0035
0036 #define PERF_MAP_ALL_UNSUPPORTED                    \
0037     [0 ... PERF_COUNT_HW_MAX - 1] = HW_OP_UNSUPPORTED
0038
0039 #define PERF_CACHE_MAP_ALL_UNSUPPORTED                  \
0040 [0 ... C(MAX) - 1] = {                          \
0041     [0 ... C(OP_MAX) - 1] = {                   \
0042         [0 ... C(RESULT_MAX) - 1] = CACHE_OP_UNSUPPORTED,   \
0043     },                              \
0044 }
0045
0046 /* The events for a given PMU register set. */
0047 struct pmu_hw_events {
0048     /*
0049      * The events that are active on the PMU for the given index.
0050      */
0051     struct perf_event   *events[ARMPMU_MAX_HWEVENTS];
0052
0053     /*
0054      * A 1 bit for an index indicates that the counter is being used for
0055      * an event. A 0 means that the counter can be used.
0056      */
0057     DECLARE_BITMAP(used_mask, ARMPMU_MAX_HWEVENTS);
0058
0059     /*
0060      * Hardware lock to serialize accesses to PMU registers. Needed for the
0061      * read/modify/write sequences.
0062      */
0063     raw_spinlock_t      pmu_lock;
0064
0065     /*
0066      * When using percpu IRQs, we need a percpu dev_id. Place it here as we
0067      * already have to allocate this struct per cpu.
0068      */
0069     struct arm_pmu      *percpu_pmu;
0070
0071     int irq;
0072 };
0073
0074 enum armpmu_attr_groups {
0075     ARMPMU_ATTR_GROUP_COMMON,
0076     ARMPMU_ATTR_GROUP_EVENTS,
0077     ARMPMU_ATTR_GROUP_FORMATS,
0078     ARMPMU_ATTR_GROUP_CAPS,
0079     ARMPMU_NR_ATTR_GROUPS
0080 };
0081
0082 struct arm_pmu {
0083     struct pmu  pmu;
0084     cpumask_t   supported_cpus;
0085     char        *name;
0086     int     pmuver;
0087     irqreturn_t (*handle_irq)(struct arm_pmu *pmu);
0088     void        (*enable)(struct perf_event *event);
0089     void        (*disable)(struct perf_event *event);
0090     int     (*get_event_idx)(struct pmu_hw_events *hw_events,
0091                      struct perf_event *event);
0092     void        (*clear_event_idx)(struct pmu_hw_events *hw_events,
0093                      struct perf_event *event);
0094     int     (*set_event_filter)(struct hw_perf_event *evt,
0095                         struct perf_event_attr *attr);
0096     u64     (*read_counter)(struct perf_event *event);
0097     void        (*write_counter)(struct perf_event *event, u64 val);
0098     void        (*start)(struct arm_pmu *);
0099     void        (*stop)(struct arm_pmu *);
0100     void        (*reset)(void *);
0101     int     (*map_event)(struct perf_event *event);
0102     int     (*filter_match)(struct perf_event *event);
0103     int     num_events;
0104     bool        secure_access; /* 32-bit ARM only */
0105 #define ARMV8_PMUV3_MAX_COMMON_EVENTS       0x40
0106     DECLARE_BITMAP(pmceid_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
0107 #define ARMV8_PMUV3_EXT_COMMON_EVENT_BASE   0x4000
0108     DECLARE_BITMAP(pmceid_ext_bitmap, ARMV8_PMUV3_MAX_COMMON_EVENTS);
0109     struct platform_device  *plat_device;
0110     struct pmu_hw_events    __percpu *hw_events;
0111     struct hlist_node   node;
0112     struct notifier_block   cpu_pm_nb;
0113     /* the attr_groups array must be NULL-terminated */
0114     const struct attribute_group *attr_groups[ARMPMU_NR_ATTR_GROUPS + 1];
0115     /* store the PMMIR_EL1 to expose slots */
0116     u64     reg_pmmir;
0117
0118     /* Only to be used by ACPI probing code */
0119     unsigned long acpi_cpuid;
0120 };
0121
0122 #define to_arm_pmu(p) (container_of(p, struct arm_pmu, pmu))
0123
0124 u64 armpmu_event_update(struct perf_event *event);
0125
0126 int armpmu_event_set_period(struct perf_event *event);
0127
0128 int armpmu_map_event(struct perf_event *event,
0129              const unsigned (*event_map)[PERF_COUNT_HW_MAX],
0130              const unsigned (*cache_map)[PERF_COUNT_HW_CACHE_MAX]
0131                         [PERF_COUNT_HW_CACHE_OP_MAX]
0132                         [PERF_COUNT_HW_CACHE_RESULT_MAX],
0133              u32 raw_event_mask);
0134
0135 typedef int (*armpmu_init_fn)(struct arm_pmu *);
0136
0137 struct pmu_probe_info {
0138     unsigned int cpuid;
0139     unsigned int mask;
0140     armpmu_init_fn init;
0141 };
0142
0143 #define PMU_PROBE(_cpuid, _mask, _fn)   \
0144 {                   \
0145     .cpuid = (_cpuid),      \
0146     .mask = (_mask),        \
0147     .init = (_fn),          \
0148 }
0149
0150 #define ARM_PMU_PROBE(_cpuid, _fn) \
0151     PMU_PROBE(_cpuid, ARM_CPU_PART_MASK, _fn)
0152
0153 #define ARM_PMU_XSCALE_MASK ((0xff << 24) | ARM_CPU_XSCALE_ARCH_MASK)
0154
0155 #define XSCALE_PMU_PROBE(_version, _fn) \
0156     PMU_PROBE(ARM_CPU_IMP_INTEL << 24 | _version, ARM_PMU_XSCALE_MASK, _fn)
0157
0158 int arm_pmu_device_probe(struct platform_device *pdev,
0159              const struct of_device_id *of_table,
0160              const struct pmu_probe_info *probe_table);
0161
0162 #ifdef CONFIG_ACPI
0163 int arm_pmu_acpi_probe(armpmu_init_fn init_fn);
0164 #else
0165 static inline int arm_pmu_acpi_probe(armpmu_init_fn init_fn) { return 0; }
0166 #endif
0167
0168 #ifdef CONFIG_KVM
0169 void kvm_host_pmu_init(struct arm_pmu *pmu);
0170 #else
0171 #define kvm_host_pmu_init(x)    do { } while(0)
0172 #endif
0173
0174 /* Internal functions only for core arm_pmu code */
0175 struct arm_pmu *armpmu_alloc(void);
0176 struct arm_pmu *armpmu_alloc_atomic(void);
0177 void armpmu_free(struct arm_pmu *pmu);
0178 int armpmu_register(struct arm_pmu *pmu);
0179 int armpmu_request_irq(int irq, int cpu);
0180 void armpmu_free_irq(int irq, int cpu);
0181
0182 #define ARMV8_PMU_PDEV_NAME "armv8-pmu"
0183
0184 #endif /* CONFIG_ARM_PMU */
0185
0186 #define ARMV8_SPE_PDEV_NAME "arm,spe-v1"
0187
0188 #endif /* __ARM_PMU_H__ */