include/linux/pci-ecam.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright 2016 Broadcom
0004  */
0005 #ifndef DRIVERS_PCI_ECAM_H
0006 #define DRIVERS_PCI_ECAM_H
0007
0008 #include <linux/pci.h>
0009 #include <linux/kernel.h>
0010 #include <linux/platform_device.h>
0011
0012 /*
0013  * Memory address shift values for the byte-level address that
0014  * can be used when accessing the PCI Express Configuration Space.
0015  */
0016
0017 /*
0018  * Enhanced Configuration Access Mechanism (ECAM)
0019  *
0020  * See PCI Express Base Specification, Revision 5.0, Version 1.0,
0021  * Section 7.2.2, Table 7-1, p. 677.
0022  */
0023 #define PCIE_ECAM_BUS_SHIFT 20 /* Bus number */
0024 #define PCIE_ECAM_DEVFN_SHIFT   12 /* Device and Function number */
0025
0026 #define PCIE_ECAM_BUS_MASK  0xff
0027 #define PCIE_ECAM_DEVFN_MASK    0xff
0028 #define PCIE_ECAM_REG_MASK  0xfff /* Limit offset to a maximum of 4K */
0029
0030 #define PCIE_ECAM_BUS(x)    (((x) & PCIE_ECAM_BUS_MASK) << PCIE_ECAM_BUS_SHIFT)
0031 #define PCIE_ECAM_DEVFN(x)  (((x) & PCIE_ECAM_DEVFN_MASK) << PCIE_ECAM_DEVFN_SHIFT)
0032 #define PCIE_ECAM_REG(x)    ((x) & PCIE_ECAM_REG_MASK)
0033
0034 #define PCIE_ECAM_OFFSET(bus, devfn, where) \
0035     (PCIE_ECAM_BUS(bus) | \
0036      PCIE_ECAM_DEVFN(devfn) | \
0037      PCIE_ECAM_REG(where))
0038
0039 /*
0040  * struct to hold pci ops and bus shift of the config window
0041  * for a PCI controller.
0042  */
0043 struct pci_config_window;
0044 struct pci_ecam_ops {
0045     unsigned int            bus_shift;
0046     struct pci_ops          pci_ops;
0047     int             (*init)(struct pci_config_window *);
0048 };
0049
0050 /*
0051  * struct to hold the mappings of a config space window. This
0052  * is expected to be used as sysdata for PCI controllers that
0053  * use ECAM.
0054  */
0055 struct pci_config_window {
0056     struct resource         res;
0057     struct resource         busr;
0058     unsigned int            bus_shift;
0059     void                *priv;
0060     const struct pci_ecam_ops   *ops;
0061     union {
0062         void __iomem        *win;   /* 64-bit single mapping */
0063         void __iomem        **winp; /* 32-bit per-bus mapping */
0064     };
0065     struct device           *parent;/* ECAM res was from this dev */
0066 };
0067
0068 /* create and free pci_config_window */
0069 struct pci_config_window *pci_ecam_create(struct device *dev,
0070         struct resource *cfgres, struct resource *busr,
0071         const struct pci_ecam_ops *ops);
0072 void pci_ecam_free(struct pci_config_window *cfg);
0073
0074 /* map_bus when ->sysdata is an instance of pci_config_window */
0075 void __iomem *pci_ecam_map_bus(struct pci_bus *bus, unsigned int devfn,
0076                    int where);
0077 /* default ECAM ops */
0078 extern const struct pci_ecam_ops pci_generic_ecam_ops;
0079
0080 #if defined(CONFIG_ACPI) && defined(CONFIG_PCI_QUIRKS)
0081 extern const struct pci_ecam_ops pci_32b_ops;   /* 32-bit accesses only */
0082 extern const struct pci_ecam_ops pci_32b_read_ops; /* 32-bit read only */
0083 extern const struct pci_ecam_ops hisi_pcie_ops; /* HiSilicon */
0084 extern const struct pci_ecam_ops thunder_pem_ecam_ops; /* Cavium ThunderX 1.x & 2.x */
0085 extern const struct pci_ecam_ops pci_thunder_ecam_ops; /* Cavium ThunderX 1.x */
0086 extern const struct pci_ecam_ops xgene_v1_pcie_ecam_ops; /* APM X-Gene PCIe v1 */
0087 extern const struct pci_ecam_ops xgene_v2_pcie_ecam_ops; /* APM X-Gene PCIe v2.x */
0088 extern const struct pci_ecam_ops al_pcie_ops;   /* Amazon Annapurna Labs PCIe */
0089 extern const struct pci_ecam_ops tegra194_pcie_ops; /* Tegra194 PCIe */
0090 extern const struct pci_ecam_ops loongson_pci_ecam_ops; /* Loongson PCIe */
0091 #endif
0092
0093 #if IS_ENABLED(CONFIG_PCI_HOST_COMMON)
0094 /* for DT-based PCI controllers that support ECAM */
0095 int pci_host_common_probe(struct platform_device *pdev);
0096 int pci_host_common_remove(struct platform_device *pdev);
0097 #endif
0098 #endif