include/linux/omap-dma.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef __LINUX_OMAP_DMA_H
0003 #define __LINUX_OMAP_DMA_H
0004 /*
0005  *  Legacy OMAP DMA handling defines and functions
0006  *
0007  *  NOTE: Do not use these any longer.
0008  *
0009  *  Use the generic dmaengine functions as defined in
0010  *  include/linux/dmaengine.h.
0011  *
0012  *  Copyright (C) 2003 Nokia Corporation
0013  *  Author: Juha Yrjölä <juha.yrjola@nokia.com>
0014  *
0015  */
0016
0017 #include <linux/platform_device.h>
0018
0019 #define INT_DMA_LCD         (NR_IRQS_LEGACY + 25)
0020
0021 #define OMAP1_DMA_TOUT_IRQ      (1 << 0)
0022 #define OMAP_DMA_DROP_IRQ       (1 << 1)
0023 #define OMAP_DMA_HALF_IRQ       (1 << 2)
0024 #define OMAP_DMA_FRAME_IRQ      (1 << 3)
0025 #define OMAP_DMA_LAST_IRQ       (1 << 4)
0026 #define OMAP_DMA_BLOCK_IRQ      (1 << 5)
0027 #define OMAP1_DMA_SYNC_IRQ      (1 << 6)
0028 #define OMAP2_DMA_PKT_IRQ       (1 << 7)
0029 #define OMAP2_DMA_TRANS_ERR_IRQ     (1 << 8)
0030 #define OMAP2_DMA_SECURE_ERR_IRQ    (1 << 9)
0031 #define OMAP2_DMA_SUPERVISOR_ERR_IRQ    (1 << 10)
0032 #define OMAP2_DMA_MISALIGNED_ERR_IRQ    (1 << 11)
0033
0034 #define OMAP_DMA_CCR_EN         (1 << 7)
0035 #define OMAP_DMA_CCR_RD_ACTIVE      (1 << 9)
0036 #define OMAP_DMA_CCR_WR_ACTIVE      (1 << 10)
0037 #define OMAP_DMA_CCR_SEL_SRC_DST_SYNC   (1 << 24)
0038 #define OMAP_DMA_CCR_BUFFERING_DISABLE  (1 << 25)
0039
0040 #define OMAP_DMA_DATA_TYPE_S8       0x00
0041 #define OMAP_DMA_DATA_TYPE_S16      0x01
0042 #define OMAP_DMA_DATA_TYPE_S32      0x02
0043
0044 #define OMAP_DMA_SYNC_ELEMENT       0x00
0045 #define OMAP_DMA_SYNC_FRAME     0x01
0046 #define OMAP_DMA_SYNC_BLOCK     0x02
0047 #define OMAP_DMA_SYNC_PACKET        0x03
0048
0049 #define OMAP_DMA_DST_SYNC_PREFETCH  0x02
0050 #define OMAP_DMA_SRC_SYNC       0x01
0051 #define OMAP_DMA_DST_SYNC       0x00
0052
0053 #define OMAP_DMA_PORT_EMIFF     0x00
0054 #define OMAP_DMA_PORT_EMIFS     0x01
0055 #define OMAP_DMA_PORT_OCP_T1        0x02
0056 #define OMAP_DMA_PORT_TIPB      0x03
0057 #define OMAP_DMA_PORT_OCP_T2        0x04
0058 #define OMAP_DMA_PORT_MPUI      0x05
0059
0060 #define OMAP_DMA_AMODE_CONSTANT     0x00
0061 #define OMAP_DMA_AMODE_POST_INC     0x01
0062 #define OMAP_DMA_AMODE_SINGLE_IDX   0x02
0063 #define OMAP_DMA_AMODE_DOUBLE_IDX   0x03
0064
0065 #define DMA_DEFAULT_FIFO_DEPTH      0x10
0066 #define DMA_DEFAULT_ARB_RATE        0x01
0067 /* Pass THREAD_RESERVE ORed with THREAD_FIFO for tparams */
0068 #define DMA_THREAD_RESERVE_NORM     (0x00 << 12) /* Def */
0069 #define DMA_THREAD_RESERVE_ONET     (0x01 << 12)
0070 #define DMA_THREAD_RESERVE_TWOT     (0x02 << 12)
0071 #define DMA_THREAD_RESERVE_THREET   (0x03 << 12)
0072 #define DMA_THREAD_FIFO_NONE        (0x00 << 14) /* Def */
0073 #define DMA_THREAD_FIFO_75      (0x01 << 14)
0074 #define DMA_THREAD_FIFO_25      (0x02 << 14)
0075 #define DMA_THREAD_FIFO_50      (0x03 << 14)
0076
0077 /* DMA4_OCP_SYSCONFIG bits */
0078 #define DMA_SYSCONFIG_MIDLEMODE_MASK        (3 << 12)
0079 #define DMA_SYSCONFIG_CLOCKACTIVITY_MASK    (3 << 8)
0080 #define DMA_SYSCONFIG_EMUFREE           (1 << 5)
0081 #define DMA_SYSCONFIG_SIDLEMODE_MASK        (3 << 3)
0082 #define DMA_SYSCONFIG_SOFTRESET         (1 << 2)
0083 #define DMA_SYSCONFIG_AUTOIDLE          (1 << 0)
0084
0085 #define DMA_SYSCONFIG_MIDLEMODE(n)      ((n) << 12)
0086 #define DMA_SYSCONFIG_SIDLEMODE(n)      ((n) << 3)
0087
0088 #define DMA_IDLEMODE_SMARTIDLE          0x2
0089 #define DMA_IDLEMODE_NO_IDLE            0x1
0090 #define DMA_IDLEMODE_FORCE_IDLE         0x0
0091
0092 /* Chaining modes*/
0093 #ifndef CONFIG_ARCH_OMAP1
0094 #define OMAP_DMA_STATIC_CHAIN       0x1
0095 #define OMAP_DMA_DYNAMIC_CHAIN      0x2
0096 #define OMAP_DMA_CHAIN_ACTIVE       0x1
0097 #define OMAP_DMA_CHAIN_INACTIVE     0x0
0098 #endif
0099
0100 #define DMA_CH_PRIO_HIGH        0x1
0101 #define DMA_CH_PRIO_LOW         0x0 /* Def */
0102
0103 /* Errata handling */
0104 #define IS_DMA_ERRATA(id)       (errata & (id))
0105 #define SET_DMA_ERRATA(id)      (errata |= (id))
0106
0107 #define DMA_ERRATA_IFRAME_BUFFERING BIT(0x0)
0108 #define DMA_ERRATA_PARALLEL_CHANNELS    BIT(0x1)
0109 #define DMA_ERRATA_i378         BIT(0x2)
0110 #define DMA_ERRATA_i541         BIT(0x3)
0111 #define DMA_ERRATA_i88          BIT(0x4)
0112 #define DMA_ERRATA_3_3          BIT(0x5)
0113 #define DMA_ROMCODE_BUG         BIT(0x6)
0114
0115 /* Attributes for OMAP DMA Contrller */
0116 #define DMA_LINKED_LCH          BIT(0x0)
0117 #define GLOBAL_PRIORITY         BIT(0x1)
0118 #define RESERVE_CHANNEL         BIT(0x2)
0119 #define IS_CSSA_32          BIT(0x3)
0120 #define IS_CDSA_32          BIT(0x4)
0121 #define IS_RW_PRIORITY          BIT(0x5)
0122 #define ENABLE_1510_MODE        BIT(0x6)
0123 #define SRC_PORT            BIT(0x7)
0124 #define DST_PORT            BIT(0x8)
0125 #define SRC_INDEX           BIT(0x9)
0126 #define DST_INDEX           BIT(0xa)
0127 #define IS_BURST_ONLY4          BIT(0xb)
0128 #define CLEAR_CSR_ON_READ       BIT(0xc)
0129 #define IS_WORD_16          BIT(0xd)
0130 #define ENABLE_16XX_MODE        BIT(0xe)
0131 #define HS_CHANNELS_RESERVED        BIT(0xf)
0132
0133 /* Defines for DMA Capabilities */
0134 #define DMA_HAS_TRANSPARENT_CAPS    (0x1 << 18)
0135 #define DMA_HAS_CONSTANT_FILL_CAPS  (0x1 << 19)
0136 #define DMA_HAS_DESCRIPTOR_CAPS     (0x3 << 20)
0137
0138 enum omap_reg_offsets {
0139
0140 GCR,        GSCR,       GRST1,      HW_ID,
0141 PCH2_ID,    PCH0_ID,    PCH1_ID,    PCHG_ID,
0142 PCHD_ID,    CAPS_0,     CAPS_1,     CAPS_2,
0143 CAPS_3,     CAPS_4,     PCH2_SR,    PCH0_SR,
0144 PCH1_SR,    PCHD_SR,    REVISION,   IRQSTATUS_L0,
0145 IRQSTATUS_L1,   IRQSTATUS_L2,   IRQSTATUS_L3,   IRQENABLE_L0,
0146 IRQENABLE_L1,   IRQENABLE_L2,   IRQENABLE_L3,   SYSSTATUS,
0147 OCP_SYSCONFIG,
0148
0149 /* omap1+ specific */
0150 CPC, CCR2, LCH_CTRL,
0151
0152 /* Common registers for all omap's */
0153 CSDP,       CCR,        CICR,       CSR,
0154 CEN,        CFN,        CSFI,       CSEI,
0155 CSAC,       CDAC,       CDEI,
0156 CDFI,       CLNK_CTRL,
0157
0158 /* Channel specific registers */
0159 CSSA,       CDSA,       COLOR,
0160 CCEN,       CCFN,
0161
0162 /* omap3630 and omap4 specific */
0163 CDP,        CNDP,       CCDN,
0164
0165 };
0166
0167 enum omap_dma_burst_mode {
0168     OMAP_DMA_DATA_BURST_DIS = 0,
0169     OMAP_DMA_DATA_BURST_4,
0170     OMAP_DMA_DATA_BURST_8,
0171     OMAP_DMA_DATA_BURST_16,
0172 };
0173
0174 enum end_type {
0175     OMAP_DMA_LITTLE_ENDIAN = 0,
0176     OMAP_DMA_BIG_ENDIAN
0177 };
0178
0179 enum omap_dma_color_mode {
0180     OMAP_DMA_COLOR_DIS = 0,
0181     OMAP_DMA_CONSTANT_FILL,
0182     OMAP_DMA_TRANSPARENT_COPY
0183 };
0184
0185 enum omap_dma_write_mode {
0186     OMAP_DMA_WRITE_NON_POSTED = 0,
0187     OMAP_DMA_WRITE_POSTED,
0188     OMAP_DMA_WRITE_LAST_NON_POSTED
0189 };
0190
0191 enum omap_dma_channel_mode {
0192     OMAP_DMA_LCH_2D = 0,
0193     OMAP_DMA_LCH_G,
0194     OMAP_DMA_LCH_P,
0195     OMAP_DMA_LCH_PD
0196 };
0197
0198 struct omap_dma_channel_params {
0199     int data_type;      /* data type 8,16,32 */
0200     int elem_count;     /* number of elements in a frame */
0201     int frame_count;    /* number of frames in a element */
0202
0203     int src_port;       /* Only on OMAP1 REVISIT: Is this needed? */
0204     int src_amode;      /* constant, post increment, indexed,
0205                     double indexed */
0206     unsigned long src_start;    /* source address : physical */
0207     int src_ei;     /* source element index */
0208     int src_fi;     /* source frame index */
0209
0210     int dst_port;       /* Only on OMAP1 REVISIT: Is this needed? */
0211     int dst_amode;      /* constant, post increment, indexed,
0212                     double indexed */
0213     unsigned long dst_start;    /* source address : physical */
0214     int dst_ei;     /* source element index */
0215     int dst_fi;     /* source frame index */
0216
0217     int trigger;        /* trigger attached if the channel is
0218                     synchronized */
0219     int sync_mode;      /* sycn on element, frame , block or packet */
0220     int src_or_dst_synch;   /* source synch(1) or destination synch(0) */
0221
0222     int ie;         /* interrupt enabled */
0223
0224     unsigned char read_prio;/* read priority */
0225     unsigned char write_prio;/* write priority */
0226
0227 #ifndef CONFIG_ARCH_OMAP1
0228     enum omap_dma_burst_mode burst_mode; /* Burst mode 4/8/16 words */
0229 #endif
0230 };
0231
0232 struct omap_dma_lch {
0233     int next_lch;
0234     int dev_id;
0235     u16 saved_csr;
0236     u16 enabled_irqs;
0237     const char *dev_name;
0238     void (*callback)(int lch, u16 ch_status, void *data);
0239     void *data;
0240     long flags;
0241     int state;
0242     int chain_id;
0243     int status;
0244 };
0245
0246 struct omap_dma_dev_attr {
0247     u32 dev_caps;
0248     u16 lch_count;
0249     u16 chan_count;
0250 };
0251
0252 enum {
0253     OMAP_DMA_REG_NONE,
0254     OMAP_DMA_REG_16BIT,
0255     OMAP_DMA_REG_2X16BIT,
0256     OMAP_DMA_REG_32BIT,
0257 };
0258
0259 struct omap_dma_reg {
0260     u16 offset;
0261     u8  stride;
0262     u8  type;
0263 };
0264
0265 #define SDMA_FILTER_PARAM(hw_req)   ((int[]) { (hw_req) })
0266 struct dma_slave_map;
0267
0268 /* System DMA platform data structure */
0269 struct omap_system_dma_plat_info {
0270     const struct omap_dma_reg *reg_map;
0271     unsigned channel_stride;
0272     struct omap_dma_dev_attr *dma_attr;
0273     u32 errata;
0274     void (*show_dma_caps)(void);
0275     void (*clear_lch_regs)(int lch);
0276     void (*clear_dma)(int lch);
0277     void (*dma_write)(u32 val, int reg, int lch);
0278     u32 (*dma_read)(int reg, int lch);
0279
0280     const struct dma_slave_map *slave_map;
0281     int slavecnt;
0282 };
0283
0284 #ifdef CONFIG_ARCH_OMAP2PLUS
0285 #define dma_omap2plus() 1
0286 #else
0287 #define dma_omap2plus() 0
0288 #endif
0289 #define dma_omap1() (!dma_omap2plus())
0290 #define __dma_omap15xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_1510_MODE)
0291 #define __dma_omap16xx(d) (dma_omap1() && (d)->dev_caps & ENABLE_16XX_MODE)
0292 #define dma_omap15xx()  __dma_omap15xx(d)
0293 #define dma_omap16xx()  __dma_omap16xx(d)
0294
0295 extern struct omap_system_dma_plat_info *omap_get_plat_info(void);
0296
0297 #if defined(CONFIG_ARCH_OMAP1)
0298 extern void omap_set_dma_priority(int lch, int dst_port, int priority);
0299 #else
0300 static inline void omap_set_dma_priority(int lch, int dst_port, int priority)
0301 {
0302 }
0303 #endif
0304
0305 extern int omap_request_dma(int dev_id, const char *dev_name,
0306             void (*callback)(int lch, u16 ch_status, void *data),
0307             void *data, int *dma_ch);
0308 extern void omap_free_dma(int ch);
0309 #if IS_ENABLED(CONFIG_USB_OMAP)
0310 extern void omap_disable_dma_irq(int ch, u16 irq_bits);
0311 extern void omap_start_dma(int lch);
0312 extern void omap_stop_dma(int lch);
0313 extern void omap_set_dma_transfer_params(int lch, int data_type,
0314                      int elem_count, int frame_count,
0315                      int sync_mode,
0316                      int dma_trigger, int src_or_dst_synch);
0317 extern void omap_set_dma_channel_mode(int lch, enum omap_dma_channel_mode mode);
0318
0319 extern void omap_set_dma_src_params(int lch, int src_port, int src_amode,
0320                     unsigned long src_start,
0321                     int src_ei, int src_fi);
0322 extern void omap_set_dma_src_data_pack(int lch, int enable);
0323 extern void omap_set_dma_src_burst_mode(int lch,
0324                     enum omap_dma_burst_mode burst_mode);
0325
0326 extern void omap_set_dma_dest_params(int lch, int dest_port, int dest_amode,
0327                      unsigned long dest_start,
0328                      int dst_ei, int dst_fi);
0329 extern void omap_set_dma_dest_data_pack(int lch, int enable);
0330 extern void omap_set_dma_dest_burst_mode(int lch,
0331                      enum omap_dma_burst_mode burst_mode);
0332
0333 extern dma_addr_t omap_get_dma_src_pos(int lch);
0334 extern dma_addr_t omap_get_dma_dst_pos(int lch);
0335 extern int omap_get_dma_active_status(int lch);
0336 #endif
0337
0338 extern int omap_dma_running(void);
0339
0340 #if IS_ENABLED(CONFIG_FB_OMAP)
0341 extern int omap_lcd_dma_running(void);
0342 #else
0343 static inline int omap_lcd_dma_running(void)
0344 {
0345     return 0;
0346 }
0347 #endif
0348
0349 #endif /* __LINUX_OMAP_DMA_H */