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0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Definitions for the NVM Express interface
0004  * Copyright (c) 2011-2014, Intel Corporation.
0005  */
0006 
0007 #ifndef _LINUX_NVME_H
0008 #define _LINUX_NVME_H
0009 
0010 #include <linux/types.h>
0011 #include <linux/uuid.h>
0012 
0013 /* NQN names in commands fields specified one size */
0014 #define NVMF_NQN_FIELD_LEN  256
0015 
0016 /* However the max length of a qualified name is another size */
0017 #define NVMF_NQN_SIZE       223
0018 
0019 #define NVMF_TRSVCID_SIZE   32
0020 #define NVMF_TRADDR_SIZE    256
0021 #define NVMF_TSAS_SIZE      256
0022 #define NVMF_AUTH_HASH_LEN  64
0023 
0024 #define NVME_DISC_SUBSYS_NAME   "nqn.2014-08.org.nvmexpress.discovery"
0025 
0026 #define NVME_RDMA_IP_PORT   4420
0027 
0028 #define NVME_NSID_ALL       0xffffffff
0029 
0030 enum nvme_subsys_type {
0031     /* Referral to another discovery type target subsystem */
0032     NVME_NQN_DISC   = 1,
0033 
0034     /* NVME type target subsystem */
0035     NVME_NQN_NVME   = 2,
0036 
0037     /* Current discovery type target subsystem */
0038     NVME_NQN_CURR   = 3,
0039 };
0040 
0041 enum nvme_ctrl_type {
0042     NVME_CTRL_IO    = 1,        /* I/O controller */
0043     NVME_CTRL_DISC  = 2,        /* Discovery controller */
0044     NVME_CTRL_ADMIN = 3,        /* Administrative controller */
0045 };
0046 
0047 enum nvme_dctype {
0048     NVME_DCTYPE_NOT_REPORTED    = 0,
0049     NVME_DCTYPE_DDC         = 1, /* Direct Discovery Controller */
0050     NVME_DCTYPE_CDC         = 2, /* Central Discovery Controller */
0051 };
0052 
0053 /* Address Family codes for Discovery Log Page entry ADRFAM field */
0054 enum {
0055     NVMF_ADDR_FAMILY_PCI    = 0,    /* PCIe */
0056     NVMF_ADDR_FAMILY_IP4    = 1,    /* IP4 */
0057     NVMF_ADDR_FAMILY_IP6    = 2,    /* IP6 */
0058     NVMF_ADDR_FAMILY_IB = 3,    /* InfiniBand */
0059     NVMF_ADDR_FAMILY_FC = 4,    /* Fibre Channel */
0060     NVMF_ADDR_FAMILY_LOOP   = 254,  /* Reserved for host usage */
0061     NVMF_ADDR_FAMILY_MAX,
0062 };
0063 
0064 /* Transport Type codes for Discovery Log Page entry TRTYPE field */
0065 enum {
0066     NVMF_TRTYPE_RDMA    = 1,    /* RDMA */
0067     NVMF_TRTYPE_FC      = 2,    /* Fibre Channel */
0068     NVMF_TRTYPE_TCP     = 3,    /* TCP/IP */
0069     NVMF_TRTYPE_LOOP    = 254,  /* Reserved for host usage */
0070     NVMF_TRTYPE_MAX,
0071 };
0072 
0073 /* Transport Requirements codes for Discovery Log Page entry TREQ field */
0074 enum {
0075     NVMF_TREQ_NOT_SPECIFIED = 0,        /* Not specified */
0076     NVMF_TREQ_REQUIRED  = 1,        /* Required */
0077     NVMF_TREQ_NOT_REQUIRED  = 2,        /* Not Required */
0078 #define NVME_TREQ_SECURE_CHANNEL_MASK \
0079     (NVMF_TREQ_REQUIRED | NVMF_TREQ_NOT_REQUIRED)
0080 
0081     NVMF_TREQ_DISABLE_SQFLOW = (1 << 2),    /* Supports SQ flow control disable */
0082 };
0083 
0084 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
0085  * RDMA_QPTYPE field
0086  */
0087 enum {
0088     NVMF_RDMA_QPTYPE_CONNECTED  = 1, /* Reliable Connected */
0089     NVMF_RDMA_QPTYPE_DATAGRAM   = 2, /* Reliable Datagram */
0090 };
0091 
0092 /* RDMA QP Service Type codes for Discovery Log Page entry TSAS
0093  * RDMA_QPTYPE field
0094  */
0095 enum {
0096     NVMF_RDMA_PRTYPE_NOT_SPECIFIED  = 1, /* No Provider Specified */
0097     NVMF_RDMA_PRTYPE_IB     = 2, /* InfiniBand */
0098     NVMF_RDMA_PRTYPE_ROCE       = 3, /* InfiniBand RoCE */
0099     NVMF_RDMA_PRTYPE_ROCEV2     = 4, /* InfiniBand RoCEV2 */
0100     NVMF_RDMA_PRTYPE_IWARP      = 5, /* IWARP */
0101 };
0102 
0103 /* RDMA Connection Management Service Type codes for Discovery Log Page
0104  * entry TSAS RDMA_CMS field
0105  */
0106 enum {
0107     NVMF_RDMA_CMS_RDMA_CM   = 1, /* Sockets based endpoint addressing */
0108 };
0109 
0110 #define NVME_AQ_DEPTH       32
0111 #define NVME_NR_AEN_COMMANDS    1
0112 #define NVME_AQ_BLK_MQ_DEPTH    (NVME_AQ_DEPTH - NVME_NR_AEN_COMMANDS)
0113 
0114 /*
0115  * Subtract one to leave an empty queue entry for 'Full Queue' condition. See
0116  * NVM-Express 1.2 specification, section 4.1.2.
0117  */
0118 #define NVME_AQ_MQ_TAG_DEPTH    (NVME_AQ_BLK_MQ_DEPTH - 1)
0119 
0120 enum {
0121     NVME_REG_CAP    = 0x0000,   /* Controller Capabilities */
0122     NVME_REG_VS = 0x0008,   /* Version */
0123     NVME_REG_INTMS  = 0x000c,   /* Interrupt Mask Set */
0124     NVME_REG_INTMC  = 0x0010,   /* Interrupt Mask Clear */
0125     NVME_REG_CC = 0x0014,   /* Controller Configuration */
0126     NVME_REG_CSTS   = 0x001c,   /* Controller Status */
0127     NVME_REG_NSSR   = 0x0020,   /* NVM Subsystem Reset */
0128     NVME_REG_AQA    = 0x0024,   /* Admin Queue Attributes */
0129     NVME_REG_ASQ    = 0x0028,   /* Admin SQ Base Address */
0130     NVME_REG_ACQ    = 0x0030,   /* Admin CQ Base Address */
0131     NVME_REG_CMBLOC = 0x0038,   /* Controller Memory Buffer Location */
0132     NVME_REG_CMBSZ  = 0x003c,   /* Controller Memory Buffer Size */
0133     NVME_REG_BPINFO = 0x0040,   /* Boot Partition Information */
0134     NVME_REG_BPRSEL = 0x0044,   /* Boot Partition Read Select */
0135     NVME_REG_BPMBL  = 0x0048,   /* Boot Partition Memory Buffer
0136                      * Location
0137                      */
0138     NVME_REG_CMBMSC = 0x0050,   /* Controller Memory Buffer Memory
0139                      * Space Control
0140                      */
0141     NVME_REG_CRTO   = 0x0068,   /* Controller Ready Timeouts */
0142     NVME_REG_PMRCAP = 0x0e00,   /* Persistent Memory Capabilities */
0143     NVME_REG_PMRCTL = 0x0e04,   /* Persistent Memory Region Control */
0144     NVME_REG_PMRSTS = 0x0e08,   /* Persistent Memory Region Status */
0145     NVME_REG_PMREBS = 0x0e0c,   /* Persistent Memory Region Elasticity
0146                      * Buffer Size
0147                      */
0148     NVME_REG_PMRSWTP = 0x0e10,  /* Persistent Memory Region Sustained
0149                      * Write Throughput
0150                      */
0151     NVME_REG_DBS    = 0x1000,   /* SQ 0 Tail Doorbell */
0152 };
0153 
0154 #define NVME_CAP_MQES(cap)  ((cap) & 0xffff)
0155 #define NVME_CAP_TIMEOUT(cap)   (((cap) >> 24) & 0xff)
0156 #define NVME_CAP_STRIDE(cap)    (((cap) >> 32) & 0xf)
0157 #define NVME_CAP_NSSRC(cap) (((cap) >> 36) & 0x1)
0158 #define NVME_CAP_CSS(cap)   (((cap) >> 37) & 0xff)
0159 #define NVME_CAP_MPSMIN(cap)    (((cap) >> 48) & 0xf)
0160 #define NVME_CAP_MPSMAX(cap)    (((cap) >> 52) & 0xf)
0161 #define NVME_CAP_CMBS(cap)  (((cap) >> 57) & 0x1)
0162 
0163 #define NVME_CMB_BIR(cmbloc)    ((cmbloc) & 0x7)
0164 #define NVME_CMB_OFST(cmbloc)   (((cmbloc) >> 12) & 0xfffff)
0165 
0166 #define NVME_CRTO_CRIMT(crto)   ((crto) >> 16)
0167 #define NVME_CRTO_CRWMT(crto)   ((crto) & 0xffff)
0168 
0169 enum {
0170     NVME_CMBSZ_SQS      = 1 << 0,
0171     NVME_CMBSZ_CQS      = 1 << 1,
0172     NVME_CMBSZ_LISTS    = 1 << 2,
0173     NVME_CMBSZ_RDS      = 1 << 3,
0174     NVME_CMBSZ_WDS      = 1 << 4,
0175 
0176     NVME_CMBSZ_SZ_SHIFT = 12,
0177     NVME_CMBSZ_SZ_MASK  = 0xfffff,
0178 
0179     NVME_CMBSZ_SZU_SHIFT    = 8,
0180     NVME_CMBSZ_SZU_MASK = 0xf,
0181 };
0182 
0183 /*
0184  * Submission and Completion Queue Entry Sizes for the NVM command set.
0185  * (In bytes and specified as a power of two (2^n)).
0186  */
0187 #define NVME_ADM_SQES       6
0188 #define NVME_NVM_IOSQES     6
0189 #define NVME_NVM_IOCQES     4
0190 
0191 enum {
0192     NVME_CC_ENABLE      = 1 << 0,
0193     NVME_CC_EN_SHIFT    = 0,
0194     NVME_CC_CSS_SHIFT   = 4,
0195     NVME_CC_MPS_SHIFT   = 7,
0196     NVME_CC_AMS_SHIFT   = 11,
0197     NVME_CC_SHN_SHIFT   = 14,
0198     NVME_CC_IOSQES_SHIFT    = 16,
0199     NVME_CC_IOCQES_SHIFT    = 20,
0200     NVME_CC_CSS_NVM     = 0 << NVME_CC_CSS_SHIFT,
0201     NVME_CC_CSS_CSI     = 6 << NVME_CC_CSS_SHIFT,
0202     NVME_CC_CSS_MASK    = 7 << NVME_CC_CSS_SHIFT,
0203     NVME_CC_AMS_RR      = 0 << NVME_CC_AMS_SHIFT,
0204     NVME_CC_AMS_WRRU    = 1 << NVME_CC_AMS_SHIFT,
0205     NVME_CC_AMS_VS      = 7 << NVME_CC_AMS_SHIFT,
0206     NVME_CC_SHN_NONE    = 0 << NVME_CC_SHN_SHIFT,
0207     NVME_CC_SHN_NORMAL  = 1 << NVME_CC_SHN_SHIFT,
0208     NVME_CC_SHN_ABRUPT  = 2 << NVME_CC_SHN_SHIFT,
0209     NVME_CC_SHN_MASK    = 3 << NVME_CC_SHN_SHIFT,
0210     NVME_CC_IOSQES      = NVME_NVM_IOSQES << NVME_CC_IOSQES_SHIFT,
0211     NVME_CC_IOCQES      = NVME_NVM_IOCQES << NVME_CC_IOCQES_SHIFT,
0212     NVME_CC_CRIME       = 1 << 24,
0213 };
0214 
0215 enum {
0216     NVME_CSTS_RDY       = 1 << 0,
0217     NVME_CSTS_CFS       = 1 << 1,
0218     NVME_CSTS_NSSRO     = 1 << 4,
0219     NVME_CSTS_PP        = 1 << 5,
0220     NVME_CSTS_SHST_NORMAL   = 0 << 2,
0221     NVME_CSTS_SHST_OCCUR    = 1 << 2,
0222     NVME_CSTS_SHST_CMPLT    = 2 << 2,
0223     NVME_CSTS_SHST_MASK = 3 << 2,
0224 };
0225 
0226 enum {
0227     NVME_CMBMSC_CRE     = 1 << 0,
0228     NVME_CMBMSC_CMSE    = 1 << 1,
0229 };
0230 
0231 enum {
0232     NVME_CAP_CSS_NVM    = 1 << 0,
0233     NVME_CAP_CSS_CSI    = 1 << 6,
0234 };
0235 
0236 enum {
0237     NVME_CAP_CRMS_CRWMS = 1ULL << 59,
0238     NVME_CAP_CRMS_CRIMS = 1ULL << 60,
0239 };
0240 
0241 struct nvme_id_power_state {
0242     __le16          max_power;  /* centiwatts */
0243     __u8            rsvd2;
0244     __u8            flags;
0245     __le32          entry_lat;  /* microseconds */
0246     __le32          exit_lat;   /* microseconds */
0247     __u8            read_tput;
0248     __u8            read_lat;
0249     __u8            write_tput;
0250     __u8            write_lat;
0251     __le16          idle_power;
0252     __u8            idle_scale;
0253     __u8            rsvd19;
0254     __le16          active_power;
0255     __u8            active_work_scale;
0256     __u8            rsvd23[9];
0257 };
0258 
0259 enum {
0260     NVME_PS_FLAGS_MAX_POWER_SCALE   = 1 << 0,
0261     NVME_PS_FLAGS_NON_OP_STATE  = 1 << 1,
0262 };
0263 
0264 enum nvme_ctrl_attr {
0265     NVME_CTRL_ATTR_HID_128_BIT  = (1 << 0),
0266     NVME_CTRL_ATTR_TBKAS        = (1 << 6),
0267     NVME_CTRL_ATTR_ELBAS        = (1 << 15),
0268 };
0269 
0270 struct nvme_id_ctrl {
0271     __le16          vid;
0272     __le16          ssvid;
0273     char            sn[20];
0274     char            mn[40];
0275     char            fr[8];
0276     __u8            rab;
0277     __u8            ieee[3];
0278     __u8            cmic;
0279     __u8            mdts;
0280     __le16          cntlid;
0281     __le32          ver;
0282     __le32          rtd3r;
0283     __le32          rtd3e;
0284     __le32          oaes;
0285     __le32          ctratt;
0286     __u8            rsvd100[11];
0287     __u8            cntrltype;
0288     __u8            fguid[16];
0289     __le16          crdt1;
0290     __le16          crdt2;
0291     __le16          crdt3;
0292     __u8            rsvd134[122];
0293     __le16          oacs;
0294     __u8            acl;
0295     __u8            aerl;
0296     __u8            frmw;
0297     __u8            lpa;
0298     __u8            elpe;
0299     __u8            npss;
0300     __u8            avscc;
0301     __u8            apsta;
0302     __le16          wctemp;
0303     __le16          cctemp;
0304     __le16          mtfa;
0305     __le32          hmpre;
0306     __le32          hmmin;
0307     __u8            tnvmcap[16];
0308     __u8            unvmcap[16];
0309     __le32          rpmbs;
0310     __le16          edstt;
0311     __u8            dsto;
0312     __u8            fwug;
0313     __le16          kas;
0314     __le16          hctma;
0315     __le16          mntmt;
0316     __le16          mxtmt;
0317     __le32          sanicap;
0318     __le32          hmminds;
0319     __le16          hmmaxd;
0320     __u8            rsvd338[4];
0321     __u8            anatt;
0322     __u8            anacap;
0323     __le32          anagrpmax;
0324     __le32          nanagrpid;
0325     __u8            rsvd352[160];
0326     __u8            sqes;
0327     __u8            cqes;
0328     __le16          maxcmd;
0329     __le32          nn;
0330     __le16          oncs;
0331     __le16          fuses;
0332     __u8            fna;
0333     __u8            vwc;
0334     __le16          awun;
0335     __le16          awupf;
0336     __u8            nvscc;
0337     __u8            nwpc;
0338     __le16          acwu;
0339     __u8            rsvd534[2];
0340     __le32          sgls;
0341     __le32          mnan;
0342     __u8            rsvd544[224];
0343     char            subnqn[256];
0344     __u8            rsvd1024[768];
0345     __le32          ioccsz;
0346     __le32          iorcsz;
0347     __le16          icdoff;
0348     __u8            ctrattr;
0349     __u8            msdbd;
0350     __u8            rsvd1804[2];
0351     __u8            dctype;
0352     __u8            rsvd1807[241];
0353     struct nvme_id_power_state  psd[32];
0354     __u8            vs[1024];
0355 };
0356 
0357 enum {
0358     NVME_CTRL_CMIC_MULTI_PORT       = 1 << 0,
0359     NVME_CTRL_CMIC_MULTI_CTRL       = 1 << 1,
0360     NVME_CTRL_CMIC_ANA          = 1 << 3,
0361     NVME_CTRL_ONCS_COMPARE          = 1 << 0,
0362     NVME_CTRL_ONCS_WRITE_UNCORRECTABLE  = 1 << 1,
0363     NVME_CTRL_ONCS_DSM          = 1 << 2,
0364     NVME_CTRL_ONCS_WRITE_ZEROES     = 1 << 3,
0365     NVME_CTRL_ONCS_RESERVATIONS     = 1 << 5,
0366     NVME_CTRL_ONCS_TIMESTAMP        = 1 << 6,
0367     NVME_CTRL_VWC_PRESENT           = 1 << 0,
0368     NVME_CTRL_OACS_SEC_SUPP                 = 1 << 0,
0369     NVME_CTRL_OACS_NS_MNGT_SUPP     = 1 << 3,
0370     NVME_CTRL_OACS_DIRECTIVES       = 1 << 5,
0371     NVME_CTRL_OACS_DBBUF_SUPP       = 1 << 8,
0372     NVME_CTRL_LPA_CMD_EFFECTS_LOG       = 1 << 1,
0373     NVME_CTRL_CTRATT_128_ID         = 1 << 0,
0374     NVME_CTRL_CTRATT_NON_OP_PSP     = 1 << 1,
0375     NVME_CTRL_CTRATT_NVM_SETS       = 1 << 2,
0376     NVME_CTRL_CTRATT_READ_RECV_LVLS     = 1 << 3,
0377     NVME_CTRL_CTRATT_ENDURANCE_GROUPS   = 1 << 4,
0378     NVME_CTRL_CTRATT_PREDICTABLE_LAT    = 1 << 5,
0379     NVME_CTRL_CTRATT_NAMESPACE_GRANULARITY  = 1 << 7,
0380     NVME_CTRL_CTRATT_UUID_LIST      = 1 << 9,
0381 };
0382 
0383 struct nvme_lbaf {
0384     __le16          ms;
0385     __u8            ds;
0386     __u8            rp;
0387 };
0388 
0389 struct nvme_id_ns {
0390     __le64          nsze;
0391     __le64          ncap;
0392     __le64          nuse;
0393     __u8            nsfeat;
0394     __u8            nlbaf;
0395     __u8            flbas;
0396     __u8            mc;
0397     __u8            dpc;
0398     __u8            dps;
0399     __u8            nmic;
0400     __u8            rescap;
0401     __u8            fpi;
0402     __u8            dlfeat;
0403     __le16          nawun;
0404     __le16          nawupf;
0405     __le16          nacwu;
0406     __le16          nabsn;
0407     __le16          nabo;
0408     __le16          nabspf;
0409     __le16          noiob;
0410     __u8            nvmcap[16];
0411     __le16          npwg;
0412     __le16          npwa;
0413     __le16          npdg;
0414     __le16          npda;
0415     __le16          nows;
0416     __u8            rsvd74[18];
0417     __le32          anagrpid;
0418     __u8            rsvd96[3];
0419     __u8            nsattr;
0420     __le16          nvmsetid;
0421     __le16          endgid;
0422     __u8            nguid[16];
0423     __u8            eui64[8];
0424     struct nvme_lbaf    lbaf[64];
0425     __u8            vs[3712];
0426 };
0427 
0428 /* I/O Command Set Independent Identify Namespace Data Structure */
0429 struct nvme_id_ns_cs_indep {
0430     __u8            nsfeat;
0431     __u8            nmic;
0432     __u8            rescap;
0433     __u8            fpi;
0434     __le32          anagrpid;
0435     __u8            nsattr;
0436     __u8            rsvd9;
0437     __le16          nvmsetid;
0438     __le16          endgid;
0439     __u8            nstat;
0440     __u8            rsvd15[4081];
0441 };
0442 
0443 struct nvme_zns_lbafe {
0444     __le64          zsze;
0445     __u8            zdes;
0446     __u8            rsvd9[7];
0447 };
0448 
0449 struct nvme_id_ns_zns {
0450     __le16          zoc;
0451     __le16          ozcs;
0452     __le32          mar;
0453     __le32          mor;
0454     __le32          rrl;
0455     __le32          frl;
0456     __u8            rsvd20[2796];
0457     struct nvme_zns_lbafe   lbafe[64];
0458     __u8            vs[256];
0459 };
0460 
0461 struct nvme_id_ctrl_zns {
0462     __u8    zasl;
0463     __u8    rsvd1[4095];
0464 };
0465 
0466 struct nvme_id_ns_nvm {
0467     __le64  lbstm;
0468     __u8    pic;
0469     __u8    rsvd9[3];
0470     __le32  elbaf[64];
0471     __u8    rsvd268[3828];
0472 };
0473 
0474 enum {
0475     NVME_ID_NS_NVM_STS_MASK     = 0x3f,
0476     NVME_ID_NS_NVM_GUARD_SHIFT  = 7,
0477     NVME_ID_NS_NVM_GUARD_MASK   = 0x3,
0478 };
0479 
0480 static inline __u8 nvme_elbaf_sts(__u32 elbaf)
0481 {
0482     return elbaf & NVME_ID_NS_NVM_STS_MASK;
0483 }
0484 
0485 static inline __u8 nvme_elbaf_guard_type(__u32 elbaf)
0486 {
0487     return (elbaf >> NVME_ID_NS_NVM_GUARD_SHIFT) & NVME_ID_NS_NVM_GUARD_MASK;
0488 }
0489 
0490 struct nvme_id_ctrl_nvm {
0491     __u8    vsl;
0492     __u8    wzsl;
0493     __u8    wusl;
0494     __u8    dmrl;
0495     __le32  dmrsl;
0496     __le64  dmsl;
0497     __u8    rsvd16[4080];
0498 };
0499 
0500 enum {
0501     NVME_ID_CNS_NS          = 0x00,
0502     NVME_ID_CNS_CTRL        = 0x01,
0503     NVME_ID_CNS_NS_ACTIVE_LIST  = 0x02,
0504     NVME_ID_CNS_NS_DESC_LIST    = 0x03,
0505     NVME_ID_CNS_CS_NS       = 0x05,
0506     NVME_ID_CNS_CS_CTRL     = 0x06,
0507     NVME_ID_CNS_NS_CS_INDEP     = 0x08,
0508     NVME_ID_CNS_NS_PRESENT_LIST = 0x10,
0509     NVME_ID_CNS_NS_PRESENT      = 0x11,
0510     NVME_ID_CNS_CTRL_NS_LIST    = 0x12,
0511     NVME_ID_CNS_CTRL_LIST       = 0x13,
0512     NVME_ID_CNS_SCNDRY_CTRL_LIST    = 0x15,
0513     NVME_ID_CNS_NS_GRANULARITY  = 0x16,
0514     NVME_ID_CNS_UUID_LIST       = 0x17,
0515 };
0516 
0517 enum {
0518     NVME_CSI_NVM            = 0,
0519     NVME_CSI_ZNS            = 2,
0520 };
0521 
0522 enum {
0523     NVME_DIR_IDENTIFY       = 0x00,
0524     NVME_DIR_STREAMS        = 0x01,
0525     NVME_DIR_SND_ID_OP_ENABLE   = 0x01,
0526     NVME_DIR_SND_ST_OP_REL_ID   = 0x01,
0527     NVME_DIR_SND_ST_OP_REL_RSC  = 0x02,
0528     NVME_DIR_RCV_ID_OP_PARAM    = 0x01,
0529     NVME_DIR_RCV_ST_OP_PARAM    = 0x01,
0530     NVME_DIR_RCV_ST_OP_STATUS   = 0x02,
0531     NVME_DIR_RCV_ST_OP_RESOURCE = 0x03,
0532     NVME_DIR_ENDIR          = 0x01,
0533 };
0534 
0535 enum {
0536     NVME_NS_FEAT_THIN   = 1 << 0,
0537     NVME_NS_FEAT_ATOMICS    = 1 << 1,
0538     NVME_NS_FEAT_IO_OPT = 1 << 4,
0539     NVME_NS_ATTR_RO     = 1 << 0,
0540     NVME_NS_FLBAS_LBA_MASK  = 0xf,
0541     NVME_NS_FLBAS_LBA_UMASK = 0x60,
0542     NVME_NS_FLBAS_LBA_SHIFT = 1,
0543     NVME_NS_FLBAS_META_EXT  = 0x10,
0544     NVME_NS_NMIC_SHARED = 1 << 0,
0545     NVME_LBAF_RP_BEST   = 0,
0546     NVME_LBAF_RP_BETTER = 1,
0547     NVME_LBAF_RP_GOOD   = 2,
0548     NVME_LBAF_RP_DEGRADED   = 3,
0549     NVME_NS_DPC_PI_LAST = 1 << 4,
0550     NVME_NS_DPC_PI_FIRST    = 1 << 3,
0551     NVME_NS_DPC_PI_TYPE3    = 1 << 2,
0552     NVME_NS_DPC_PI_TYPE2    = 1 << 1,
0553     NVME_NS_DPC_PI_TYPE1    = 1 << 0,
0554     NVME_NS_DPS_PI_FIRST    = 1 << 3,
0555     NVME_NS_DPS_PI_MASK = 0x7,
0556     NVME_NS_DPS_PI_TYPE1    = 1,
0557     NVME_NS_DPS_PI_TYPE2    = 2,
0558     NVME_NS_DPS_PI_TYPE3    = 3,
0559 };
0560 
0561 enum {
0562     NVME_NSTAT_NRDY     = 1 << 0,
0563 };
0564 
0565 enum {
0566     NVME_NVM_NS_16B_GUARD   = 0,
0567     NVME_NVM_NS_32B_GUARD   = 1,
0568     NVME_NVM_NS_64B_GUARD   = 2,
0569 };
0570 
0571 static inline __u8 nvme_lbaf_index(__u8 flbas)
0572 {
0573     return (flbas & NVME_NS_FLBAS_LBA_MASK) |
0574         ((flbas & NVME_NS_FLBAS_LBA_UMASK) >> NVME_NS_FLBAS_LBA_SHIFT);
0575 }
0576 
0577 /* Identify Namespace Metadata Capabilities (MC): */
0578 enum {
0579     NVME_MC_EXTENDED_LBA    = (1 << 0),
0580     NVME_MC_METADATA_PTR    = (1 << 1),
0581 };
0582 
0583 struct nvme_ns_id_desc {
0584     __u8 nidt;
0585     __u8 nidl;
0586     __le16 reserved;
0587 };
0588 
0589 #define NVME_NIDT_EUI64_LEN 8
0590 #define NVME_NIDT_NGUID_LEN 16
0591 #define NVME_NIDT_UUID_LEN  16
0592 #define NVME_NIDT_CSI_LEN   1
0593 
0594 enum {
0595     NVME_NIDT_EUI64     = 0x01,
0596     NVME_NIDT_NGUID     = 0x02,
0597     NVME_NIDT_UUID      = 0x03,
0598     NVME_NIDT_CSI       = 0x04,
0599 };
0600 
0601 struct nvme_smart_log {
0602     __u8            critical_warning;
0603     __u8            temperature[2];
0604     __u8            avail_spare;
0605     __u8            spare_thresh;
0606     __u8            percent_used;
0607     __u8            endu_grp_crit_warn_sumry;
0608     __u8            rsvd7[25];
0609     __u8            data_units_read[16];
0610     __u8            data_units_written[16];
0611     __u8            host_reads[16];
0612     __u8            host_writes[16];
0613     __u8            ctrl_busy_time[16];
0614     __u8            power_cycles[16];
0615     __u8            power_on_hours[16];
0616     __u8            unsafe_shutdowns[16];
0617     __u8            media_errors[16];
0618     __u8            num_err_log_entries[16];
0619     __le32          warning_temp_time;
0620     __le32          critical_comp_time;
0621     __le16          temp_sensor[8];
0622     __le32          thm_temp1_trans_count;
0623     __le32          thm_temp2_trans_count;
0624     __le32          thm_temp1_total_time;
0625     __le32          thm_temp2_total_time;
0626     __u8            rsvd232[280];
0627 };
0628 
0629 struct nvme_fw_slot_info_log {
0630     __u8            afi;
0631     __u8            rsvd1[7];
0632     __le64          frs[7];
0633     __u8            rsvd64[448];
0634 };
0635 
0636 enum {
0637     NVME_CMD_EFFECTS_CSUPP      = 1 << 0,
0638     NVME_CMD_EFFECTS_LBCC       = 1 << 1,
0639     NVME_CMD_EFFECTS_NCC        = 1 << 2,
0640     NVME_CMD_EFFECTS_NIC        = 1 << 3,
0641     NVME_CMD_EFFECTS_CCC        = 1 << 4,
0642     NVME_CMD_EFFECTS_CSE_MASK   = 3 << 16,
0643     NVME_CMD_EFFECTS_UUID_SEL   = 1 << 19,
0644 };
0645 
0646 struct nvme_effects_log {
0647     __le32 acs[256];
0648     __le32 iocs[256];
0649     __u8   resv[2048];
0650 };
0651 
0652 enum nvme_ana_state {
0653     NVME_ANA_OPTIMIZED      = 0x01,
0654     NVME_ANA_NONOPTIMIZED       = 0x02,
0655     NVME_ANA_INACCESSIBLE       = 0x03,
0656     NVME_ANA_PERSISTENT_LOSS    = 0x04,
0657     NVME_ANA_CHANGE         = 0x0f,
0658 };
0659 
0660 struct nvme_ana_group_desc {
0661     __le32  grpid;
0662     __le32  nnsids;
0663     __le64  chgcnt;
0664     __u8    state;
0665     __u8    rsvd17[15];
0666     __le32  nsids[];
0667 };
0668 
0669 /* flag for the log specific field of the ANA log */
0670 #define NVME_ANA_LOG_RGO    (1 << 0)
0671 
0672 struct nvme_ana_rsp_hdr {
0673     __le64  chgcnt;
0674     __le16  ngrps;
0675     __le16  rsvd10[3];
0676 };
0677 
0678 struct nvme_zone_descriptor {
0679     __u8        zt;
0680     __u8        zs;
0681     __u8        za;
0682     __u8        rsvd3[5];
0683     __le64      zcap;
0684     __le64      zslba;
0685     __le64      wp;
0686     __u8        rsvd32[32];
0687 };
0688 
0689 enum {
0690     NVME_ZONE_TYPE_SEQWRITE_REQ = 0x2,
0691 };
0692 
0693 struct nvme_zone_report {
0694     __le64      nr_zones;
0695     __u8        resv8[56];
0696     struct nvme_zone_descriptor entries[];
0697 };
0698 
0699 enum {
0700     NVME_SMART_CRIT_SPARE       = 1 << 0,
0701     NVME_SMART_CRIT_TEMPERATURE = 1 << 1,
0702     NVME_SMART_CRIT_RELIABILITY = 1 << 2,
0703     NVME_SMART_CRIT_MEDIA       = 1 << 3,
0704     NVME_SMART_CRIT_VOLATILE_MEMORY = 1 << 4,
0705 };
0706 
0707 enum {
0708     NVME_AER_ERROR          = 0,
0709     NVME_AER_SMART          = 1,
0710     NVME_AER_NOTICE         = 2,
0711     NVME_AER_CSS            = 6,
0712     NVME_AER_VS         = 7,
0713 };
0714 
0715 enum {
0716     NVME_AER_ERROR_PERSIST_INT_ERR  = 0x03,
0717 };
0718 
0719 enum {
0720     NVME_AER_NOTICE_NS_CHANGED  = 0x00,
0721     NVME_AER_NOTICE_FW_ACT_STARTING = 0x01,
0722     NVME_AER_NOTICE_ANA     = 0x03,
0723     NVME_AER_NOTICE_DISC_CHANGED    = 0xf0,
0724 };
0725 
0726 enum {
0727     NVME_AEN_BIT_NS_ATTR        = 8,
0728     NVME_AEN_BIT_FW_ACT     = 9,
0729     NVME_AEN_BIT_ANA_CHANGE     = 11,
0730     NVME_AEN_BIT_DISC_CHANGE    = 31,
0731 };
0732 
0733 enum {
0734     NVME_AEN_CFG_NS_ATTR        = 1 << NVME_AEN_BIT_NS_ATTR,
0735     NVME_AEN_CFG_FW_ACT     = 1 << NVME_AEN_BIT_FW_ACT,
0736     NVME_AEN_CFG_ANA_CHANGE     = 1 << NVME_AEN_BIT_ANA_CHANGE,
0737     NVME_AEN_CFG_DISC_CHANGE    = 1 << NVME_AEN_BIT_DISC_CHANGE,
0738 };
0739 
0740 struct nvme_lba_range_type {
0741     __u8            type;
0742     __u8            attributes;
0743     __u8            rsvd2[14];
0744     __le64          slba;
0745     __le64          nlb;
0746     __u8            guid[16];
0747     __u8            rsvd48[16];
0748 };
0749 
0750 enum {
0751     NVME_LBART_TYPE_FS  = 0x01,
0752     NVME_LBART_TYPE_RAID    = 0x02,
0753     NVME_LBART_TYPE_CACHE   = 0x03,
0754     NVME_LBART_TYPE_SWAP    = 0x04,
0755 
0756     NVME_LBART_ATTRIB_TEMP  = 1 << 0,
0757     NVME_LBART_ATTRIB_HIDE  = 1 << 1,
0758 };
0759 
0760 struct nvme_reservation_status {
0761     __le32  gen;
0762     __u8    rtype;
0763     __u8    regctl[2];
0764     __u8    resv5[2];
0765     __u8    ptpls;
0766     __u8    resv10[13];
0767     struct {
0768         __le16  cntlid;
0769         __u8    rcsts;
0770         __u8    resv3[5];
0771         __le64  hostid;
0772         __le64  rkey;
0773     } regctl_ds[];
0774 };
0775 
0776 enum nvme_async_event_type {
0777     NVME_AER_TYPE_ERROR = 0,
0778     NVME_AER_TYPE_SMART = 1,
0779     NVME_AER_TYPE_NOTICE    = 2,
0780 };
0781 
0782 /* I/O commands */
0783 
0784 enum nvme_opcode {
0785     nvme_cmd_flush      = 0x00,
0786     nvme_cmd_write      = 0x01,
0787     nvme_cmd_read       = 0x02,
0788     nvme_cmd_write_uncor    = 0x04,
0789     nvme_cmd_compare    = 0x05,
0790     nvme_cmd_write_zeroes   = 0x08,
0791     nvme_cmd_dsm        = 0x09,
0792     nvme_cmd_verify     = 0x0c,
0793     nvme_cmd_resv_register  = 0x0d,
0794     nvme_cmd_resv_report    = 0x0e,
0795     nvme_cmd_resv_acquire   = 0x11,
0796     nvme_cmd_resv_release   = 0x15,
0797     nvme_cmd_zone_mgmt_send = 0x79,
0798     nvme_cmd_zone_mgmt_recv = 0x7a,
0799     nvme_cmd_zone_append    = 0x7d,
0800 };
0801 
0802 #define nvme_opcode_name(opcode)    { opcode, #opcode }
0803 #define show_nvm_opcode_name(val)               \
0804     __print_symbolic(val,                   \
0805         nvme_opcode_name(nvme_cmd_flush),       \
0806         nvme_opcode_name(nvme_cmd_write),       \
0807         nvme_opcode_name(nvme_cmd_read),        \
0808         nvme_opcode_name(nvme_cmd_write_uncor),     \
0809         nvme_opcode_name(nvme_cmd_compare),     \
0810         nvme_opcode_name(nvme_cmd_write_zeroes),    \
0811         nvme_opcode_name(nvme_cmd_dsm),         \
0812         nvme_opcode_name(nvme_cmd_resv_register),   \
0813         nvme_opcode_name(nvme_cmd_resv_report),     \
0814         nvme_opcode_name(nvme_cmd_resv_acquire),    \
0815         nvme_opcode_name(nvme_cmd_resv_release),    \
0816         nvme_opcode_name(nvme_cmd_zone_mgmt_send),  \
0817         nvme_opcode_name(nvme_cmd_zone_mgmt_recv),  \
0818         nvme_opcode_name(nvme_cmd_zone_append))
0819 
0820 
0821 
0822 /*
0823  * Descriptor subtype - lower 4 bits of nvme_(keyed_)sgl_desc identifier
0824  *
0825  * @NVME_SGL_FMT_ADDRESS:     absolute address of the data block
0826  * @NVME_SGL_FMT_OFFSET:      relative offset of the in-capsule data block
0827  * @NVME_SGL_FMT_TRANSPORT_A: transport defined format, value 0xA
0828  * @NVME_SGL_FMT_INVALIDATE:  RDMA transport specific remote invalidation
0829  *                            request subtype
0830  */
0831 enum {
0832     NVME_SGL_FMT_ADDRESS        = 0x00,
0833     NVME_SGL_FMT_OFFSET     = 0x01,
0834     NVME_SGL_FMT_TRANSPORT_A    = 0x0A,
0835     NVME_SGL_FMT_INVALIDATE     = 0x0f,
0836 };
0837 
0838 /*
0839  * Descriptor type - upper 4 bits of nvme_(keyed_)sgl_desc identifier
0840  *
0841  * For struct nvme_sgl_desc:
0842  *   @NVME_SGL_FMT_DATA_DESC:       data block descriptor
0843  *   @NVME_SGL_FMT_SEG_DESC:        sgl segment descriptor
0844  *   @NVME_SGL_FMT_LAST_SEG_DESC:   last sgl segment descriptor
0845  *
0846  * For struct nvme_keyed_sgl_desc:
0847  *   @NVME_KEY_SGL_FMT_DATA_DESC:   keyed data block descriptor
0848  *
0849  * Transport-specific SGL types:
0850  *   @NVME_TRANSPORT_SGL_DATA_DESC: Transport SGL data dlock descriptor
0851  */
0852 enum {
0853     NVME_SGL_FMT_DATA_DESC      = 0x00,
0854     NVME_SGL_FMT_SEG_DESC       = 0x02,
0855     NVME_SGL_FMT_LAST_SEG_DESC  = 0x03,
0856     NVME_KEY_SGL_FMT_DATA_DESC  = 0x04,
0857     NVME_TRANSPORT_SGL_DATA_DESC    = 0x05,
0858 };
0859 
0860 struct nvme_sgl_desc {
0861     __le64  addr;
0862     __le32  length;
0863     __u8    rsvd[3];
0864     __u8    type;
0865 };
0866 
0867 struct nvme_keyed_sgl_desc {
0868     __le64  addr;
0869     __u8    length[3];
0870     __u8    key[4];
0871     __u8    type;
0872 };
0873 
0874 union nvme_data_ptr {
0875     struct {
0876         __le64  prp1;
0877         __le64  prp2;
0878     };
0879     struct nvme_sgl_desc    sgl;
0880     struct nvme_keyed_sgl_desc ksgl;
0881 };
0882 
0883 /*
0884  * Lowest two bits of our flags field (FUSE field in the spec):
0885  *
0886  * @NVME_CMD_FUSE_FIRST:   Fused Operation, first command
0887  * @NVME_CMD_FUSE_SECOND:  Fused Operation, second command
0888  *
0889  * Highest two bits in our flags field (PSDT field in the spec):
0890  *
0891  * @NVME_CMD_PSDT_SGL_METABUF:  Use SGLS for this transfer,
0892  *  If used, MPTR contains addr of single physical buffer (byte aligned).
0893  * @NVME_CMD_PSDT_SGL_METASEG:  Use SGLS for this transfer,
0894  *  If used, MPTR contains an address of an SGL segment containing
0895  *  exactly 1 SGL descriptor (qword aligned).
0896  */
0897 enum {
0898     NVME_CMD_FUSE_FIRST = (1 << 0),
0899     NVME_CMD_FUSE_SECOND    = (1 << 1),
0900 
0901     NVME_CMD_SGL_METABUF    = (1 << 6),
0902     NVME_CMD_SGL_METASEG    = (1 << 7),
0903     NVME_CMD_SGL_ALL    = NVME_CMD_SGL_METABUF | NVME_CMD_SGL_METASEG,
0904 };
0905 
0906 struct nvme_common_command {
0907     __u8            opcode;
0908     __u8            flags;
0909     __u16           command_id;
0910     __le32          nsid;
0911     __le32          cdw2[2];
0912     __le64          metadata;
0913     union nvme_data_ptr dptr;
0914     struct_group(cdws,
0915     __le32          cdw10;
0916     __le32          cdw11;
0917     __le32          cdw12;
0918     __le32          cdw13;
0919     __le32          cdw14;
0920     __le32          cdw15;
0921     );
0922 };
0923 
0924 struct nvme_rw_command {
0925     __u8            opcode;
0926     __u8            flags;
0927     __u16           command_id;
0928     __le32          nsid;
0929     __le32          cdw2;
0930     __le32          cdw3;
0931     __le64          metadata;
0932     union nvme_data_ptr dptr;
0933     __le64          slba;
0934     __le16          length;
0935     __le16          control;
0936     __le32          dsmgmt;
0937     __le32          reftag;
0938     __le16          apptag;
0939     __le16          appmask;
0940 };
0941 
0942 enum {
0943     NVME_RW_LR          = 1 << 15,
0944     NVME_RW_FUA         = 1 << 14,
0945     NVME_RW_APPEND_PIREMAP      = 1 << 9,
0946     NVME_RW_DSM_FREQ_UNSPEC     = 0,
0947     NVME_RW_DSM_FREQ_TYPICAL    = 1,
0948     NVME_RW_DSM_FREQ_RARE       = 2,
0949     NVME_RW_DSM_FREQ_READS      = 3,
0950     NVME_RW_DSM_FREQ_WRITES     = 4,
0951     NVME_RW_DSM_FREQ_RW     = 5,
0952     NVME_RW_DSM_FREQ_ONCE       = 6,
0953     NVME_RW_DSM_FREQ_PREFETCH   = 7,
0954     NVME_RW_DSM_FREQ_TEMP       = 8,
0955     NVME_RW_DSM_LATENCY_NONE    = 0 << 4,
0956     NVME_RW_DSM_LATENCY_IDLE    = 1 << 4,
0957     NVME_RW_DSM_LATENCY_NORM    = 2 << 4,
0958     NVME_RW_DSM_LATENCY_LOW     = 3 << 4,
0959     NVME_RW_DSM_SEQ_REQ     = 1 << 6,
0960     NVME_RW_DSM_COMPRESSED      = 1 << 7,
0961     NVME_RW_PRINFO_PRCHK_REF    = 1 << 10,
0962     NVME_RW_PRINFO_PRCHK_APP    = 1 << 11,
0963     NVME_RW_PRINFO_PRCHK_GUARD  = 1 << 12,
0964     NVME_RW_PRINFO_PRACT        = 1 << 13,
0965     NVME_RW_DTYPE_STREAMS       = 1 << 4,
0966 };
0967 
0968 struct nvme_dsm_cmd {
0969     __u8            opcode;
0970     __u8            flags;
0971     __u16           command_id;
0972     __le32          nsid;
0973     __u64           rsvd2[2];
0974     union nvme_data_ptr dptr;
0975     __le32          nr;
0976     __le32          attributes;
0977     __u32           rsvd12[4];
0978 };
0979 
0980 enum {
0981     NVME_DSMGMT_IDR     = 1 << 0,
0982     NVME_DSMGMT_IDW     = 1 << 1,
0983     NVME_DSMGMT_AD      = 1 << 2,
0984 };
0985 
0986 #define NVME_DSM_MAX_RANGES 256
0987 
0988 struct nvme_dsm_range {
0989     __le32          cattr;
0990     __le32          nlb;
0991     __le64          slba;
0992 };
0993 
0994 struct nvme_write_zeroes_cmd {
0995     __u8            opcode;
0996     __u8            flags;
0997     __u16           command_id;
0998     __le32          nsid;
0999     __u64           rsvd2;
1000     __le64          metadata;
1001     union nvme_data_ptr dptr;
1002     __le64          slba;
1003     __le16          length;
1004     __le16          control;
1005     __le32          dsmgmt;
1006     __le32          reftag;
1007     __le16          apptag;
1008     __le16          appmask;
1009 };
1010 
1011 enum nvme_zone_mgmt_action {
1012     NVME_ZONE_CLOSE     = 0x1,
1013     NVME_ZONE_FINISH    = 0x2,
1014     NVME_ZONE_OPEN      = 0x3,
1015     NVME_ZONE_RESET     = 0x4,
1016     NVME_ZONE_OFFLINE   = 0x5,
1017     NVME_ZONE_SET_DESC_EXT  = 0x10,
1018 };
1019 
1020 struct nvme_zone_mgmt_send_cmd {
1021     __u8            opcode;
1022     __u8            flags;
1023     __u16           command_id;
1024     __le32          nsid;
1025     __le32          cdw2[2];
1026     __le64          metadata;
1027     union nvme_data_ptr dptr;
1028     __le64          slba;
1029     __le32          cdw12;
1030     __u8            zsa;
1031     __u8            select_all;
1032     __u8            rsvd13[2];
1033     __le32          cdw14[2];
1034 };
1035 
1036 struct nvme_zone_mgmt_recv_cmd {
1037     __u8            opcode;
1038     __u8            flags;
1039     __u16           command_id;
1040     __le32          nsid;
1041     __le64          rsvd2[2];
1042     union nvme_data_ptr dptr;
1043     __le64          slba;
1044     __le32          numd;
1045     __u8            zra;
1046     __u8            zrasf;
1047     __u8            pr;
1048     __u8            rsvd13;
1049     __le32          cdw14[2];
1050 };
1051 
1052 enum {
1053     NVME_ZRA_ZONE_REPORT        = 0,
1054     NVME_ZRASF_ZONE_REPORT_ALL  = 0,
1055     NVME_ZRASF_ZONE_STATE_EMPTY = 0x01,
1056     NVME_ZRASF_ZONE_STATE_IMP_OPEN  = 0x02,
1057     NVME_ZRASF_ZONE_STATE_EXP_OPEN  = 0x03,
1058     NVME_ZRASF_ZONE_STATE_CLOSED    = 0x04,
1059     NVME_ZRASF_ZONE_STATE_READONLY  = 0x05,
1060     NVME_ZRASF_ZONE_STATE_FULL  = 0x06,
1061     NVME_ZRASF_ZONE_STATE_OFFLINE   = 0x07,
1062     NVME_REPORT_ZONE_PARTIAL    = 1,
1063 };
1064 
1065 /* Features */
1066 
1067 enum {
1068     NVME_TEMP_THRESH_MASK       = 0xffff,
1069     NVME_TEMP_THRESH_SELECT_SHIFT   = 16,
1070     NVME_TEMP_THRESH_TYPE_UNDER = 0x100000,
1071 };
1072 
1073 struct nvme_feat_auto_pst {
1074     __le64 entries[32];
1075 };
1076 
1077 enum {
1078     NVME_HOST_MEM_ENABLE    = (1 << 0),
1079     NVME_HOST_MEM_RETURN    = (1 << 1),
1080 };
1081 
1082 struct nvme_feat_host_behavior {
1083     __u8 acre;
1084     __u8 etdas;
1085     __u8 lbafee;
1086     __u8 resv1[509];
1087 };
1088 
1089 enum {
1090     NVME_ENABLE_ACRE    = 1,
1091     NVME_ENABLE_LBAFEE  = 1,
1092 };
1093 
1094 /* Admin commands */
1095 
1096 enum nvme_admin_opcode {
1097     nvme_admin_delete_sq        = 0x00,
1098     nvme_admin_create_sq        = 0x01,
1099     nvme_admin_get_log_page     = 0x02,
1100     nvme_admin_delete_cq        = 0x04,
1101     nvme_admin_create_cq        = 0x05,
1102     nvme_admin_identify     = 0x06,
1103     nvme_admin_abort_cmd        = 0x08,
1104     nvme_admin_set_features     = 0x09,
1105     nvme_admin_get_features     = 0x0a,
1106     nvme_admin_async_event      = 0x0c,
1107     nvme_admin_ns_mgmt      = 0x0d,
1108     nvme_admin_activate_fw      = 0x10,
1109     nvme_admin_download_fw      = 0x11,
1110     nvme_admin_dev_self_test    = 0x14,
1111     nvme_admin_ns_attach        = 0x15,
1112     nvme_admin_keep_alive       = 0x18,
1113     nvme_admin_directive_send   = 0x19,
1114     nvme_admin_directive_recv   = 0x1a,
1115     nvme_admin_virtual_mgmt     = 0x1c,
1116     nvme_admin_nvme_mi_send     = 0x1d,
1117     nvme_admin_nvme_mi_recv     = 0x1e,
1118     nvme_admin_dbbuf        = 0x7C,
1119     nvme_admin_format_nvm       = 0x80,
1120     nvme_admin_security_send    = 0x81,
1121     nvme_admin_security_recv    = 0x82,
1122     nvme_admin_sanitize_nvm     = 0x84,
1123     nvme_admin_get_lba_status   = 0x86,
1124     nvme_admin_vendor_start     = 0xC0,
1125 };
1126 
1127 #define nvme_admin_opcode_name(opcode)  { opcode, #opcode }
1128 #define show_admin_opcode_name(val)                 \
1129     __print_symbolic(val,                       \
1130         nvme_admin_opcode_name(nvme_admin_delete_sq),       \
1131         nvme_admin_opcode_name(nvme_admin_create_sq),       \
1132         nvme_admin_opcode_name(nvme_admin_get_log_page),    \
1133         nvme_admin_opcode_name(nvme_admin_delete_cq),       \
1134         nvme_admin_opcode_name(nvme_admin_create_cq),       \
1135         nvme_admin_opcode_name(nvme_admin_identify),        \
1136         nvme_admin_opcode_name(nvme_admin_abort_cmd),       \
1137         nvme_admin_opcode_name(nvme_admin_set_features),    \
1138         nvme_admin_opcode_name(nvme_admin_get_features),    \
1139         nvme_admin_opcode_name(nvme_admin_async_event),     \
1140         nvme_admin_opcode_name(nvme_admin_ns_mgmt),     \
1141         nvme_admin_opcode_name(nvme_admin_activate_fw),     \
1142         nvme_admin_opcode_name(nvme_admin_download_fw),     \
1143         nvme_admin_opcode_name(nvme_admin_ns_attach),       \
1144         nvme_admin_opcode_name(nvme_admin_keep_alive),      \
1145         nvme_admin_opcode_name(nvme_admin_directive_send),  \
1146         nvme_admin_opcode_name(nvme_admin_directive_recv),  \
1147         nvme_admin_opcode_name(nvme_admin_dbbuf),       \
1148         nvme_admin_opcode_name(nvme_admin_format_nvm),      \
1149         nvme_admin_opcode_name(nvme_admin_security_send),   \
1150         nvme_admin_opcode_name(nvme_admin_security_recv),   \
1151         nvme_admin_opcode_name(nvme_admin_sanitize_nvm),    \
1152         nvme_admin_opcode_name(nvme_admin_get_lba_status))
1153 
1154 enum {
1155     NVME_QUEUE_PHYS_CONTIG  = (1 << 0),
1156     NVME_CQ_IRQ_ENABLED = (1 << 1),
1157     NVME_SQ_PRIO_URGENT = (0 << 1),
1158     NVME_SQ_PRIO_HIGH   = (1 << 1),
1159     NVME_SQ_PRIO_MEDIUM = (2 << 1),
1160     NVME_SQ_PRIO_LOW    = (3 << 1),
1161     NVME_FEAT_ARBITRATION   = 0x01,
1162     NVME_FEAT_POWER_MGMT    = 0x02,
1163     NVME_FEAT_LBA_RANGE = 0x03,
1164     NVME_FEAT_TEMP_THRESH   = 0x04,
1165     NVME_FEAT_ERR_RECOVERY  = 0x05,
1166     NVME_FEAT_VOLATILE_WC   = 0x06,
1167     NVME_FEAT_NUM_QUEUES    = 0x07,
1168     NVME_FEAT_IRQ_COALESCE  = 0x08,
1169     NVME_FEAT_IRQ_CONFIG    = 0x09,
1170     NVME_FEAT_WRITE_ATOMIC  = 0x0a,
1171     NVME_FEAT_ASYNC_EVENT   = 0x0b,
1172     NVME_FEAT_AUTO_PST  = 0x0c,
1173     NVME_FEAT_HOST_MEM_BUF  = 0x0d,
1174     NVME_FEAT_TIMESTAMP = 0x0e,
1175     NVME_FEAT_KATO      = 0x0f,
1176     NVME_FEAT_HCTM      = 0x10,
1177     NVME_FEAT_NOPSC     = 0x11,
1178     NVME_FEAT_RRL       = 0x12,
1179     NVME_FEAT_PLM_CONFIG    = 0x13,
1180     NVME_FEAT_PLM_WINDOW    = 0x14,
1181     NVME_FEAT_HOST_BEHAVIOR = 0x16,
1182     NVME_FEAT_SANITIZE  = 0x17,
1183     NVME_FEAT_SW_PROGRESS   = 0x80,
1184     NVME_FEAT_HOST_ID   = 0x81,
1185     NVME_FEAT_RESV_MASK = 0x82,
1186     NVME_FEAT_RESV_PERSIST  = 0x83,
1187     NVME_FEAT_WRITE_PROTECT = 0x84,
1188     NVME_FEAT_VENDOR_START  = 0xC0,
1189     NVME_FEAT_VENDOR_END    = 0xFF,
1190     NVME_LOG_ERROR      = 0x01,
1191     NVME_LOG_SMART      = 0x02,
1192     NVME_LOG_FW_SLOT    = 0x03,
1193     NVME_LOG_CHANGED_NS = 0x04,
1194     NVME_LOG_CMD_EFFECTS    = 0x05,
1195     NVME_LOG_DEVICE_SELF_TEST = 0x06,
1196     NVME_LOG_TELEMETRY_HOST = 0x07,
1197     NVME_LOG_TELEMETRY_CTRL = 0x08,
1198     NVME_LOG_ENDURANCE_GROUP = 0x09,
1199     NVME_LOG_ANA        = 0x0c,
1200     NVME_LOG_DISC       = 0x70,
1201     NVME_LOG_RESERVATION    = 0x80,
1202     NVME_FWACT_REPL     = (0 << 3),
1203     NVME_FWACT_REPL_ACTV    = (1 << 3),
1204     NVME_FWACT_ACTV     = (2 << 3),
1205 };
1206 
1207 /* NVMe Namespace Write Protect State */
1208 enum {
1209     NVME_NS_NO_WRITE_PROTECT = 0,
1210     NVME_NS_WRITE_PROTECT,
1211     NVME_NS_WRITE_PROTECT_POWER_CYCLE,
1212     NVME_NS_WRITE_PROTECT_PERMANENT,
1213 };
1214 
1215 #define NVME_MAX_CHANGED_NAMESPACES 1024
1216 
1217 struct nvme_identify {
1218     __u8            opcode;
1219     __u8            flags;
1220     __u16           command_id;
1221     __le32          nsid;
1222     __u64           rsvd2[2];
1223     union nvme_data_ptr dptr;
1224     __u8            cns;
1225     __u8            rsvd3;
1226     __le16          ctrlid;
1227     __u8            rsvd11[3];
1228     __u8            csi;
1229     __u32           rsvd12[4];
1230 };
1231 
1232 #define NVME_IDENTIFY_DATA_SIZE 4096
1233 
1234 struct nvme_features {
1235     __u8            opcode;
1236     __u8            flags;
1237     __u16           command_id;
1238     __le32          nsid;
1239     __u64           rsvd2[2];
1240     union nvme_data_ptr dptr;
1241     __le32          fid;
1242     __le32          dword11;
1243     __le32                  dword12;
1244     __le32                  dword13;
1245     __le32                  dword14;
1246     __le32                  dword15;
1247 };
1248 
1249 struct nvme_host_mem_buf_desc {
1250     __le64          addr;
1251     __le32          size;
1252     __u32           rsvd;
1253 };
1254 
1255 struct nvme_create_cq {
1256     __u8            opcode;
1257     __u8            flags;
1258     __u16           command_id;
1259     __u32           rsvd1[5];
1260     __le64          prp1;
1261     __u64           rsvd8;
1262     __le16          cqid;
1263     __le16          qsize;
1264     __le16          cq_flags;
1265     __le16          irq_vector;
1266     __u32           rsvd12[4];
1267 };
1268 
1269 struct nvme_create_sq {
1270     __u8            opcode;
1271     __u8            flags;
1272     __u16           command_id;
1273     __u32           rsvd1[5];
1274     __le64          prp1;
1275     __u64           rsvd8;
1276     __le16          sqid;
1277     __le16          qsize;
1278     __le16          sq_flags;
1279     __le16          cqid;
1280     __u32           rsvd12[4];
1281 };
1282 
1283 struct nvme_delete_queue {
1284     __u8            opcode;
1285     __u8            flags;
1286     __u16           command_id;
1287     __u32           rsvd1[9];
1288     __le16          qid;
1289     __u16           rsvd10;
1290     __u32           rsvd11[5];
1291 };
1292 
1293 struct nvme_abort_cmd {
1294     __u8            opcode;
1295     __u8            flags;
1296     __u16           command_id;
1297     __u32           rsvd1[9];
1298     __le16          sqid;
1299     __u16           cid;
1300     __u32           rsvd11[5];
1301 };
1302 
1303 struct nvme_download_firmware {
1304     __u8            opcode;
1305     __u8            flags;
1306     __u16           command_id;
1307     __u32           rsvd1[5];
1308     union nvme_data_ptr dptr;
1309     __le32          numd;
1310     __le32          offset;
1311     __u32           rsvd12[4];
1312 };
1313 
1314 struct nvme_format_cmd {
1315     __u8            opcode;
1316     __u8            flags;
1317     __u16           command_id;
1318     __le32          nsid;
1319     __u64           rsvd2[4];
1320     __le32          cdw10;
1321     __u32           rsvd11[5];
1322 };
1323 
1324 struct nvme_get_log_page_command {
1325     __u8            opcode;
1326     __u8            flags;
1327     __u16           command_id;
1328     __le32          nsid;
1329     __u64           rsvd2[2];
1330     union nvme_data_ptr dptr;
1331     __u8            lid;
1332     __u8            lsp; /* upper 4 bits reserved */
1333     __le16          numdl;
1334     __le16          numdu;
1335     __u16           rsvd11;
1336     union {
1337         struct {
1338             __le32 lpol;
1339             __le32 lpou;
1340         };
1341         __le64 lpo;
1342     };
1343     __u8            rsvd14[3];
1344     __u8            csi;
1345     __u32           rsvd15;
1346 };
1347 
1348 struct nvme_directive_cmd {
1349     __u8            opcode;
1350     __u8            flags;
1351     __u16           command_id;
1352     __le32          nsid;
1353     __u64           rsvd2[2];
1354     union nvme_data_ptr dptr;
1355     __le32          numd;
1356     __u8            doper;
1357     __u8            dtype;
1358     __le16          dspec;
1359     __u8            endir;
1360     __u8            tdtype;
1361     __u16           rsvd15;
1362 
1363     __u32           rsvd16[3];
1364 };
1365 
1366 /*
1367  * Fabrics subcommands.
1368  */
1369 enum nvmf_fabrics_opcode {
1370     nvme_fabrics_command        = 0x7f,
1371 };
1372 
1373 enum nvmf_capsule_command {
1374     nvme_fabrics_type_property_set  = 0x00,
1375     nvme_fabrics_type_connect   = 0x01,
1376     nvme_fabrics_type_property_get  = 0x04,
1377     nvme_fabrics_type_auth_send = 0x05,
1378     nvme_fabrics_type_auth_receive  = 0x06,
1379 };
1380 
1381 #define nvme_fabrics_type_name(type)   { type, #type }
1382 #define show_fabrics_type_name(type)                    \
1383     __print_symbolic(type,                      \
1384         nvme_fabrics_type_name(nvme_fabrics_type_property_set), \
1385         nvme_fabrics_type_name(nvme_fabrics_type_connect),  \
1386         nvme_fabrics_type_name(nvme_fabrics_type_property_get), \
1387         nvme_fabrics_type_name(nvme_fabrics_type_auth_send),    \
1388         nvme_fabrics_type_name(nvme_fabrics_type_auth_receive))
1389 
1390 /*
1391  * If not fabrics command, fctype will be ignored.
1392  */
1393 #define show_opcode_name(qid, opcode, fctype)           \
1394     ((opcode) == nvme_fabrics_command ?         \
1395      show_fabrics_type_name(fctype) :           \
1396     ((qid) ?                        \
1397      show_nvm_opcode_name(opcode) :             \
1398      show_admin_opcode_name(opcode)))
1399 
1400 struct nvmf_common_command {
1401     __u8    opcode;
1402     __u8    resv1;
1403     __u16   command_id;
1404     __u8    fctype;
1405     __u8    resv2[35];
1406     __u8    ts[24];
1407 };
1408 
1409 /*
1410  * The legal cntlid range a NVMe Target will provide.
1411  * Note that cntlid of value 0 is considered illegal in the fabrics world.
1412  * Devices based on earlier specs did not have the subsystem concept;
1413  * therefore, those devices had their cntlid value set to 0 as a result.
1414  */
1415 #define NVME_CNTLID_MIN     1
1416 #define NVME_CNTLID_MAX     0xffef
1417 #define NVME_CNTLID_DYNAMIC 0xffff
1418 
1419 #define MAX_DISC_LOGS   255
1420 
1421 /* Discovery log page entry flags (EFLAGS): */
1422 enum {
1423     NVME_DISC_EFLAGS_EPCSD      = (1 << 1),
1424     NVME_DISC_EFLAGS_DUPRETINFO = (1 << 0),
1425 };
1426 
1427 /* Discovery log page entry */
1428 struct nvmf_disc_rsp_page_entry {
1429     __u8        trtype;
1430     __u8        adrfam;
1431     __u8        subtype;
1432     __u8        treq;
1433     __le16      portid;
1434     __le16      cntlid;
1435     __le16      asqsz;
1436     __le16      eflags;
1437     __u8        resv10[20];
1438     char        trsvcid[NVMF_TRSVCID_SIZE];
1439     __u8        resv64[192];
1440     char        subnqn[NVMF_NQN_FIELD_LEN];
1441     char        traddr[NVMF_TRADDR_SIZE];
1442     union tsas {
1443         char        common[NVMF_TSAS_SIZE];
1444         struct rdma {
1445             __u8    qptype;
1446             __u8    prtype;
1447             __u8    cms;
1448             __u8    resv3[5];
1449             __u16   pkey;
1450             __u8    resv10[246];
1451         } rdma;
1452     } tsas;
1453 };
1454 
1455 /* Discovery log page header */
1456 struct nvmf_disc_rsp_page_hdr {
1457     __le64      genctr;
1458     __le64      numrec;
1459     __le16      recfmt;
1460     __u8        resv14[1006];
1461     struct nvmf_disc_rsp_page_entry entries[];
1462 };
1463 
1464 enum {
1465     NVME_CONNECT_DISABLE_SQFLOW = (1 << 2),
1466 };
1467 
1468 struct nvmf_connect_command {
1469     __u8        opcode;
1470     __u8        resv1;
1471     __u16       command_id;
1472     __u8        fctype;
1473     __u8        resv2[19];
1474     union nvme_data_ptr dptr;
1475     __le16      recfmt;
1476     __le16      qid;
1477     __le16      sqsize;
1478     __u8        cattr;
1479     __u8        resv3;
1480     __le32      kato;
1481     __u8        resv4[12];
1482 };
1483 
1484 enum {
1485     NVME_CONNECT_AUTHREQ_ASCR   = (1 << 2),
1486     NVME_CONNECT_AUTHREQ_ATR    = (1 << 1),
1487 };
1488 
1489 struct nvmf_connect_data {
1490     uuid_t      hostid;
1491     __le16      cntlid;
1492     char        resv4[238];
1493     char        subsysnqn[NVMF_NQN_FIELD_LEN];
1494     char        hostnqn[NVMF_NQN_FIELD_LEN];
1495     char        resv5[256];
1496 };
1497 
1498 struct nvmf_property_set_command {
1499     __u8        opcode;
1500     __u8        resv1;
1501     __u16       command_id;
1502     __u8        fctype;
1503     __u8        resv2[35];
1504     __u8        attrib;
1505     __u8        resv3[3];
1506     __le32      offset;
1507     __le64      value;
1508     __u8        resv4[8];
1509 };
1510 
1511 struct nvmf_property_get_command {
1512     __u8        opcode;
1513     __u8        resv1;
1514     __u16       command_id;
1515     __u8        fctype;
1516     __u8        resv2[35];
1517     __u8        attrib;
1518     __u8        resv3[3];
1519     __le32      offset;
1520     __u8        resv4[16];
1521 };
1522 
1523 struct nvmf_auth_common_command {
1524     __u8        opcode;
1525     __u8        resv1;
1526     __u16       command_id;
1527     __u8        fctype;
1528     __u8        resv2[19];
1529     union nvme_data_ptr dptr;
1530     __u8        resv3;
1531     __u8        spsp0;
1532     __u8        spsp1;
1533     __u8        secp;
1534     __le32      al_tl;
1535     __u8        resv4[16];
1536 };
1537 
1538 struct nvmf_auth_send_command {
1539     __u8        opcode;
1540     __u8        resv1;
1541     __u16       command_id;
1542     __u8        fctype;
1543     __u8        resv2[19];
1544     union nvme_data_ptr dptr;
1545     __u8        resv3;
1546     __u8        spsp0;
1547     __u8        spsp1;
1548     __u8        secp;
1549     __le32      tl;
1550     __u8        resv4[16];
1551 };
1552 
1553 struct nvmf_auth_receive_command {
1554     __u8        opcode;
1555     __u8        resv1;
1556     __u16       command_id;
1557     __u8        fctype;
1558     __u8        resv2[19];
1559     union nvme_data_ptr dptr;
1560     __u8        resv3;
1561     __u8        spsp0;
1562     __u8        spsp1;
1563     __u8        secp;
1564     __le32      al;
1565     __u8        resv4[16];
1566 };
1567 
1568 /* Value for secp */
1569 enum {
1570     NVME_AUTH_DHCHAP_PROTOCOL_IDENTIFIER    = 0xe9,
1571 };
1572 
1573 /* Defined value for auth_type */
1574 enum {
1575     NVME_AUTH_COMMON_MESSAGES   = 0x00,
1576     NVME_AUTH_DHCHAP_MESSAGES   = 0x01,
1577 };
1578 
1579 /* Defined messages for auth_id */
1580 enum {
1581     NVME_AUTH_DHCHAP_MESSAGE_NEGOTIATE  = 0x00,
1582     NVME_AUTH_DHCHAP_MESSAGE_CHALLENGE  = 0x01,
1583     NVME_AUTH_DHCHAP_MESSAGE_REPLY      = 0x02,
1584     NVME_AUTH_DHCHAP_MESSAGE_SUCCESS1   = 0x03,
1585     NVME_AUTH_DHCHAP_MESSAGE_SUCCESS2   = 0x04,
1586     NVME_AUTH_DHCHAP_MESSAGE_FAILURE2   = 0xf0,
1587     NVME_AUTH_DHCHAP_MESSAGE_FAILURE1   = 0xf1,
1588 };
1589 
1590 struct nvmf_auth_dhchap_protocol_descriptor {
1591     __u8        authid;
1592     __u8        rsvd;
1593     __u8        halen;
1594     __u8        dhlen;
1595     __u8        idlist[60];
1596 };
1597 
1598 enum {
1599     NVME_AUTH_DHCHAP_AUTH_ID    = 0x01,
1600 };
1601 
1602 /* Defined hash functions for DH-HMAC-CHAP authentication */
1603 enum {
1604     NVME_AUTH_HASH_SHA256   = 0x01,
1605     NVME_AUTH_HASH_SHA384   = 0x02,
1606     NVME_AUTH_HASH_SHA512   = 0x03,
1607     NVME_AUTH_HASH_INVALID  = 0xff,
1608 };
1609 
1610 /* Defined Diffie-Hellman group identifiers for DH-HMAC-CHAP authentication */
1611 enum {
1612     NVME_AUTH_DHGROUP_NULL      = 0x00,
1613     NVME_AUTH_DHGROUP_2048      = 0x01,
1614     NVME_AUTH_DHGROUP_3072      = 0x02,
1615     NVME_AUTH_DHGROUP_4096      = 0x03,
1616     NVME_AUTH_DHGROUP_6144      = 0x04,
1617     NVME_AUTH_DHGROUP_8192      = 0x05,
1618     NVME_AUTH_DHGROUP_INVALID   = 0xff,
1619 };
1620 
1621 union nvmf_auth_protocol {
1622     struct nvmf_auth_dhchap_protocol_descriptor dhchap;
1623 };
1624 
1625 struct nvmf_auth_dhchap_negotiate_data {
1626     __u8        auth_type;
1627     __u8        auth_id;
1628     __le16      rsvd;
1629     __le16      t_id;
1630     __u8        sc_c;
1631     __u8        napd;
1632     union nvmf_auth_protocol auth_protocol[];
1633 };
1634 
1635 struct nvmf_auth_dhchap_challenge_data {
1636     __u8        auth_type;
1637     __u8        auth_id;
1638     __u16       rsvd1;
1639     __le16      t_id;
1640     __u8        hl;
1641     __u8        rsvd2;
1642     __u8        hashid;
1643     __u8        dhgid;
1644     __le16      dhvlen;
1645     __le32      seqnum;
1646     /* 'hl' bytes of challenge value */
1647     __u8        cval[];
1648     /* followed by 'dhvlen' bytes of DH value */
1649 };
1650 
1651 struct nvmf_auth_dhchap_reply_data {
1652     __u8        auth_type;
1653     __u8        auth_id;
1654     __le16      rsvd1;
1655     __le16      t_id;
1656     __u8        hl;
1657     __u8        rsvd2;
1658     __u8        cvalid;
1659     __u8        rsvd3;
1660     __le16      dhvlen;
1661     __le32      seqnum;
1662     /* 'hl' bytes of response data */
1663     __u8        rval[];
1664     /* followed by 'hl' bytes of Challenge value */
1665     /* followed by 'dhvlen' bytes of DH value */
1666 };
1667 
1668 enum {
1669     NVME_AUTH_DHCHAP_RESPONSE_VALID = (1 << 0),
1670 };
1671 
1672 struct nvmf_auth_dhchap_success1_data {
1673     __u8        auth_type;
1674     __u8        auth_id;
1675     __le16      rsvd1;
1676     __le16      t_id;
1677     __u8        hl;
1678     __u8        rsvd2;
1679     __u8        rvalid;
1680     __u8        rsvd3[7];
1681     /* 'hl' bytes of response value if 'rvalid' is set */
1682     __u8        rval[];
1683 };
1684 
1685 struct nvmf_auth_dhchap_success2_data {
1686     __u8        auth_type;
1687     __u8        auth_id;
1688     __le16      rsvd1;
1689     __le16      t_id;
1690     __u8        rsvd2[10];
1691 };
1692 
1693 struct nvmf_auth_dhchap_failure_data {
1694     __u8        auth_type;
1695     __u8        auth_id;
1696     __le16      rsvd1;
1697     __le16      t_id;
1698     __u8        rescode;
1699     __u8        rescode_exp;
1700 };
1701 
1702 enum {
1703     NVME_AUTH_DHCHAP_FAILURE_REASON_FAILED  = 0x01,
1704 };
1705 
1706 enum {
1707     NVME_AUTH_DHCHAP_FAILURE_FAILED         = 0x01,
1708     NVME_AUTH_DHCHAP_FAILURE_NOT_USABLE     = 0x02,
1709     NVME_AUTH_DHCHAP_FAILURE_CONCAT_MISMATCH    = 0x03,
1710     NVME_AUTH_DHCHAP_FAILURE_HASH_UNUSABLE      = 0x04,
1711     NVME_AUTH_DHCHAP_FAILURE_DHGROUP_UNUSABLE   = 0x05,
1712     NVME_AUTH_DHCHAP_FAILURE_INCORRECT_PAYLOAD  = 0x06,
1713     NVME_AUTH_DHCHAP_FAILURE_INCORRECT_MESSAGE  = 0x07,
1714 };
1715 
1716 
1717 struct nvme_dbbuf {
1718     __u8            opcode;
1719     __u8            flags;
1720     __u16           command_id;
1721     __u32           rsvd1[5];
1722     __le64          prp1;
1723     __le64          prp2;
1724     __u32           rsvd12[6];
1725 };
1726 
1727 struct streams_directive_params {
1728     __le16  msl;
1729     __le16  nssa;
1730     __le16  nsso;
1731     __u8    rsvd[10];
1732     __le32  sws;
1733     __le16  sgs;
1734     __le16  nsa;
1735     __le16  nso;
1736     __u8    rsvd2[6];
1737 };
1738 
1739 struct nvme_command {
1740     union {
1741         struct nvme_common_command common;
1742         struct nvme_rw_command rw;
1743         struct nvme_identify identify;
1744         struct nvme_features features;
1745         struct nvme_create_cq create_cq;
1746         struct nvme_create_sq create_sq;
1747         struct nvme_delete_queue delete_queue;
1748         struct nvme_download_firmware dlfw;
1749         struct nvme_format_cmd format;
1750         struct nvme_dsm_cmd dsm;
1751         struct nvme_write_zeroes_cmd write_zeroes;
1752         struct nvme_zone_mgmt_send_cmd zms;
1753         struct nvme_zone_mgmt_recv_cmd zmr;
1754         struct nvme_abort_cmd abort;
1755         struct nvme_get_log_page_command get_log_page;
1756         struct nvmf_common_command fabrics;
1757         struct nvmf_connect_command connect;
1758         struct nvmf_property_set_command prop_set;
1759         struct nvmf_property_get_command prop_get;
1760         struct nvmf_auth_common_command auth_common;
1761         struct nvmf_auth_send_command auth_send;
1762         struct nvmf_auth_receive_command auth_receive;
1763         struct nvme_dbbuf dbbuf;
1764         struct nvme_directive_cmd directive;
1765     };
1766 };
1767 
1768 static inline bool nvme_is_fabrics(struct nvme_command *cmd)
1769 {
1770     return cmd->common.opcode == nvme_fabrics_command;
1771 }
1772 
1773 struct nvme_error_slot {
1774     __le64      error_count;
1775     __le16      sqid;
1776     __le16      cmdid;
1777     __le16      status_field;
1778     __le16      param_error_location;
1779     __le64      lba;
1780     __le32      nsid;
1781     __u8        vs;
1782     __u8        resv[3];
1783     __le64      cs;
1784     __u8        resv2[24];
1785 };
1786 
1787 static inline bool nvme_is_write(struct nvme_command *cmd)
1788 {
1789     /*
1790      * What a mess...
1791      *
1792      * Why can't we simply have a Fabrics In and Fabrics out command?
1793      */
1794     if (unlikely(nvme_is_fabrics(cmd)))
1795         return cmd->fabrics.fctype & 1;
1796     return cmd->common.opcode & 1;
1797 }
1798 
1799 enum {
1800     /*
1801      * Generic Command Status:
1802      */
1803     NVME_SC_SUCCESS         = 0x0,
1804     NVME_SC_INVALID_OPCODE      = 0x1,
1805     NVME_SC_INVALID_FIELD       = 0x2,
1806     NVME_SC_CMDID_CONFLICT      = 0x3,
1807     NVME_SC_DATA_XFER_ERROR     = 0x4,
1808     NVME_SC_POWER_LOSS      = 0x5,
1809     NVME_SC_INTERNAL        = 0x6,
1810     NVME_SC_ABORT_REQ       = 0x7,
1811     NVME_SC_ABORT_QUEUE     = 0x8,
1812     NVME_SC_FUSED_FAIL      = 0x9,
1813     NVME_SC_FUSED_MISSING       = 0xa,
1814     NVME_SC_INVALID_NS      = 0xb,
1815     NVME_SC_CMD_SEQ_ERROR       = 0xc,
1816     NVME_SC_SGL_INVALID_LAST    = 0xd,
1817     NVME_SC_SGL_INVALID_COUNT   = 0xe,
1818     NVME_SC_SGL_INVALID_DATA    = 0xf,
1819     NVME_SC_SGL_INVALID_METADATA    = 0x10,
1820     NVME_SC_SGL_INVALID_TYPE    = 0x11,
1821     NVME_SC_CMB_INVALID_USE     = 0x12,
1822     NVME_SC_PRP_INVALID_OFFSET  = 0x13,
1823     NVME_SC_ATOMIC_WU_EXCEEDED  = 0x14,
1824     NVME_SC_OP_DENIED       = 0x15,
1825     NVME_SC_SGL_INVALID_OFFSET  = 0x16,
1826     NVME_SC_RESERVED        = 0x17,
1827     NVME_SC_HOST_ID_INCONSIST   = 0x18,
1828     NVME_SC_KA_TIMEOUT_EXPIRED  = 0x19,
1829     NVME_SC_KA_TIMEOUT_INVALID  = 0x1A,
1830     NVME_SC_ABORTED_PREEMPT_ABORT   = 0x1B,
1831     NVME_SC_SANITIZE_FAILED     = 0x1C,
1832     NVME_SC_SANITIZE_IN_PROGRESS    = 0x1D,
1833     NVME_SC_SGL_INVALID_GRANULARITY = 0x1E,
1834     NVME_SC_CMD_NOT_SUP_CMB_QUEUE   = 0x1F,
1835     NVME_SC_NS_WRITE_PROTECTED  = 0x20,
1836     NVME_SC_CMD_INTERRUPTED     = 0x21,
1837     NVME_SC_TRANSIENT_TR_ERR    = 0x22,
1838     NVME_SC_ADMIN_COMMAND_MEDIA_NOT_READY = 0x24,
1839     NVME_SC_INVALID_IO_CMD_SET  = 0x2C,
1840 
1841     NVME_SC_LBA_RANGE       = 0x80,
1842     NVME_SC_CAP_EXCEEDED        = 0x81,
1843     NVME_SC_NS_NOT_READY        = 0x82,
1844     NVME_SC_RESERVATION_CONFLICT    = 0x83,
1845     NVME_SC_FORMAT_IN_PROGRESS  = 0x84,
1846 
1847     /*
1848      * Command Specific Status:
1849      */
1850     NVME_SC_CQ_INVALID      = 0x100,
1851     NVME_SC_QID_INVALID     = 0x101,
1852     NVME_SC_QUEUE_SIZE      = 0x102,
1853     NVME_SC_ABORT_LIMIT     = 0x103,
1854     NVME_SC_ABORT_MISSING       = 0x104,
1855     NVME_SC_ASYNC_LIMIT     = 0x105,
1856     NVME_SC_FIRMWARE_SLOT       = 0x106,
1857     NVME_SC_FIRMWARE_IMAGE      = 0x107,
1858     NVME_SC_INVALID_VECTOR      = 0x108,
1859     NVME_SC_INVALID_LOG_PAGE    = 0x109,
1860     NVME_SC_INVALID_FORMAT      = 0x10a,
1861     NVME_SC_FW_NEEDS_CONV_RESET = 0x10b,
1862     NVME_SC_INVALID_QUEUE       = 0x10c,
1863     NVME_SC_FEATURE_NOT_SAVEABLE    = 0x10d,
1864     NVME_SC_FEATURE_NOT_CHANGEABLE  = 0x10e,
1865     NVME_SC_FEATURE_NOT_PER_NS  = 0x10f,
1866     NVME_SC_FW_NEEDS_SUBSYS_RESET   = 0x110,
1867     NVME_SC_FW_NEEDS_RESET      = 0x111,
1868     NVME_SC_FW_NEEDS_MAX_TIME   = 0x112,
1869     NVME_SC_FW_ACTIVATE_PROHIBITED  = 0x113,
1870     NVME_SC_OVERLAPPING_RANGE   = 0x114,
1871     NVME_SC_NS_INSUFFICIENT_CAP = 0x115,
1872     NVME_SC_NS_ID_UNAVAILABLE   = 0x116,
1873     NVME_SC_NS_ALREADY_ATTACHED = 0x118,
1874     NVME_SC_NS_IS_PRIVATE       = 0x119,
1875     NVME_SC_NS_NOT_ATTACHED     = 0x11a,
1876     NVME_SC_THIN_PROV_NOT_SUPP  = 0x11b,
1877     NVME_SC_CTRL_LIST_INVALID   = 0x11c,
1878     NVME_SC_SELT_TEST_IN_PROGRESS   = 0x11d,
1879     NVME_SC_BP_WRITE_PROHIBITED = 0x11e,
1880     NVME_SC_CTRL_ID_INVALID     = 0x11f,
1881     NVME_SC_SEC_CTRL_STATE_INVALID  = 0x120,
1882     NVME_SC_CTRL_RES_NUM_INVALID    = 0x121,
1883     NVME_SC_RES_ID_INVALID      = 0x122,
1884     NVME_SC_PMR_SAN_PROHIBITED  = 0x123,
1885     NVME_SC_ANA_GROUP_ID_INVALID    = 0x124,
1886     NVME_SC_ANA_ATTACH_FAILED   = 0x125,
1887 
1888     /*
1889      * I/O Command Set Specific - NVM commands:
1890      */
1891     NVME_SC_BAD_ATTRIBUTES      = 0x180,
1892     NVME_SC_INVALID_PI      = 0x181,
1893     NVME_SC_READ_ONLY       = 0x182,
1894     NVME_SC_ONCS_NOT_SUPPORTED  = 0x183,
1895 
1896     /*
1897      * I/O Command Set Specific - Fabrics commands:
1898      */
1899     NVME_SC_CONNECT_FORMAT      = 0x180,
1900     NVME_SC_CONNECT_CTRL_BUSY   = 0x181,
1901     NVME_SC_CONNECT_INVALID_PARAM   = 0x182,
1902     NVME_SC_CONNECT_RESTART_DISC    = 0x183,
1903     NVME_SC_CONNECT_INVALID_HOST    = 0x184,
1904 
1905     NVME_SC_DISCOVERY_RESTART   = 0x190,
1906     NVME_SC_AUTH_REQUIRED       = 0x191,
1907 
1908     /*
1909      * I/O Command Set Specific - Zoned commands:
1910      */
1911     NVME_SC_ZONE_BOUNDARY_ERROR = 0x1b8,
1912     NVME_SC_ZONE_FULL       = 0x1b9,
1913     NVME_SC_ZONE_READ_ONLY      = 0x1ba,
1914     NVME_SC_ZONE_OFFLINE        = 0x1bb,
1915     NVME_SC_ZONE_INVALID_WRITE  = 0x1bc,
1916     NVME_SC_ZONE_TOO_MANY_ACTIVE    = 0x1bd,
1917     NVME_SC_ZONE_TOO_MANY_OPEN  = 0x1be,
1918     NVME_SC_ZONE_INVALID_TRANSITION = 0x1bf,
1919 
1920     /*
1921      * Media and Data Integrity Errors:
1922      */
1923     NVME_SC_WRITE_FAULT     = 0x280,
1924     NVME_SC_READ_ERROR      = 0x281,
1925     NVME_SC_GUARD_CHECK     = 0x282,
1926     NVME_SC_APPTAG_CHECK        = 0x283,
1927     NVME_SC_REFTAG_CHECK        = 0x284,
1928     NVME_SC_COMPARE_FAILED      = 0x285,
1929     NVME_SC_ACCESS_DENIED       = 0x286,
1930     NVME_SC_UNWRITTEN_BLOCK     = 0x287,
1931 
1932     /*
1933      * Path-related Errors:
1934      */
1935     NVME_SC_INTERNAL_PATH_ERROR = 0x300,
1936     NVME_SC_ANA_PERSISTENT_LOSS = 0x301,
1937     NVME_SC_ANA_INACCESSIBLE    = 0x302,
1938     NVME_SC_ANA_TRANSITION      = 0x303,
1939     NVME_SC_CTRL_PATH_ERROR     = 0x360,
1940     NVME_SC_HOST_PATH_ERROR     = 0x370,
1941     NVME_SC_HOST_ABORTED_CMD    = 0x371,
1942 
1943     NVME_SC_CRD         = 0x1800,
1944     NVME_SC_MORE            = 0x2000,
1945     NVME_SC_DNR         = 0x4000,
1946 };
1947 
1948 struct nvme_completion {
1949     /*
1950      * Used by Admin and Fabrics commands to return data:
1951      */
1952     union nvme_result {
1953         __le16  u16;
1954         __le32  u32;
1955         __le64  u64;
1956     } result;
1957     __le16  sq_head;    /* how much of this queue may be reclaimed */
1958     __le16  sq_id;      /* submission queue that generated this entry */
1959     __u16   command_id; /* of the command which completed */
1960     __le16  status;     /* did the command fail, and if so, why? */
1961 };
1962 
1963 #define NVME_VS(major, minor, tertiary) \
1964     (((major) << 16) | ((minor) << 8) | (tertiary))
1965 
1966 #define NVME_MAJOR(ver)     ((ver) >> 16)
1967 #define NVME_MINOR(ver)     (((ver) >> 8) & 0xff)
1968 #define NVME_TERTIARY(ver)  ((ver) & 0xff)
1969 
1970 #endif /* _LINUX_NVME_H */
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