linux/mtd/spi-nor.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (C) 2014 Freescale Semiconductor, Inc.
0004  */
0005
0006 #ifndef __LINUX_MTD_SPI_NOR_H
0007 #define __LINUX_MTD_SPI_NOR_H
0008
0009 #include <linux/bitops.h>
0010 #include <linux/mtd/cfi.h>
0011 #include <linux/mtd/mtd.h>
0012 #include <linux/spi/spi-mem.h>
0013
0014 /*
0015  * Note on opcode nomenclature: some opcodes have a format like
0016  * SPINOR_OP_FUNCTION{4,}_x_y_z. The numbers x, y, and z stand for the number
0017  * of I/O lines used for the opcode, address, and data (respectively). The
0018  * FUNCTION has an optional suffix of '4', to represent an opcode which
0019  * requires a 4-byte (32-bit) address.
0020  */
0021
0022 /* Flash opcodes. */
0023 #define SPINOR_OP_WRDI      0x04    /* Write disable */
0024 #define SPINOR_OP_WREN      0x06    /* Write enable */
0025 #define SPINOR_OP_RDSR      0x05    /* Read status register */
0026 #define SPINOR_OP_WRSR      0x01    /* Write status register 1 byte */
0027 #define SPINOR_OP_RDSR2     0x3f    /* Read status register 2 */
0028 #define SPINOR_OP_WRSR2     0x3e    /* Write status register 2 */
0029 #define SPINOR_OP_READ      0x03    /* Read data bytes (low frequency) */
0030 #define SPINOR_OP_READ_FAST 0x0b    /* Read data bytes (high frequency) */
0031 #define SPINOR_OP_READ_1_1_2    0x3b    /* Read data bytes (Dual Output SPI) */
0032 #define SPINOR_OP_READ_1_2_2    0xbb    /* Read data bytes (Dual I/O SPI) */
0033 #define SPINOR_OP_READ_1_1_4    0x6b    /* Read data bytes (Quad Output SPI) */
0034 #define SPINOR_OP_READ_1_4_4    0xeb    /* Read data bytes (Quad I/O SPI) */
0035 #define SPINOR_OP_READ_1_1_8    0x8b    /* Read data bytes (Octal Output SPI) */
0036 #define SPINOR_OP_READ_1_8_8    0xcb    /* Read data bytes (Octal I/O SPI) */
0037 #define SPINOR_OP_PP        0x02    /* Page program (up to 256 bytes) */
0038 #define SPINOR_OP_PP_1_1_4  0x32    /* Quad page program */
0039 #define SPINOR_OP_PP_1_4_4  0x38    /* Quad page program */
0040 #define SPINOR_OP_PP_1_1_8  0x82    /* Octal page program */
0041 #define SPINOR_OP_PP_1_8_8  0xc2    /* Octal page program */
0042 #define SPINOR_OP_BE_4K     0x20    /* Erase 4KiB block */
0043 #define SPINOR_OP_BE_4K_PMC 0xd7    /* Erase 4KiB block on PMC chips */
0044 #define SPINOR_OP_BE_32K    0x52    /* Erase 32KiB block */
0045 #define SPINOR_OP_CHIP_ERASE    0xc7    /* Erase whole flash chip */
0046 #define SPINOR_OP_SE        0xd8    /* Sector erase (usually 64KiB) */
0047 #define SPINOR_OP_RDID      0x9f    /* Read JEDEC ID */
0048 #define SPINOR_OP_RDSFDP    0x5a    /* Read SFDP */
0049 #define SPINOR_OP_RDCR      0x35    /* Read configuration register */
0050 #define SPINOR_OP_SRSTEN    0x66    /* Software Reset Enable */
0051 #define SPINOR_OP_SRST      0x99    /* Software Reset */
0052 #define SPINOR_OP_GBULK     0x98    /* Global Block Unlock */
0053
0054 /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */
0055 #define SPINOR_OP_READ_4B   0x13    /* Read data bytes (low frequency) */
0056 #define SPINOR_OP_READ_FAST_4B  0x0c    /* Read data bytes (high frequency) */
0057 #define SPINOR_OP_READ_1_1_2_4B 0x3c    /* Read data bytes (Dual Output SPI) */
0058 #define SPINOR_OP_READ_1_2_2_4B 0xbc    /* Read data bytes (Dual I/O SPI) */
0059 #define SPINOR_OP_READ_1_1_4_4B 0x6c    /* Read data bytes (Quad Output SPI) */
0060 #define SPINOR_OP_READ_1_4_4_4B 0xec    /* Read data bytes (Quad I/O SPI) */
0061 #define SPINOR_OP_READ_1_1_8_4B 0x7c    /* Read data bytes (Octal Output SPI) */
0062 #define SPINOR_OP_READ_1_8_8_4B 0xcc    /* Read data bytes (Octal I/O SPI) */
0063 #define SPINOR_OP_PP_4B     0x12    /* Page program (up to 256 bytes) */
0064 #define SPINOR_OP_PP_1_1_4_4B   0x34    /* Quad page program */
0065 #define SPINOR_OP_PP_1_4_4_4B   0x3e    /* Quad page program */
0066 #define SPINOR_OP_PP_1_1_8_4B   0x84    /* Octal page program */
0067 #define SPINOR_OP_PP_1_8_8_4B   0x8e    /* Octal page program */
0068 #define SPINOR_OP_BE_4K_4B  0x21    /* Erase 4KiB block */
0069 #define SPINOR_OP_BE_32K_4B 0x5c    /* Erase 32KiB block */
0070 #define SPINOR_OP_SE_4B     0xdc    /* Sector erase (usually 64KiB) */
0071
0072 /* Double Transfer Rate opcodes - defined in JEDEC JESD216B. */
0073 #define SPINOR_OP_READ_1_1_1_DTR    0x0d
0074 #define SPINOR_OP_READ_1_2_2_DTR    0xbd
0075 #define SPINOR_OP_READ_1_4_4_DTR    0xed
0076
0077 #define SPINOR_OP_READ_1_1_1_DTR_4B 0x0e
0078 #define SPINOR_OP_READ_1_2_2_DTR_4B 0xbe
0079 #define SPINOR_OP_READ_1_4_4_DTR_4B 0xee
0080
0081 /* Used for SST flashes only. */
0082 #define SPINOR_OP_BP        0x02    /* Byte program */
0083 #define SPINOR_OP_AAI_WP    0xad    /* Auto address increment word program */
0084
0085 /* Used for Macronix and Winbond flashes. */
0086 #define SPINOR_OP_EN4B      0xb7    /* Enter 4-byte mode */
0087 #define SPINOR_OP_EX4B      0xe9    /* Exit 4-byte mode */
0088
0089 /* Used for Spansion flashes only. */
0090 #define SPINOR_OP_BRWR      0x17    /* Bank register write */
0091
0092 /* Used for Micron flashes only. */
0093 #define SPINOR_OP_RD_EVCR      0x65    /* Read EVCR register */
0094 #define SPINOR_OP_WD_EVCR      0x61    /* Write EVCR register */
0095
0096 /* Used for GigaDevices and Winbond flashes. */
0097 #define SPINOR_OP_ESECR     0x44    /* Erase Security registers */
0098 #define SPINOR_OP_PSECR     0x42    /* Program Security registers */
0099 #define SPINOR_OP_RSECR     0x48    /* Read Security registers */
0100
0101 /* Status Register bits. */
0102 #define SR_WIP          BIT(0)  /* Write in progress */
0103 #define SR_WEL          BIT(1)  /* Write enable latch */
0104 /* meaning of other SR_* bits may differ between vendors */
0105 #define SR_BP0          BIT(2)  /* Block protect 0 */
0106 #define SR_BP1          BIT(3)  /* Block protect 1 */
0107 #define SR_BP2          BIT(4)  /* Block protect 2 */
0108 #define SR_BP3          BIT(5)  /* Block protect 3 */
0109 #define SR_TB_BIT5      BIT(5)  /* Top/Bottom protect */
0110 #define SR_BP3_BIT6     BIT(6)  /* Block protect 3 */
0111 #define SR_TB_BIT6      BIT(6)  /* Top/Bottom protect */
0112 #define SR_SRWD         BIT(7)  /* SR write protect */
0113 /* Spansion/Cypress specific status bits */
0114 #define SR_E_ERR        BIT(5)
0115 #define SR_P_ERR        BIT(6)
0116
0117 #define SR1_QUAD_EN_BIT6    BIT(6)
0118
0119 #define SR_BP_SHIFT     2
0120
0121 /* Enhanced Volatile Configuration Register bits */
0122 #define EVCR_QUAD_EN_MICRON BIT(7)  /* Micron Quad I/O */
0123
0124 /* Status Register 2 bits. */
0125 #define SR2_QUAD_EN_BIT1    BIT(1)
0126 #define SR2_LB1         BIT(3)  /* Security Register Lock Bit 1 */
0127 #define SR2_LB2         BIT(4)  /* Security Register Lock Bit 2 */
0128 #define SR2_LB3         BIT(5)  /* Security Register Lock Bit 3 */
0129 #define SR2_QUAD_EN_BIT7    BIT(7)
0130
0131 /* Supported SPI protocols */
0132 #define SNOR_PROTO_INST_MASK    GENMASK(23, 16)
0133 #define SNOR_PROTO_INST_SHIFT   16
0134 #define SNOR_PROTO_INST(_nbits) \
0135     ((((unsigned long)(_nbits)) << SNOR_PROTO_INST_SHIFT) & \
0136      SNOR_PROTO_INST_MASK)
0137
0138 #define SNOR_PROTO_ADDR_MASK    GENMASK(15, 8)
0139 #define SNOR_PROTO_ADDR_SHIFT   8
0140 #define SNOR_PROTO_ADDR(_nbits) \
0141     ((((unsigned long)(_nbits)) << SNOR_PROTO_ADDR_SHIFT) & \
0142      SNOR_PROTO_ADDR_MASK)
0143
0144 #define SNOR_PROTO_DATA_MASK    GENMASK(7, 0)
0145 #define SNOR_PROTO_DATA_SHIFT   0
0146 #define SNOR_PROTO_DATA(_nbits) \
0147     ((((unsigned long)(_nbits)) << SNOR_PROTO_DATA_SHIFT) & \
0148      SNOR_PROTO_DATA_MASK)
0149
0150 #define SNOR_PROTO_IS_DTR   BIT(24) /* Double Transfer Rate */
0151
0152 #define SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits)   \
0153     (SNOR_PROTO_INST(_inst_nbits) |             \
0154      SNOR_PROTO_ADDR(_addr_nbits) |             \
0155      SNOR_PROTO_DATA(_data_nbits))
0156 #define SNOR_PROTO_DTR(_inst_nbits, _addr_nbits, _data_nbits)   \
0157     (SNOR_PROTO_IS_DTR |                    \
0158      SNOR_PROTO_STR(_inst_nbits, _addr_nbits, _data_nbits))
0159
0160 enum spi_nor_protocol {
0161     SNOR_PROTO_1_1_1 = SNOR_PROTO_STR(1, 1, 1),
0162     SNOR_PROTO_1_1_2 = SNOR_PROTO_STR(1, 1, 2),
0163     SNOR_PROTO_1_1_4 = SNOR_PROTO_STR(1, 1, 4),
0164     SNOR_PROTO_1_1_8 = SNOR_PROTO_STR(1, 1, 8),
0165     SNOR_PROTO_1_2_2 = SNOR_PROTO_STR(1, 2, 2),
0166     SNOR_PROTO_1_4_4 = SNOR_PROTO_STR(1, 4, 4),
0167     SNOR_PROTO_1_8_8 = SNOR_PROTO_STR(1, 8, 8),
0168     SNOR_PROTO_2_2_2 = SNOR_PROTO_STR(2, 2, 2),
0169     SNOR_PROTO_4_4_4 = SNOR_PROTO_STR(4, 4, 4),
0170     SNOR_PROTO_8_8_8 = SNOR_PROTO_STR(8, 8, 8),
0171
0172     SNOR_PROTO_1_1_1_DTR = SNOR_PROTO_DTR(1, 1, 1),
0173     SNOR_PROTO_1_2_2_DTR = SNOR_PROTO_DTR(1, 2, 2),
0174     SNOR_PROTO_1_4_4_DTR = SNOR_PROTO_DTR(1, 4, 4),
0175     SNOR_PROTO_1_8_8_DTR = SNOR_PROTO_DTR(1, 8, 8),
0176     SNOR_PROTO_8_8_8_DTR = SNOR_PROTO_DTR(8, 8, 8),
0177 };
0178
0179 static inline bool spi_nor_protocol_is_dtr(enum spi_nor_protocol proto)
0180 {
0181     return !!(proto & SNOR_PROTO_IS_DTR);
0182 }
0183
0184 static inline u8 spi_nor_get_protocol_inst_nbits(enum spi_nor_protocol proto)
0185 {
0186     return ((unsigned long)(proto & SNOR_PROTO_INST_MASK)) >>
0187         SNOR_PROTO_INST_SHIFT;
0188 }
0189
0190 static inline u8 spi_nor_get_protocol_addr_nbits(enum spi_nor_protocol proto)
0191 {
0192     return ((unsigned long)(proto & SNOR_PROTO_ADDR_MASK)) >>
0193         SNOR_PROTO_ADDR_SHIFT;
0194 }
0195
0196 static inline u8 spi_nor_get_protocol_data_nbits(enum spi_nor_protocol proto)
0197 {
0198     return ((unsigned long)(proto & SNOR_PROTO_DATA_MASK)) >>
0199         SNOR_PROTO_DATA_SHIFT;
0200 }
0201
0202 static inline u8 spi_nor_get_protocol_width(enum spi_nor_protocol proto)
0203 {
0204     return spi_nor_get_protocol_data_nbits(proto);
0205 }
0206
0207 /**
0208  * struct spi_nor_hwcaps - Structure for describing the hardware capabilies
0209  * supported by the SPI controller (bus master).
0210  * @mask:       the bitmask listing all the supported hw capabilies
0211  */
0212 struct spi_nor_hwcaps {
0213     u32 mask;
0214 };
0215
0216 /*
0217  *(Fast) Read capabilities.
0218  * MUST be ordered by priority: the higher bit position, the higher priority.
0219  * As a matter of performances, it is relevant to use Octal SPI protocols first,
0220  * then Quad SPI protocols before Dual SPI protocols, Fast Read and lastly
0221  * (Slow) Read.
0222  */
0223 #define SNOR_HWCAPS_READ_MASK       GENMASK(15, 0)
0224 #define SNOR_HWCAPS_READ        BIT(0)
0225 #define SNOR_HWCAPS_READ_FAST       BIT(1)
0226 #define SNOR_HWCAPS_READ_1_1_1_DTR  BIT(2)
0227
0228 #define SNOR_HWCAPS_READ_DUAL       GENMASK(6, 3)
0229 #define SNOR_HWCAPS_READ_1_1_2      BIT(3)
0230 #define SNOR_HWCAPS_READ_1_2_2      BIT(4)
0231 #define SNOR_HWCAPS_READ_2_2_2      BIT(5)
0232 #define SNOR_HWCAPS_READ_1_2_2_DTR  BIT(6)
0233
0234 #define SNOR_HWCAPS_READ_QUAD       GENMASK(10, 7)
0235 #define SNOR_HWCAPS_READ_1_1_4      BIT(7)
0236 #define SNOR_HWCAPS_READ_1_4_4      BIT(8)
0237 #define SNOR_HWCAPS_READ_4_4_4      BIT(9)
0238 #define SNOR_HWCAPS_READ_1_4_4_DTR  BIT(10)
0239
0240 #define SNOR_HWCAPS_READ_OCTAL      GENMASK(15, 11)
0241 #define SNOR_HWCAPS_READ_1_1_8      BIT(11)
0242 #define SNOR_HWCAPS_READ_1_8_8      BIT(12)
0243 #define SNOR_HWCAPS_READ_8_8_8      BIT(13)
0244 #define SNOR_HWCAPS_READ_1_8_8_DTR  BIT(14)
0245 #define SNOR_HWCAPS_READ_8_8_8_DTR  BIT(15)
0246
0247 /*
0248  * Page Program capabilities.
0249  * MUST be ordered by priority: the higher bit position, the higher priority.
0250  * Like (Fast) Read capabilities, Octal/Quad SPI protocols are preferred to the
0251  * legacy SPI 1-1-1 protocol.
0252  * Note that Dual Page Programs are not supported because there is no existing
0253  * JEDEC/SFDP standard to define them. Also at this moment no SPI flash memory
0254  * implements such commands.
0255  */
0256 #define SNOR_HWCAPS_PP_MASK     GENMASK(23, 16)
0257 #define SNOR_HWCAPS_PP          BIT(16)
0258
0259 #define SNOR_HWCAPS_PP_QUAD     GENMASK(19, 17)
0260 #define SNOR_HWCAPS_PP_1_1_4        BIT(17)
0261 #define SNOR_HWCAPS_PP_1_4_4        BIT(18)
0262 #define SNOR_HWCAPS_PP_4_4_4        BIT(19)
0263
0264 #define SNOR_HWCAPS_PP_OCTAL        GENMASK(23, 20)
0265 #define SNOR_HWCAPS_PP_1_1_8        BIT(20)
0266 #define SNOR_HWCAPS_PP_1_8_8        BIT(21)
0267 #define SNOR_HWCAPS_PP_8_8_8        BIT(22)
0268 #define SNOR_HWCAPS_PP_8_8_8_DTR    BIT(23)
0269
0270 #define SNOR_HWCAPS_X_X_X   (SNOR_HWCAPS_READ_2_2_2 |   \
0271                  SNOR_HWCAPS_READ_4_4_4 |   \
0272                  SNOR_HWCAPS_READ_8_8_8 |   \
0273                  SNOR_HWCAPS_PP_4_4_4 |     \
0274                  SNOR_HWCAPS_PP_8_8_8)
0275
0276 #define SNOR_HWCAPS_X_X_X_DTR   (SNOR_HWCAPS_READ_8_8_8_DTR |   \
0277                  SNOR_HWCAPS_PP_8_8_8_DTR)
0278
0279 #define SNOR_HWCAPS_DTR     (SNOR_HWCAPS_READ_1_1_1_DTR |   \
0280                  SNOR_HWCAPS_READ_1_2_2_DTR |   \
0281                  SNOR_HWCAPS_READ_1_4_4_DTR |   \
0282                  SNOR_HWCAPS_READ_1_8_8_DTR |   \
0283                  SNOR_HWCAPS_READ_8_8_8_DTR)
0284
0285 #define SNOR_HWCAPS_ALL     (SNOR_HWCAPS_READ_MASK |    \
0286                  SNOR_HWCAPS_PP_MASK)
0287
0288 /* Forward declaration that is used in 'struct spi_nor_controller_ops' */
0289 struct spi_nor;
0290
0291 /**
0292  * struct spi_nor_controller_ops - SPI NOR controller driver specific
0293  *                                 operations.
0294  * @prepare:        [OPTIONAL] do some preparations for the
0295  *          read/write/erase/lock/unlock operations.
0296  * @unprepare:      [OPTIONAL] do some post work after the
0297  *          read/write/erase/lock/unlock operations.
0298  * @read_reg:       read out the register.
0299  * @write_reg:      write data to the register.
0300  * @read:       read data from the SPI NOR.
0301  * @write:      write data to the SPI NOR.
0302  * @erase:      erase a sector of the SPI NOR at the offset @offs; if
0303  *          not provided by the driver, SPI NOR will send the erase
0304  *          opcode via write_reg().
0305  */
0306 struct spi_nor_controller_ops {
0307     int (*prepare)(struct spi_nor *nor);
0308     void (*unprepare)(struct spi_nor *nor);
0309     int (*read_reg)(struct spi_nor *nor, u8 opcode, u8 *buf, size_t len);
0310     int (*write_reg)(struct spi_nor *nor, u8 opcode, const u8 *buf,
0311              size_t len);
0312
0313     ssize_t (*read)(struct spi_nor *nor, loff_t from, size_t len, u8 *buf);
0314     ssize_t (*write)(struct spi_nor *nor, loff_t to, size_t len,
0315              const u8 *buf);
0316     int (*erase)(struct spi_nor *nor, loff_t offs);
0317 };
0318
0319 /**
0320  * enum spi_nor_cmd_ext - describes the command opcode extension in DTR mode
0321  * @SPI_NOR_EXT_NONE: no extension. This is the default, and is used in Legacy
0322  *            SPI mode
0323  * @SPI_NOR_EXT_REPEAT: the extension is same as the opcode
0324  * @SPI_NOR_EXT_INVERT: the extension is the bitwise inverse of the opcode
0325  * @SPI_NOR_EXT_HEX: the extension is any hex value. The command and opcode
0326  *           combine to form a 16-bit opcode.
0327  */
0328 enum spi_nor_cmd_ext {
0329     SPI_NOR_EXT_NONE = 0,
0330     SPI_NOR_EXT_REPEAT,
0331     SPI_NOR_EXT_INVERT,
0332     SPI_NOR_EXT_HEX,
0333 };
0334
0335 /*
0336  * Forward declarations that are used internally by the core and manufacturer
0337  * drivers.
0338  */
0339 struct flash_info;
0340 struct spi_nor_manufacturer;
0341 struct spi_nor_flash_parameter;
0342
0343 /**
0344  * struct spi_nor - Structure for defining the SPI NOR layer
0345  * @mtd:        an mtd_info structure
0346  * @lock:       the lock for the read/write/erase/lock/unlock operations
0347  * @dev:        pointer to an SPI device or an SPI NOR controller device
0348  * @spimem:     pointer to the SPI memory device
0349  * @bouncebuf:      bounce buffer used when the buffer passed by the MTD
0350  *                      layer is not DMA-able
0351  * @bouncebuf_size: size of the bounce buffer
0352  * @info:       SPI NOR part JEDEC MFR ID and other info
0353  * @manufacturer:   SPI NOR manufacturer
0354  * @addr_nbytes:    number of address bytes
0355  * @erase_opcode:   the opcode for erasing a sector
0356  * @read_opcode:    the read opcode
0357  * @read_dummy:     the dummy needed by the read operation
0358  * @program_opcode: the program opcode
0359  * @sst_write_second:   used by the SST write operation
0360  * @flags:      flag options for the current SPI NOR (SNOR_F_*)
0361  * @cmd_ext_type:   the command opcode extension type for DTR mode.
0362  * @read_proto:     the SPI protocol for read operations
0363  * @write_proto:    the SPI protocol for write operations
0364  * @reg_proto:      the SPI protocol for read_reg/write_reg/erase operations
0365  * @sfdp:       the SFDP data of the flash
0366  * @debugfs_root:   pointer to the debugfs directory
0367  * @controller_ops: SPI NOR controller driver specific operations.
0368  * @params:     [FLASH-SPECIFIC] SPI NOR flash parameters and settings.
0369  *                      The structure includes legacy flash parameters and
0370  *                      settings that can be overwritten by the spi_nor_fixups
0371  *                      hooks, or dynamically when parsing the SFDP tables.
0372  * @dirmap:     pointers to struct spi_mem_dirmap_desc for reads/writes.
0373  * @priv:       pointer to the private data
0374  */
0375 struct spi_nor {
0376     struct mtd_info     mtd;
0377     struct mutex        lock;
0378     struct device       *dev;
0379     struct spi_mem      *spimem;
0380     u8          *bouncebuf;
0381     size_t          bouncebuf_size;
0382     const struct flash_info *info;
0383     const struct spi_nor_manufacturer *manufacturer;
0384     u8          addr_nbytes;
0385     u8          erase_opcode;
0386     u8          read_opcode;
0387     u8          read_dummy;
0388     u8          program_opcode;
0389     enum spi_nor_protocol   read_proto;
0390     enum spi_nor_protocol   write_proto;
0391     enum spi_nor_protocol   reg_proto;
0392     bool            sst_write_second;
0393     u32         flags;
0394     enum spi_nor_cmd_ext    cmd_ext_type;
0395     struct sfdp     *sfdp;
0396     struct dentry       *debugfs_root;
0397
0398     const struct spi_nor_controller_ops *controller_ops;
0399
0400     struct spi_nor_flash_parameter *params;
0401
0402     struct {
0403         struct spi_mem_dirmap_desc *rdesc;
0404         struct spi_mem_dirmap_desc *wdesc;
0405     } dirmap;
0406
0407     void *priv;
0408 };
0409
0410 static inline void spi_nor_set_flash_node(struct spi_nor *nor,
0411                       struct device_node *np)
0412 {
0413     mtd_set_of_node(&nor->mtd, np);
0414 }
0415
0416 static inline struct device_node *spi_nor_get_flash_node(struct spi_nor *nor)
0417 {
0418     return mtd_get_of_node(&nor->mtd);
0419 }
0420
0421 /**
0422  * spi_nor_scan() - scan the SPI NOR
0423  * @nor:    the spi_nor structure
0424  * @name:   the chip type name
0425  * @hwcaps: the hardware capabilities supported by the controller driver
0426  *
0427  * The drivers can use this function to scan the SPI NOR.
0428  * In the scanning, it will try to get all the necessary information to
0429  * fill the mtd_info{} and the spi_nor{}.
0430  *
0431  * The chip type name can be provided through the @name parameter.
0432  *
0433  * Return: 0 for success, others for failure.
0434  */
0435 int spi_nor_scan(struct spi_nor *nor, const char *name,
0436          const struct spi_nor_hwcaps *hwcaps);
0437
0438 /**
0439  * spi_nor_restore_addr_mode() - restore the status of SPI NOR
0440  * @nor:    the spi_nor structure
0441  */
0442 void spi_nor_restore(struct spi_nor *nor);
0443
0444 #endif