linux/mtd/pfow.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /* Primary function overlay window definitions
0003  * and service functions used by LPDDR chips
0004  */
0005 #ifndef __LINUX_MTD_PFOW_H
0006 #define __LINUX_MTD_PFOW_H
0007
0008 #include <linux/mtd/qinfo.h>
0009
0010 /* PFOW registers addressing */
0011 /* Address of symbol "P" */
0012 #define PFOW_QUERY_STRING_P         0x0000
0013 /* Address of symbol "F" */
0014 #define PFOW_QUERY_STRING_F         0x0002
0015 /* Address of symbol "O" */
0016 #define PFOW_QUERY_STRING_O         0x0004
0017 /* Address of symbol "W" */
0018 #define PFOW_QUERY_STRING_W         0x0006
0019 /* Identification info for LPDDR chip */
0020 #define PFOW_MANUFACTURER_ID            0x0020
0021 #define PFOW_DEVICE_ID              0x0022
0022 /* Address in PFOW where prog buffer can be found */
0023 #define PFOW_PROGRAM_BUFFER_OFFSET      0x0040
0024 /* Size of program buffer in words */
0025 #define PFOW_PROGRAM_BUFFER_SIZE        0x0042
0026 /* Address command code register */
0027 #define PFOW_COMMAND_CODE           0x0080
0028 /* command data register */
0029 #define PFOW_COMMAND_DATA           0x0084
0030 /* command address register lower address bits */
0031 #define PFOW_COMMAND_ADDRESS_L          0x0088
0032 /* command address register upper address bits */
0033 #define PFOW_COMMAND_ADDRESS_H          0x008a
0034 /* number of bytes to be proggrammed lower address bits */
0035 #define PFOW_DATA_COUNT_L           0x0090
0036 /* number of bytes to be proggrammed higher address bits */
0037 #define PFOW_DATA_COUNT_H           0x0092
0038 /* command execution register, the only possible value is 0x01 */
0039 #define PFOW_COMMAND_EXECUTE            0x00c0
0040 /* 0x01 should be written at this address to clear buffer */
0041 #define PFOW_CLEAR_PROGRAM_BUFFER       0x00c4
0042 /* device program/erase suspend register */
0043 #define PFOW_PROGRAM_ERASE_SUSPEND      0x00c8
0044 /* device status register */
0045 #define PFOW_DSR                0x00cc
0046
0047 /* LPDDR memory device command codes */
0048 /* They are possible values of PFOW command code register */
0049 #define LPDDR_WORD_PROGRAM      0x0041
0050 #define LPDDR_BUFF_PROGRAM      0x00E9
0051 #define LPDDR_BLOCK_ERASE       0x0020
0052 #define LPDDR_LOCK_BLOCK        0x0061
0053 #define LPDDR_UNLOCK_BLOCK      0x0062
0054 #define LPDDR_READ_BLOCK_LOCK_STATUS    0x0065
0055 #define LPDDR_INFO_QUERY        0x0098
0056 #define LPDDR_READ_OTP          0x0097
0057 #define LPDDR_PROG_OTP          0x00C0
0058 #define LPDDR_RESUME            0x00D0
0059
0060 /* Defines possible value of PFOW command execution register */
0061 #define LPDDR_START_EXECUTION           0x0001
0062
0063 /* Defines possible value of PFOW program/erase suspend register */
0064 #define LPDDR_SUSPEND               0x0001
0065
0066 /* Possible values of PFOW device status register */
0067 /* access R - read; RC read & clearable */
0068 #define DSR_DPS         (1<<1) /* RC; device protect status
0069                     * 0 - not protected 1 - locked */
0070 #define DSR_PSS         (1<<2) /* R; program suspend status;
0071                     * 0-prog in progress/completed,
0072                     * 1- prog suspended */
0073 #define DSR_VPPS        (1<<3) /* RC; 0-Vpp OK, * 1-Vpp low */
0074 #define DSR_PROGRAM_STATUS  (1<<4) /* RC; 0-successful, 1-error */
0075 #define DSR_ERASE_STATUS    (1<<5) /* RC; erase or blank check status;
0076                     * 0-success erase/blank check,
0077                     * 1 blank check error */
0078 #define DSR_ESS         (1<<6) /* R; erase suspend status;
0079                     * 0-erase in progress/complete,
0080                     * 1 erase suspended */
0081 #define DSR_READY_STATUS    (1<<7) /* R; Device status
0082                     * 0-busy,
0083                     * 1-ready */
0084 #define DSR_RPS         (0x3<<8) /* RC;  region program status
0085                     * 00 - Success,
0086                     * 01-re-program attempt in region with
0087                     * object mode data,
0088                     * 10-object mode program w attempt in
0089                     * region with control mode data
0090                     * 11-attempt to program invalid half
0091                     * with 0x41 command */
0092 #define DSR_AOS         (1<<12) /* RC; 1- AO related failure */
0093 #define DSR_AVAILABLE       (1<<15) /* R; Device availbility
0094                     * 1 - Device available
0095                     * 0 - not available */
0096
0097 /* The superset of all possible error bits in DSR */
0098 #define DSR_ERR         0x133A
0099
0100 static inline void send_pfow_command(struct map_info *map,
0101                 unsigned long cmd_code, unsigned long adr,
0102                 unsigned long len, map_word *datum)
0103 {
0104     int bits_per_chip = map_bankwidth(map) * 8;
0105
0106     map_write(map, CMD(cmd_code), map->pfow_base + PFOW_COMMAND_CODE);
0107     map_write(map, CMD(adr & ((1<<bits_per_chip) - 1)),
0108                 map->pfow_base + PFOW_COMMAND_ADDRESS_L);
0109     map_write(map, CMD(adr>>bits_per_chip),
0110                 map->pfow_base + PFOW_COMMAND_ADDRESS_H);
0111     if (len) {
0112         map_write(map, CMD(len & ((1<<bits_per_chip) - 1)),
0113                     map->pfow_base + PFOW_DATA_COUNT_L);
0114         map_write(map, CMD(len>>bits_per_chip),
0115                     map->pfow_base + PFOW_DATA_COUNT_H);
0116     }
0117     if (datum)
0118         map_write(map, *datum, map->pfow_base + PFOW_COMMAND_DATA);
0119
0120     /* Command execution start */
0121     map_write(map, CMD(LPDDR_START_EXECUTION),
0122             map->pfow_base + PFOW_COMMAND_EXECUTE);
0123 }
0124 #endif /* __LINUX_MTD_PFOW_H */