linux/mtd/ndfc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  Copyright (c) 2006 Thomas Gleixner <tglx@linutronix.de>
0004  *
0005  *  Info:
0006  *   Contains defines, datastructures for ndfc nand controller
0007  */
0008 #ifndef __LINUX_MTD_NDFC_H
0009 #define __LINUX_MTD_NDFC_H
0010
0011 /* NDFC Register definitions */
0012 #define NDFC_CMD        0x00
0013 #define NDFC_ALE        0x04
0014 #define NDFC_DATA       0x08
0015 #define NDFC_ECC        0x10
0016 #define NDFC_BCFG0      0x30
0017 #define NDFC_BCFG1      0x34
0018 #define NDFC_BCFG2      0x38
0019 #define NDFC_BCFG3      0x3c
0020 #define NDFC_CCR        0x40
0021 #define NDFC_STAT       0x44
0022 #define NDFC_HWCTL      0x48
0023 #define NDFC_REVID      0x50
0024
0025 #define NDFC_STAT_IS_READY  0x01000000
0026
0027 #define NDFC_CCR_RESET_CE   0x80000000 /* CE Reset */
0028 #define NDFC_CCR_RESET_ECC  0x40000000 /* ECC Reset */
0029 #define NDFC_CCR_RIE        0x20000000 /* Interrupt Enable on Device Rdy */
0030 #define NDFC_CCR_REN        0x10000000 /* Enable wait for Rdy in LinearR */
0031 #define NDFC_CCR_ROMEN      0x08000000 /* Enable ROM In LinearR */
0032 #define NDFC_CCR_ARE        0x04000000 /* Auto-Read Enable */
0033 #define NDFC_CCR_BS(x)      (((x) & 0x3) << 24) /* Select Bank on CE[x] */
0034 #define NDFC_CCR_BS_MASK    0x03000000 /* Select Bank */
0035 #define NDFC_CCR_ARAC0      0x00000000 /* 3 Addr, 1 Col 2 Row 512b page */
0036 #define NDFC_CCR_ARAC1      0x00001000 /* 4 Addr, 1 Col 3 Row 512b page */
0037 #define NDFC_CCR_ARAC2      0x00002000 /* 4 Addr, 2 Col 2 Row 2K page */
0038 #define NDFC_CCR_ARAC3      0x00003000 /* 5 Addr, 2 Col 3 Row 2K page */
0039 #define NDFC_CCR_ARAC_MASK  0x00003000 /* Auto-Read mode Addr Cycles */
0040 #define NDFC_CCR_RPG        0x0000C000 /* Auto-Read Page */
0041 #define NDFC_CCR_EBCC       0x00000004 /* EBC Configuration Completed */
0042 #define NDFC_CCR_DHC        0x00000002 /* Direct Hardware Control Enable */
0043
0044 #define NDFC_BxCFG_EN       0x80000000 /* Bank Enable */
0045 #define NDFC_BxCFG_CED      0x40000000 /* nCE Style */
0046 #define NDFC_BxCFG_SZ_MASK  0x08000000 /* Bank Size */
0047 #define NDFC_BxCFG_SZ_8BIT  0x00000000 /* 8bit */
0048 #define NDFC_BxCFG_SZ_16BIT 0x08000000 /* 16bit */
0049
0050 #define NDFC_MAX_BANKS      4
0051
0052 struct ndfc_controller_settings {
0053     uint32_t    ccr_settings;
0054     uint64_t    ndfc_erpn;
0055 };
0056
0057 struct ndfc_chip_settings {
0058     uint32_t    bank_settings;
0059 };
0060
0061 #endif