linux/mtd/nand-ecc-mtk.h

0001 /* SPDX-License-Identifier: GPL-2.0 OR MIT */
0002 /*
0003  * MTK SDG1 ECC controller
0004  *
0005  * Copyright (c) 2016 Mediatek
0006  * Authors: Xiaolei Li      <xiaolei.li@mediatek.com>
0007  *      Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
0008  */
0009
0010 #ifndef __DRIVERS_MTD_NAND_MTK_ECC_H__
0011 #define __DRIVERS_MTD_NAND_MTK_ECC_H__
0012
0013 #include <linux/types.h>
0014
0015 enum mtk_ecc_mode {ECC_DMA_MODE = 0, ECC_NFI_MODE = 1};
0016 enum mtk_ecc_operation {ECC_ENCODE, ECC_DECODE};
0017
0018 struct device_node;
0019 struct mtk_ecc;
0020
0021 struct mtk_ecc_stats {
0022     u32 corrected;
0023     u32 bitflips;
0024     u32 failed;
0025 };
0026
0027 struct mtk_ecc_config {
0028     enum mtk_ecc_operation op;
0029     enum mtk_ecc_mode mode;
0030     dma_addr_t addr;
0031     u32 strength;
0032     u32 sectors;
0033     u32 len;
0034 };
0035
0036 int mtk_ecc_encode(struct mtk_ecc *, struct mtk_ecc_config *, u8 *, u32);
0037 void mtk_ecc_get_stats(struct mtk_ecc *, struct mtk_ecc_stats *, int);
0038 int mtk_ecc_wait_done(struct mtk_ecc *, enum mtk_ecc_operation);
0039 int mtk_ecc_enable(struct mtk_ecc *, struct mtk_ecc_config *);
0040 void mtk_ecc_disable(struct mtk_ecc *);
0041 void mtk_ecc_adjust_strength(struct mtk_ecc *ecc, u32 *p);
0042 unsigned int mtk_ecc_get_parity_bits(struct mtk_ecc *ecc);
0043
0044 struct mtk_ecc *of_mtk_ecc_get(struct device_node *);
0045 void mtk_ecc_release(struct mtk_ecc *);
0046
0047 #endif