linux/mmc/sdio.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  *  include/linux/mmc/sdio.h
0004  *
0005  *  Copyright 2006-2007 Pierre Ossman
0006  */
0007
0008 #ifndef LINUX_MMC_SDIO_H
0009 #define LINUX_MMC_SDIO_H
0010
0011 /* SDIO commands                         type  argument     response */
0012 #define SD_IO_SEND_OP_COND          5 /* bcr  [23:0] OCR         R4  */
0013 #define SD_IO_RW_DIRECT            52 /* ac   [31:0] See below   R5  */
0014 #define SD_IO_RW_EXTENDED          53 /* adtc [31:0] See below   R5  */
0015
0016 /*
0017  * SD_IO_RW_DIRECT argument format:
0018  *
0019  *      [31] R/W flag
0020  *      [30:28] Function number
0021  *      [27] RAW flag
0022  *      [25:9] Register address
0023  *      [7:0] Data
0024  */
0025
0026 /*
0027  * SD_IO_RW_EXTENDED argument format:
0028  *
0029  *      [31] R/W flag
0030  *      [30:28] Function number
0031  *      [27] Block mode
0032  *      [26] Increment address
0033  *      [25:9] Register address
0034  *      [8:0] Byte/block count
0035  */
0036
0037 #define R4_18V_PRESENT (1<<24)
0038 #define R4_MEMORY_PRESENT (1 << 27)
0039
0040 /*
0041   SDIO status in R5
0042   Type
0043     e : error bit
0044     s : status bit
0045     r : detected and set for the actual command response
0046     x : detected and set during command execution. the host must poll
0047             the card by sending status command in order to read these bits.
0048   Clear condition
0049     a : according to the card state
0050     b : always related to the previous command. Reception of
0051             a valid command will clear it (with a delay of one command)
0052     c : clear by read
0053  */
0054
0055 #define R5_COM_CRC_ERROR    (1 << 15)   /* er, b */
0056 #define R5_ILLEGAL_COMMAND  (1 << 14)   /* er, b */
0057 #define R5_ERROR        (1 << 11)   /* erx, c */
0058 #define R5_FUNCTION_NUMBER  (1 << 9)    /* er, c */
0059 #define R5_OUT_OF_RANGE     (1 << 8)    /* er, c */
0060 #define R5_STATUS(x)        (x & 0xCB00)
0061 #define R5_IO_CURRENT_STATE(x)  ((x & 0x3000) >> 12) /* s, b */
0062
0063 /*
0064  * Card Common Control Registers (CCCR)
0065  */
0066
0067 #define SDIO_CCCR_CCCR      0x00
0068
0069 #define  SDIO_CCCR_REV_1_00 0   /* CCCR/FBR Version 1.00 */
0070 #define  SDIO_CCCR_REV_1_10 1   /* CCCR/FBR Version 1.10 */
0071 #define  SDIO_CCCR_REV_1_20 2   /* CCCR/FBR Version 1.20 */
0072 #define  SDIO_CCCR_REV_3_00 3   /* CCCR/FBR Version 3.00 */
0073
0074 #define  SDIO_SDIO_REV_1_00 0   /* SDIO Spec Version 1.00 */
0075 #define  SDIO_SDIO_REV_1_10 1   /* SDIO Spec Version 1.10 */
0076 #define  SDIO_SDIO_REV_1_20 2   /* SDIO Spec Version 1.20 */
0077 #define  SDIO_SDIO_REV_2_00 3   /* SDIO Spec Version 2.00 */
0078 #define  SDIO_SDIO_REV_3_00 4   /* SDIO Spec Version 3.00 */
0079
0080 #define SDIO_CCCR_SD        0x01
0081
0082 #define  SDIO_SD_REV_1_01   0   /* SD Physical Spec Version 1.01 */
0083 #define  SDIO_SD_REV_1_10   1   /* SD Physical Spec Version 1.10 */
0084 #define  SDIO_SD_REV_2_00   2   /* SD Physical Spec Version 2.00 */
0085 #define  SDIO_SD_REV_3_00   3   /* SD Physical Spec Version 3.00 */
0086
0087 #define SDIO_CCCR_IOEx      0x02
0088 #define SDIO_CCCR_IORx      0x03
0089
0090 #define SDIO_CCCR_IENx      0x04    /* Function/Master Interrupt Enable */
0091 #define SDIO_CCCR_INTx      0x05    /* Function Interrupt Pending */
0092
0093 #define SDIO_CCCR_ABORT     0x06    /* function abort/card reset */
0094
0095 #define SDIO_CCCR_IF        0x07    /* bus interface controls */
0096
0097 #define  SDIO_BUS_WIDTH_MASK    0x03    /* data bus width setting */
0098 #define  SDIO_BUS_WIDTH_1BIT    0x00
0099 #define  SDIO_BUS_WIDTH_RESERVED 0x01
0100 #define  SDIO_BUS_WIDTH_4BIT    0x02
0101 #define  SDIO_BUS_ECSI      0x20    /* Enable continuous SPI interrupt */
0102 #define  SDIO_BUS_SCSI      0x40    /* Support continuous SPI interrupt */
0103
0104 #define  SDIO_BUS_ASYNC_INT 0x20
0105
0106 #define  SDIO_BUS_CD_DISABLE     0x80   /* disable pull-up on DAT3 (pin 1) */
0107
0108 #define SDIO_CCCR_CAPS      0x08
0109
0110 #define  SDIO_CCCR_CAP_SDC  0x01    /* can do CMD52 while data transfer */
0111 #define  SDIO_CCCR_CAP_SMB  0x02    /* can do multi-block xfers (CMD53) */
0112 #define  SDIO_CCCR_CAP_SRW  0x04    /* supports read-wait protocol */
0113 #define  SDIO_CCCR_CAP_SBS  0x08    /* supports suspend/resume */
0114 #define  SDIO_CCCR_CAP_S4MI 0x10    /* interrupt during 4-bit CMD53 */
0115 #define  SDIO_CCCR_CAP_E4MI 0x20    /* enable ints during 4-bit CMD53 */
0116 #define  SDIO_CCCR_CAP_LSC  0x40    /* low speed card */
0117 #define  SDIO_CCCR_CAP_4BLS 0x80    /* 4 bit low speed card */
0118
0119 #define SDIO_CCCR_CIS       0x09    /* common CIS pointer (3 bytes) */
0120
0121 /* Following 4 regs are valid only if SBS is set */
0122 #define SDIO_CCCR_SUSPEND   0x0c
0123 #define SDIO_CCCR_SELx      0x0d
0124 #define SDIO_CCCR_EXECx     0x0e
0125 #define SDIO_CCCR_READYx    0x0f
0126
0127 #define SDIO_CCCR_BLKSIZE   0x10
0128
0129 #define SDIO_CCCR_POWER     0x12
0130
0131 #define  SDIO_POWER_SMPC    0x01    /* Supports Master Power Control */
0132 #define  SDIO_POWER_EMPC    0x02    /* Enable Master Power Control */
0133
0134 #define SDIO_CCCR_SPEED     0x13
0135
0136 #define  SDIO_SPEED_SHS     0x01    /* Supports High-Speed mode */
0137 #define  SDIO_SPEED_BSS_SHIFT   1
0138 #define  SDIO_SPEED_BSS_MASK    (7<<SDIO_SPEED_BSS_SHIFT)
0139 #define  SDIO_SPEED_SDR12   (0<<SDIO_SPEED_BSS_SHIFT)
0140 #define  SDIO_SPEED_SDR25   (1<<SDIO_SPEED_BSS_SHIFT)
0141 #define  SDIO_SPEED_SDR50   (2<<SDIO_SPEED_BSS_SHIFT)
0142 #define  SDIO_SPEED_SDR104  (3<<SDIO_SPEED_BSS_SHIFT)
0143 #define  SDIO_SPEED_DDR50   (4<<SDIO_SPEED_BSS_SHIFT)
0144 #define  SDIO_SPEED_EHS     SDIO_SPEED_SDR25    /* Enable High-Speed */
0145
0146 #define SDIO_CCCR_UHS       0x14
0147 #define  SDIO_UHS_SDR50     0x01
0148 #define  SDIO_UHS_SDR104    0x02
0149 #define  SDIO_UHS_DDR50     0x04
0150
0151 #define SDIO_CCCR_DRIVE_STRENGTH 0x15
0152 #define  SDIO_SDTx_MASK     0x07
0153 #define  SDIO_DRIVE_SDTA    (1<<0)
0154 #define  SDIO_DRIVE_SDTC    (1<<1)
0155 #define  SDIO_DRIVE_SDTD    (1<<2)
0156 #define  SDIO_DRIVE_DTSx_MASK   0x03
0157 #define  SDIO_DRIVE_DTSx_SHIFT  4
0158 #define  SDIO_DTSx_SET_TYPE_B   (0 << SDIO_DRIVE_DTSx_SHIFT)
0159 #define  SDIO_DTSx_SET_TYPE_A   (1 << SDIO_DRIVE_DTSx_SHIFT)
0160 #define  SDIO_DTSx_SET_TYPE_C   (2 << SDIO_DRIVE_DTSx_SHIFT)
0161 #define  SDIO_DTSx_SET_TYPE_D   (3 << SDIO_DRIVE_DTSx_SHIFT)
0162
0163 #define SDIO_CCCR_INTERRUPT_EXT 0x16
0164 #define SDIO_INTERRUPT_EXT_SAI  (1 << 0)
0165 #define SDIO_INTERRUPT_EXT_EAI  (1 << 1)
0166
0167 /*
0168  * Function Basic Registers (FBR)
0169  */
0170
0171 #define SDIO_FBR_BASE(f)    ((f) * 0x100) /* base of function f's FBRs */
0172
0173 #define SDIO_FBR_STD_IF     0x00
0174
0175 #define  SDIO_FBR_SUPPORTS_CSA  0x40    /* supports Code Storage Area */
0176 #define  SDIO_FBR_ENABLE_CSA    0x80    /* enable Code Storage Area */
0177
0178 #define SDIO_FBR_STD_IF_EXT 0x01
0179
0180 #define SDIO_FBR_POWER      0x02
0181
0182 #define  SDIO_FBR_POWER_SPS 0x01    /* Supports Power Selection */
0183 #define  SDIO_FBR_POWER_EPS 0x02    /* Enable (low) Power Selection */
0184
0185 #define SDIO_FBR_CIS        0x09    /* CIS pointer (3 bytes) */
0186
0187
0188 #define SDIO_FBR_CSA        0x0C    /* CSA pointer (3 bytes) */
0189
0190 #define SDIO_FBR_CSA_DATA   0x0F
0191
0192 #define SDIO_FBR_BLKSIZE    0x10    /* block size (2 bytes) */
0193
0194 #endif /* LINUX_MMC_SDIO_H */