linux/mlx5/qp.h

0001 /*
0002  * Copyright (c) 2013-2015, Mellanox Technologies. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032
0033 #ifndef MLX5_QP_H
0034 #define MLX5_QP_H
0035
0036 #include <linux/mlx5/device.h>
0037 #include <linux/mlx5/driver.h>
0038
0039 #define MLX5_INVALID_LKEY   0x100
0040 /* UMR (3 WQE_BB's) + SIG (3 WQE_BB's) + PSV (mem) + PSV (wire) */
0041 #define MLX5_SIG_WQE_SIZE   (MLX5_SEND_WQE_BB * 8)
0042 #define MLX5_DIF_SIZE       8
0043 #define MLX5_STRIDE_BLOCK_OP    0x400
0044 #define MLX5_CPY_GRD_MASK   0xc0
0045 #define MLX5_CPY_APP_MASK   0x30
0046 #define MLX5_CPY_REF_MASK   0x0f
0047 #define MLX5_BSF_INC_REFTAG (1 << 6)
0048 #define MLX5_BSF_INL_VALID  (1 << 15)
0049 #define MLX5_BSF_REFRESH_DIF    (1 << 14)
0050 #define MLX5_BSF_REPEAT_BLOCK   (1 << 7)
0051 #define MLX5_BSF_APPTAG_ESCAPE  0x1
0052 #define MLX5_BSF_APPREF_ESCAPE  0x2
0053
0054 enum mlx5_qp_optpar {
0055     MLX5_QP_OPTPAR_ALT_ADDR_PATH        = 1 << 0,
0056     MLX5_QP_OPTPAR_RRE          = 1 << 1,
0057     MLX5_QP_OPTPAR_RAE          = 1 << 2,
0058     MLX5_QP_OPTPAR_RWE          = 1 << 3,
0059     MLX5_QP_OPTPAR_PKEY_INDEX       = 1 << 4,
0060     MLX5_QP_OPTPAR_Q_KEY            = 1 << 5,
0061     MLX5_QP_OPTPAR_RNR_TIMEOUT      = 1 << 6,
0062     MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH    = 1 << 7,
0063     MLX5_QP_OPTPAR_SRA_MAX          = 1 << 8,
0064     MLX5_QP_OPTPAR_RRA_MAX          = 1 << 9,
0065     MLX5_QP_OPTPAR_PM_STATE         = 1 << 10,
0066     MLX5_QP_OPTPAR_RETRY_COUNT      = 1 << 12,
0067     MLX5_QP_OPTPAR_RNR_RETRY        = 1 << 13,
0068     MLX5_QP_OPTPAR_ACK_TIMEOUT      = 1 << 14,
0069     MLX5_QP_OPTPAR_LAG_TX_AFF       = 1 << 15,
0070     MLX5_QP_OPTPAR_PRI_PORT         = 1 << 16,
0071     MLX5_QP_OPTPAR_SRQN         = 1 << 18,
0072     MLX5_QP_OPTPAR_CQN_RCV          = 1 << 19,
0073     MLX5_QP_OPTPAR_DC_HS            = 1 << 20,
0074     MLX5_QP_OPTPAR_DC_KEY           = 1 << 21,
0075     MLX5_QP_OPTPAR_COUNTER_SET_ID       = 1 << 25,
0076 };
0077
0078 enum mlx5_qp_state {
0079     MLX5_QP_STATE_RST           = 0,
0080     MLX5_QP_STATE_INIT          = 1,
0081     MLX5_QP_STATE_RTR           = 2,
0082     MLX5_QP_STATE_RTS           = 3,
0083     MLX5_QP_STATE_SQER          = 4,
0084     MLX5_QP_STATE_SQD           = 5,
0085     MLX5_QP_STATE_ERR           = 6,
0086     MLX5_QP_STATE_SQ_DRAINING       = 7,
0087     MLX5_QP_STATE_SUSPENDED         = 9,
0088     MLX5_QP_NUM_STATE,
0089     MLX5_QP_STATE,
0090     MLX5_QP_STATE_BAD,
0091 };
0092
0093 enum {
0094     MLX5_SQ_STATE_NA    = MLX5_SQC_STATE_ERR + 1,
0095     MLX5_SQ_NUM_STATE   = MLX5_SQ_STATE_NA + 1,
0096     MLX5_RQ_STATE_NA    = MLX5_RQC_STATE_ERR + 1,
0097     MLX5_RQ_NUM_STATE   = MLX5_RQ_STATE_NA + 1,
0098 };
0099
0100 enum {
0101     MLX5_QP_ST_RC               = 0x0,
0102     MLX5_QP_ST_UC               = 0x1,
0103     MLX5_QP_ST_UD               = 0x2,
0104     MLX5_QP_ST_XRC              = 0x3,
0105     MLX5_QP_ST_MLX              = 0x4,
0106     MLX5_QP_ST_DCI              = 0x5,
0107     MLX5_QP_ST_DCT              = 0x6,
0108     MLX5_QP_ST_QP0              = 0x7,
0109     MLX5_QP_ST_QP1              = 0x8,
0110     MLX5_QP_ST_RAW_ETHERTYPE        = 0x9,
0111     MLX5_QP_ST_RAW_IPV6         = 0xa,
0112     MLX5_QP_ST_SNIFFER          = 0xb,
0113     MLX5_QP_ST_SYNC_UMR         = 0xe,
0114     MLX5_QP_ST_PTP_1588         = 0xd,
0115     MLX5_QP_ST_REG_UMR          = 0xc,
0116     MLX5_QP_ST_MAX
0117 };
0118
0119 enum {
0120     MLX5_QP_PM_MIGRATED         = 0x3,
0121     MLX5_QP_PM_ARMED            = 0x0,
0122     MLX5_QP_PM_REARM            = 0x1
0123 };
0124
0125 enum {
0126     MLX5_NON_ZERO_RQ    = 0x0,
0127     MLX5_SRQ_RQ     = 0x1,
0128     MLX5_CRQ_RQ     = 0x2,
0129     MLX5_ZERO_LEN_RQ    = 0x3
0130 };
0131
0132 /* TODO REM */
0133 enum {
0134     /* params1 */
0135     MLX5_QP_BIT_SRE             = 1 << 15,
0136     MLX5_QP_BIT_SWE             = 1 << 14,
0137     MLX5_QP_BIT_SAE             = 1 << 13,
0138     /* params2 */
0139     MLX5_QP_BIT_RRE             = 1 << 15,
0140     MLX5_QP_BIT_RWE             = 1 << 14,
0141     MLX5_QP_BIT_RAE             = 1 << 13,
0142     MLX5_QP_BIT_RIC             = 1 <<  4,
0143     MLX5_QP_BIT_CC_SLAVE_RECV       = 1 <<  2,
0144     MLX5_QP_BIT_CC_SLAVE_SEND       = 1 <<  1,
0145     MLX5_QP_BIT_CC_MASTER           = 1 <<  0
0146 };
0147
0148 enum {
0149     MLX5_WQE_CTRL_CQ_UPDATE     = 2 << 2,
0150     MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2,
0151     MLX5_WQE_CTRL_SOLICITED     = 1 << 1,
0152 };
0153
0154 enum {
0155     MLX5_SEND_WQE_DS    = 16,
0156     MLX5_SEND_WQE_BB    = 64,
0157 };
0158
0159 #define MLX5_SEND_WQEBB_NUM_DS  (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS)
0160
0161 enum {
0162     MLX5_SEND_WQE_MAX_WQEBBS    = 16,
0163 };
0164
0165 enum {
0166     MLX5_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
0167     MLX5_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
0168     MLX5_WQE_FMR_PERM_REMOTE_READ   = 1 << 29,
0169     MLX5_WQE_FMR_PERM_REMOTE_WRITE  = 1 << 30,
0170     MLX5_WQE_FMR_PERM_ATOMIC    = 1 << 31
0171 };
0172
0173 enum {
0174     MLX5_FENCE_MODE_NONE            = 0 << 5,
0175     MLX5_FENCE_MODE_INITIATOR_SMALL     = 1 << 5,
0176     MLX5_FENCE_MODE_FENCE           = 2 << 5,
0177     MLX5_FENCE_MODE_STRONG_ORDERING     = 3 << 5,
0178     MLX5_FENCE_MODE_SMALL_AND_FENCE     = 4 << 5,
0179 };
0180
0181 enum {
0182     MLX5_RCV_DBR    = 0,
0183     MLX5_SND_DBR    = 1,
0184 };
0185
0186 enum {
0187     MLX5_FLAGS_INLINE   = 1<<7,
0188     MLX5_FLAGS_CHECK_FREE   = 1<<5,
0189 };
0190
0191 struct mlx5_wqe_fmr_seg {
0192     __be32          flags;
0193     __be32          mem_key;
0194     __be64          buf_list;
0195     __be64          start_addr;
0196     __be64          reg_len;
0197     __be32          offset;
0198     __be32          page_size;
0199     u32         reserved[2];
0200 };
0201
0202 struct mlx5_wqe_ctrl_seg {
0203     __be32          opmod_idx_opcode;
0204     __be32          qpn_ds;
0205
0206     struct_group(trailer,
0207
0208     u8          signature;
0209     u8          rsvd[2];
0210     u8          fm_ce_se;
0211     union {
0212         __be32      general_id;
0213         __be32      imm;
0214         __be32      umr_mkey;
0215         __be32      tis_tir_num;
0216     };
0217
0218     ); /* end of trailer group */
0219 };
0220
0221 #define MLX5_WQE_CTRL_DS_MASK 0x3f
0222 #define MLX5_WQE_CTRL_QPN_MASK 0xffffff00
0223 #define MLX5_WQE_CTRL_QPN_SHIFT 8
0224 #define MLX5_WQE_DS_UNITS 16
0225 #define MLX5_WQE_CTRL_OPCODE_MASK 0xff
0226 #define MLX5_WQE_CTRL_WQE_INDEX_MASK 0x00ffff00
0227 #define MLX5_WQE_CTRL_WQE_INDEX_SHIFT 8
0228
0229 enum {
0230     MLX5_ETH_WQE_L3_INNER_CSUM      = 1 << 4,
0231     MLX5_ETH_WQE_L4_INNER_CSUM      = 1 << 5,
0232     MLX5_ETH_WQE_L3_CSUM            = 1 << 6,
0233     MLX5_ETH_WQE_L4_CSUM            = 1 << 7,
0234 };
0235
0236 enum {
0237     MLX5_ETH_WQE_SVLAN              = 1 << 0,
0238     MLX5_ETH_WQE_TRAILER_HDR_OUTER_IP_ASSOC = 1 << 26,
0239     MLX5_ETH_WQE_TRAILER_HDR_OUTER_L4_ASSOC = 1 << 27,
0240     MLX5_ETH_WQE_TRAILER_HDR_INNER_IP_ASSOC = 3 << 26,
0241     MLX5_ETH_WQE_TRAILER_HDR_INNER_L4_ASSOC = 1 << 28,
0242     MLX5_ETH_WQE_INSERT_TRAILER     = 1 << 30,
0243     MLX5_ETH_WQE_INSERT_VLAN        = 1 << 15,
0244 };
0245
0246 enum {
0247     MLX5_ETH_WQE_SWP_INNER_L3_IPV6  = 1 << 0,
0248     MLX5_ETH_WQE_SWP_INNER_L4_UDP   = 1 << 1,
0249     MLX5_ETH_WQE_SWP_OUTER_L3_IPV6  = 1 << 4,
0250     MLX5_ETH_WQE_SWP_OUTER_L4_UDP   = 1 << 5,
0251 };
0252
0253 enum {
0254     MLX5_ETH_WQE_FT_META_IPSEC = BIT(0),
0255 };
0256
0257 struct mlx5_wqe_eth_seg {
0258     u8              swp_outer_l4_offset;
0259     u8              swp_outer_l3_offset;
0260     u8              swp_inner_l4_offset;
0261     u8              swp_inner_l3_offset;
0262     u8              cs_flags;
0263     u8              swp_flags;
0264     __be16          mss;
0265     __be32          flow_table_metadata;
0266     union {
0267         struct {
0268             __be16 sz;
0269             u8     start[2];
0270         } inline_hdr;
0271         struct {
0272             __be16 type;
0273             __be16 vlan_tci;
0274         } insert;
0275         __be32 trailer;
0276     };
0277 };
0278
0279 struct mlx5_wqe_xrc_seg {
0280     __be32          xrc_srqn;
0281     u8          rsvd[12];
0282 };
0283
0284 struct mlx5_wqe_masked_atomic_seg {
0285     __be64          swap_add;
0286     __be64          compare;
0287     __be64          swap_add_mask;
0288     __be64          compare_mask;
0289 };
0290
0291 struct mlx5_base_av {
0292     union {
0293         struct {
0294             __be32  qkey;
0295             __be32  reserved;
0296         } qkey;
0297         __be64  dc_key;
0298     } key;
0299     __be32  dqp_dct;
0300     u8  stat_rate_sl;
0301     u8  fl_mlid;
0302     union {
0303         __be16  rlid;
0304         __be16  udp_sport;
0305     };
0306 };
0307
0308 struct mlx5_av {
0309     union {
0310         struct {
0311             __be32  qkey;
0312             __be32  reserved;
0313         } qkey;
0314         __be64  dc_key;
0315     } key;
0316     __be32  dqp_dct;
0317     u8  stat_rate_sl;
0318     u8  fl_mlid;
0319     union {
0320         __be16  rlid;
0321         __be16  udp_sport;
0322     };
0323     u8  reserved0[4];
0324     u8  rmac[6];
0325     u8  tclass;
0326     u8  hop_limit;
0327     __be32  grh_gid_fl;
0328     u8  rgid[16];
0329 };
0330
0331 struct mlx5_ib_ah {
0332     struct ib_ah        ibah;
0333     struct mlx5_av      av;
0334     u8          xmit_port;
0335 };
0336
0337 static inline struct mlx5_ib_ah *to_mah(struct ib_ah *ibah)
0338 {
0339     return container_of(ibah, struct mlx5_ib_ah, ibah);
0340 }
0341
0342 struct mlx5_wqe_datagram_seg {
0343     struct mlx5_av  av;
0344 };
0345
0346 struct mlx5_wqe_raddr_seg {
0347     __be64          raddr;
0348     __be32          rkey;
0349     u32         reserved;
0350 };
0351
0352 struct mlx5_wqe_atomic_seg {
0353     __be64          swap_add;
0354     __be64          compare;
0355 };
0356
0357 struct mlx5_wqe_data_seg {
0358     __be32          byte_count;
0359     __be32          lkey;
0360     __be64          addr;
0361 };
0362
0363 struct mlx5_wqe_umr_ctrl_seg {
0364     u8      flags;
0365     u8      rsvd0[3];
0366     __be16      xlt_octowords;
0367     union {
0368         __be16  xlt_offset;
0369         __be16  bsf_octowords;
0370     };
0371     __be64      mkey_mask;
0372     __be32      xlt_offset_47_16;
0373     u8      rsvd1[28];
0374 };
0375
0376 struct mlx5_seg_set_psv {
0377     __be32      psv_num;
0378     __be16      syndrome;
0379     __be16      status;
0380     __be32      transient_sig;
0381     __be32      ref_tag;
0382 };
0383
0384 struct mlx5_seg_get_psv {
0385     u8      rsvd[19];
0386     u8      num_psv;
0387     __be32      l_key;
0388     __be64      va;
0389     __be32      psv_index[4];
0390 };
0391
0392 struct mlx5_seg_check_psv {
0393     u8      rsvd0[2];
0394     __be16      err_coalescing_op;
0395     u8      rsvd1[2];
0396     __be16      xport_err_op;
0397     u8      rsvd2[2];
0398     __be16      xport_err_mask;
0399     u8      rsvd3[7];
0400     u8      num_psv;
0401     __be32      l_key;
0402     __be64      va;
0403     __be32      psv_index[4];
0404 };
0405
0406 struct mlx5_rwqe_sig {
0407     u8  rsvd0[4];
0408     u8  signature;
0409     u8  rsvd1[11];
0410 };
0411
0412 struct mlx5_wqe_signature_seg {
0413     u8  rsvd0[4];
0414     u8  signature;
0415     u8  rsvd1[11];
0416 };
0417
0418 #define MLX5_WQE_INLINE_SEG_BYTE_COUNT_MASK 0x3ff
0419
0420 struct mlx5_wqe_inline_seg {
0421     __be32  byte_count;
0422     __be32  data[];
0423 };
0424
0425 enum mlx5_sig_type {
0426     MLX5_DIF_CRC = 0x1,
0427     MLX5_DIF_IPCS = 0x2,
0428 };
0429
0430 struct mlx5_bsf_inl {
0431     __be16      vld_refresh;
0432     __be16      dif_apptag;
0433     __be32      dif_reftag;
0434     u8      sig_type;
0435     u8      rp_inv_seed;
0436     u8      rsvd[3];
0437     u8      dif_inc_ref_guard_check;
0438     __be16      dif_app_bitmask_check;
0439 };
0440
0441 struct mlx5_bsf {
0442     struct mlx5_bsf_basic {
0443         u8      bsf_size_sbs;
0444         u8      check_byte_mask;
0445         union {
0446             u8  copy_byte_mask;
0447             u8  bs_selector;
0448             u8  rsvd_wflags;
0449         } wire;
0450         union {
0451             u8  bs_selector;
0452             u8  rsvd_mflags;
0453         } mem;
0454         __be32      raw_data_size;
0455         __be32      w_bfs_psv;
0456         __be32      m_bfs_psv;
0457     } basic;
0458     struct mlx5_bsf_ext {
0459         __be32      t_init_gen_pro_size;
0460         __be32      rsvd_epi_size;
0461         __be32      w_tfs_psv;
0462         __be32      m_tfs_psv;
0463     } ext;
0464     struct mlx5_bsf_inl w_inl;
0465     struct mlx5_bsf_inl m_inl;
0466 };
0467
0468 struct mlx5_mtt {
0469     __be64      ptag;
0470 };
0471
0472 struct mlx5_klm {
0473     __be32      bcount;
0474     __be32      key;
0475     __be64      va;
0476 };
0477
0478 struct mlx5_stride_block_entry {
0479     __be16      stride;
0480     __be16      bcount;
0481     __be32      key;
0482     __be64      va;
0483 };
0484
0485 struct mlx5_stride_block_ctrl_seg {
0486     __be32      bcount_per_cycle;
0487     __be32      op;
0488     __be32      repeat_count;
0489     u16     rsvd;
0490     __be16      num_entries;
0491 };
0492
0493 struct mlx5_core_qp {
0494     struct mlx5_core_rsc_common common; /* must be first */
0495     void (*event)       (struct mlx5_core_qp *, int);
0496     int         qpn;
0497     struct mlx5_rsc_debug   *dbg;
0498     int         pid;
0499     u16         uid;
0500 };
0501
0502 struct mlx5_core_dct {
0503     struct mlx5_core_qp mqp;
0504     struct completion   drained;
0505 };
0506
0507 int mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
0508 void mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp);
0509
0510 static inline const char *mlx5_qp_type_str(int type)
0511 {
0512     switch (type) {
0513     case MLX5_QP_ST_RC: return "RC";
0514     case MLX5_QP_ST_UC: return "C";
0515     case MLX5_QP_ST_UD: return "UD";
0516     case MLX5_QP_ST_XRC: return "XRC";
0517     case MLX5_QP_ST_MLX: return "MLX";
0518     case MLX5_QP_ST_QP0: return "QP0";
0519     case MLX5_QP_ST_QP1: return "QP1";
0520     case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE";
0521     case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6";
0522     case MLX5_QP_ST_SNIFFER: return "SNIFFER";
0523     case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR";
0524     case MLX5_QP_ST_PTP_1588: return "PTP_1588";
0525     case MLX5_QP_ST_REG_UMR: return "REG_UMR";
0526     default: return "Invalid transport type";
0527     }
0528 }
0529
0530 static inline const char *mlx5_qp_state_str(int state)
0531 {
0532     switch (state) {
0533     case MLX5_QP_STATE_RST:
0534     return "RST";
0535     case MLX5_QP_STATE_INIT:
0536     return "INIT";
0537     case MLX5_QP_STATE_RTR:
0538     return "RTR";
0539     case MLX5_QP_STATE_RTS:
0540     return "RTS";
0541     case MLX5_QP_STATE_SQER:
0542     return "SQER";
0543     case MLX5_QP_STATE_SQD:
0544     return "SQD";
0545     case MLX5_QP_STATE_ERR:
0546     return "ERR";
0547     case MLX5_QP_STATE_SQ_DRAINING:
0548     return "SQ_DRAINING";
0549     case MLX5_QP_STATE_SUSPENDED:
0550     return "SUSPENDED";
0551     default: return "Invalid QP state";
0552     }
0553 }
0554
0555 static inline int mlx5_get_qp_default_ts(struct mlx5_core_dev *dev)
0556 {
0557     return !MLX5_CAP_ROCE(dev, qp_ts_format) ?
0558                MLX5_TIMESTAMP_FORMAT_FREE_RUNNING :
0559                MLX5_TIMESTAMP_FORMAT_DEFAULT;
0560 }
0561
0562 #endif /* MLX5_QP_H */