linux/mlx5/port.h

0001 /*
0002  * Copyright (c) 2016, Mellanox Technologies. All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032
0033 #ifndef __MLX5_PORT_H__
0034 #define __MLX5_PORT_H__
0035
0036 #include <linux/mlx5/driver.h>
0037
0038 enum mlx5_beacon_duration {
0039     MLX5_BEACON_DURATION_OFF = 0x0,
0040     MLX5_BEACON_DURATION_INF = 0xffff,
0041 };
0042
0043 enum mlx5_module_id {
0044     MLX5_MODULE_ID_SFP              = 0x3,
0045     MLX5_MODULE_ID_QSFP             = 0xC,
0046     MLX5_MODULE_ID_QSFP_PLUS        = 0xD,
0047     MLX5_MODULE_ID_QSFP28           = 0x11,
0048     MLX5_MODULE_ID_DSFP     = 0x1B,
0049 };
0050
0051 enum mlx5_an_status {
0052     MLX5_AN_UNAVAILABLE = 0,
0053     MLX5_AN_COMPLETE    = 1,
0054     MLX5_AN_FAILED      = 2,
0055     MLX5_AN_LINK_UP     = 3,
0056     MLX5_AN_LINK_DOWN   = 4,
0057 };
0058
0059 #define MLX5_I2C_ADDR_LOW       0x50
0060 #define MLX5_I2C_ADDR_HIGH      0x51
0061 #define MLX5_EEPROM_PAGE_LENGTH     256
0062 #define MLX5_EEPROM_HIGH_PAGE_LENGTH    128
0063
0064 struct mlx5_module_eeprom_query_params {
0065     u16 size;
0066     u16 offset;
0067     u16 i2c_address;
0068     u32 page;
0069     u32 bank;
0070     u32 module_number;
0071 };
0072
0073 enum mlx5e_link_mode {
0074     MLX5E_1000BASE_CX_SGMII  = 0,
0075     MLX5E_1000BASE_KX    = 1,
0076     MLX5E_10GBASE_CX4    = 2,
0077     MLX5E_10GBASE_KX4    = 3,
0078     MLX5E_10GBASE_KR     = 4,
0079     MLX5E_20GBASE_KR2    = 5,
0080     MLX5E_40GBASE_CR4    = 6,
0081     MLX5E_40GBASE_KR4    = 7,
0082     MLX5E_56GBASE_R4     = 8,
0083     MLX5E_10GBASE_CR     = 12,
0084     MLX5E_10GBASE_SR     = 13,
0085     MLX5E_10GBASE_ER     = 14,
0086     MLX5E_40GBASE_SR4    = 15,
0087     MLX5E_40GBASE_LR4    = 16,
0088     MLX5E_50GBASE_SR2    = 18,
0089     MLX5E_100GBASE_CR4   = 20,
0090     MLX5E_100GBASE_SR4   = 21,
0091     MLX5E_100GBASE_KR4   = 22,
0092     MLX5E_100GBASE_LR4   = 23,
0093     MLX5E_100BASE_TX     = 24,
0094     MLX5E_1000BASE_T     = 25,
0095     MLX5E_10GBASE_T      = 26,
0096     MLX5E_25GBASE_CR     = 27,
0097     MLX5E_25GBASE_KR     = 28,
0098     MLX5E_25GBASE_SR     = 29,
0099     MLX5E_50GBASE_CR2    = 30,
0100     MLX5E_50GBASE_KR2    = 31,
0101     MLX5E_LINK_MODES_NUMBER,
0102 };
0103
0104 enum mlx5e_ext_link_mode {
0105     MLX5E_SGMII_100M            = 0,
0106     MLX5E_1000BASE_X_SGMII          = 1,
0107     MLX5E_5GBASE_R              = 3,
0108     MLX5E_10GBASE_XFI_XAUI_1        = 4,
0109     MLX5E_40GBASE_XLAUI_4_XLPPI_4       = 5,
0110     MLX5E_25GAUI_1_25GBASE_CR_KR        = 6,
0111     MLX5E_50GAUI_2_LAUI_2_50GBASE_CR2_KR2   = 7,
0112     MLX5E_50GAUI_1_LAUI_1_50GBASE_CR_KR = 8,
0113     MLX5E_CAUI_4_100GBASE_CR4_KR4       = 9,
0114     MLX5E_100GAUI_2_100GBASE_CR2_KR2    = 10,
0115     MLX5E_100GAUI_1_100GBASE_CR_KR      = 11,
0116     MLX5E_200GAUI_4_200GBASE_CR4_KR4    = 12,
0117     MLX5E_200GAUI_2_200GBASE_CR2_KR2    = 13,
0118     MLX5E_400GAUI_8             = 15,
0119     MLX5E_400GAUI_4_400GBASE_CR4_KR4    = 16,
0120     MLX5E_EXT_LINK_MODES_NUMBER,
0121 };
0122
0123 enum mlx5e_connector_type {
0124     MLX5E_PORT_UNKNOWN  = 0,
0125     MLX5E_PORT_NONE         = 1,
0126     MLX5E_PORT_TP           = 2,
0127     MLX5E_PORT_AUI          = 3,
0128     MLX5E_PORT_BNC          = 4,
0129     MLX5E_PORT_MII          = 5,
0130     MLX5E_PORT_FIBRE        = 6,
0131     MLX5E_PORT_DA           = 7,
0132     MLX5E_PORT_OTHER        = 8,
0133     MLX5E_CONNECTOR_TYPE_NUMBER,
0134 };
0135
0136 enum mlx5_ptys_width {
0137     MLX5_PTYS_WIDTH_1X  = 1 << 0,
0138     MLX5_PTYS_WIDTH_2X  = 1 << 1,
0139     MLX5_PTYS_WIDTH_4X  = 1 << 2,
0140     MLX5_PTYS_WIDTH_8X  = 1 << 3,
0141     MLX5_PTYS_WIDTH_12X = 1 << 4,
0142 };
0143
0144 #define MLX5E_PROT_MASK(link_mode) (1U << link_mode)
0145 #define MLX5_GET_ETH_PROTO(reg, out, ext, field)    \
0146     (ext ? MLX5_GET(reg, out, ext_##field) :    \
0147     MLX5_GET(reg, out, field))
0148
0149 int mlx5_set_port_caps(struct mlx5_core_dev *dev, u8 port_num, u32 caps);
0150 int mlx5_query_port_ptys(struct mlx5_core_dev *dev, u32 *ptys,
0151              int ptys_size, int proto_mask, u8 local_port);
0152
0153 int mlx5_query_ib_port_oper(struct mlx5_core_dev *dev, u16 *link_width_oper,
0154                 u16 *proto_oper, u8 local_port);
0155 void mlx5_toggle_port_link(struct mlx5_core_dev *dev);
0156 int mlx5_set_port_admin_status(struct mlx5_core_dev *dev,
0157                    enum mlx5_port_status status);
0158 int mlx5_query_port_admin_status(struct mlx5_core_dev *dev,
0159                  enum mlx5_port_status *status);
0160 int mlx5_set_port_beacon(struct mlx5_core_dev *dev, u16 beacon_duration);
0161
0162 int mlx5_set_port_mtu(struct mlx5_core_dev *dev, u16 mtu, u8 port);
0163 void mlx5_query_port_max_mtu(struct mlx5_core_dev *dev, u16 *max_mtu, u8 port);
0164 void mlx5_query_port_oper_mtu(struct mlx5_core_dev *dev, u16 *oper_mtu,
0165                   u8 port);
0166
0167 int mlx5_query_port_vl_hw_cap(struct mlx5_core_dev *dev,
0168                   u8 *vl_hw_cap, u8 local_port);
0169
0170 int mlx5_set_port_pause(struct mlx5_core_dev *dev, u32 rx_pause, u32 tx_pause);
0171 int mlx5_query_port_pause(struct mlx5_core_dev *dev,
0172               u32 *rx_pause, u32 *tx_pause);
0173
0174 int mlx5_set_port_pfc(struct mlx5_core_dev *dev, u8 pfc_en_tx, u8 pfc_en_rx);
0175 int mlx5_query_port_pfc(struct mlx5_core_dev *dev, u8 *pfc_en_tx,
0176             u8 *pfc_en_rx);
0177
0178 int mlx5_set_port_stall_watermark(struct mlx5_core_dev *dev,
0179                   u16 stall_critical_watermark,
0180                   u16 stall_minor_watermark);
0181 int mlx5_query_port_stall_watermark(struct mlx5_core_dev *dev,
0182                     u16 *stall_critical_watermark, u16 *stall_minor_watermark);
0183
0184 int mlx5_max_tc(struct mlx5_core_dev *mdev);
0185
0186 int mlx5_set_port_prio_tc(struct mlx5_core_dev *mdev, u8 *prio_tc);
0187 int mlx5_query_port_prio_tc(struct mlx5_core_dev *mdev,
0188                 u8 prio, u8 *tc);
0189 int mlx5_set_port_tc_group(struct mlx5_core_dev *mdev, u8 *tc_group);
0190 int mlx5_query_port_tc_group(struct mlx5_core_dev *mdev,
0191                  u8 tc, u8 *tc_group);
0192 int mlx5_set_port_tc_bw_alloc(struct mlx5_core_dev *mdev, u8 *tc_bw);
0193 int mlx5_query_port_tc_bw_alloc(struct mlx5_core_dev *mdev,
0194                 u8 tc, u8 *bw_pct);
0195 int mlx5_modify_port_ets_rate_limit(struct mlx5_core_dev *mdev,
0196                     u8 *max_bw_value,
0197                     u8 *max_bw_unit);
0198 int mlx5_query_port_ets_rate_limit(struct mlx5_core_dev *mdev,
0199                    u8 *max_bw_value,
0200                    u8 *max_bw_unit);
0201 int mlx5_set_port_wol(struct mlx5_core_dev *mdev, u8 wol_mode);
0202 int mlx5_query_port_wol(struct mlx5_core_dev *mdev, u8 *wol_mode);
0203
0204 int mlx5_query_ports_check(struct mlx5_core_dev *mdev, u32 *out, int outlen);
0205 int mlx5_set_ports_check(struct mlx5_core_dev *mdev, u32 *in, int inlen);
0206 int mlx5_set_port_fcs(struct mlx5_core_dev *mdev, u8 enable);
0207 void mlx5_query_port_fcs(struct mlx5_core_dev *mdev, bool *supported,
0208              bool *enabled);
0209 int mlx5_query_module_eeprom(struct mlx5_core_dev *dev,
0210                  u16 offset, u16 size, u8 *data);
0211 int mlx5_query_module_eeprom_by_page(struct mlx5_core_dev *dev,
0212                      struct mlx5_module_eeprom_query_params *params, u8 *data);
0213
0214 int mlx5_query_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *out);
0215 int mlx5_set_port_dcbx_param(struct mlx5_core_dev *mdev, u32 *in);
0216
0217 int mlx5_set_trust_state(struct mlx5_core_dev *mdev, u8 trust_state);
0218 int mlx5_query_trust_state(struct mlx5_core_dev *mdev, u8 *trust_state);
0219 int mlx5_set_dscp2prio(struct mlx5_core_dev *mdev, u8 dscp, u8 prio);
0220 int mlx5_query_dscp2prio(struct mlx5_core_dev *mdev, u8 *dscp2prio);
0221 #endif /* __MLX5_PORT_H__ */