0001
0002
0003
0004 #ifndef __MLX5_IFC_VDPA_H_
0005 #define __MLX5_IFC_VDPA_H_
0006
0007 enum {
0008 MLX5_VIRTIO_Q_EVENT_MODE_NO_MSIX_MODE = 0x0,
0009 MLX5_VIRTIO_Q_EVENT_MODE_QP_MODE = 0x1,
0010 MLX5_VIRTIO_Q_EVENT_MODE_MSIX_MODE = 0x2,
0011 };
0012
0013 enum {
0014 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT = 0,
0015 MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED = 1,
0016 };
0017
0018 enum {
0019 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_SPLIT =
0020 BIT(MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_SPLIT),
0021 MLX5_VIRTIO_EMULATION_CAP_VIRTIO_QUEUE_TYPE_PACKED =
0022 BIT(MLX5_VIRTIO_EMULATION_VIRTIO_QUEUE_TYPE_PACKED),
0023 };
0024
0025 struct mlx5_ifc_virtio_q_bits {
0026 u8 virtio_q_type[0x8];
0027 u8 reserved_at_8[0x5];
0028 u8 event_mode[0x3];
0029 u8 queue_index[0x10];
0030
0031 u8 full_emulation[0x1];
0032 u8 virtio_version_1_0[0x1];
0033 u8 reserved_at_22[0x2];
0034 u8 offload_type[0x4];
0035 u8 event_qpn_or_msix[0x18];
0036
0037 u8 doorbell_stride_index[0x10];
0038 u8 queue_size[0x10];
0039
0040 u8 device_emulation_id[0x20];
0041
0042 u8 desc_addr[0x40];
0043
0044 u8 used_addr[0x40];
0045
0046 u8 available_addr[0x40];
0047
0048 u8 virtio_q_mkey[0x20];
0049
0050 u8 max_tunnel_desc[0x10];
0051 u8 reserved_at_170[0x8];
0052 u8 error_type[0x8];
0053
0054 u8 umem_1_id[0x20];
0055
0056 u8 umem_1_size[0x20];
0057
0058 u8 umem_1_offset[0x40];
0059
0060 u8 umem_2_id[0x20];
0061
0062 u8 umem_2_size[0x20];
0063
0064 u8 umem_2_offset[0x40];
0065
0066 u8 umem_3_id[0x20];
0067
0068 u8 umem_3_size[0x20];
0069
0070 u8 umem_3_offset[0x40];
0071
0072 u8 counter_set_id[0x20];
0073
0074 u8 reserved_at_320[0x8];
0075 u8 pd[0x18];
0076
0077 u8 reserved_at_340[0xc0];
0078 };
0079
0080 struct mlx5_ifc_virtio_net_q_object_bits {
0081 u8 modify_field_select[0x40];
0082
0083 u8 reserved_at_40[0x20];
0084
0085 u8 vhca_id[0x10];
0086 u8 reserved_at_70[0x10];
0087
0088 u8 queue_feature_bit_mask_12_3[0xa];
0089 u8 dirty_bitmap_dump_enable[0x1];
0090 u8 vhost_log_page[0x5];
0091 u8 reserved_at_90[0xc];
0092 u8 state[0x4];
0093
0094 u8 reserved_at_a0[0x5];
0095 u8 queue_feature_bit_mask_2_0[0x3];
0096 u8 tisn_or_qpn[0x18];
0097
0098 u8 dirty_bitmap_mkey[0x20];
0099
0100 u8 dirty_bitmap_size[0x20];
0101
0102 u8 dirty_bitmap_addr[0x40];
0103
0104 u8 hw_available_index[0x10];
0105 u8 hw_used_index[0x10];
0106
0107 u8 reserved_at_160[0xa0];
0108
0109 struct mlx5_ifc_virtio_q_bits virtio_q_context;
0110 };
0111
0112 struct mlx5_ifc_create_virtio_net_q_in_bits {
0113 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
0114
0115 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
0116 };
0117
0118 struct mlx5_ifc_create_virtio_net_q_out_bits {
0119 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
0120 };
0121
0122 struct mlx5_ifc_destroy_virtio_net_q_in_bits {
0123 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_out_cmd_hdr;
0124 };
0125
0126 struct mlx5_ifc_destroy_virtio_net_q_out_bits {
0127 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
0128 };
0129
0130 struct mlx5_ifc_query_virtio_net_q_in_bits {
0131 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
0132 };
0133
0134 struct mlx5_ifc_query_virtio_net_q_out_bits {
0135 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
0136
0137 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
0138 };
0139
0140 enum {
0141 MLX5_VIRTQ_MODIFY_MASK_STATE = (u64)1 << 0,
0142 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_PARAMS = (u64)1 << 3,
0143 MLX5_VIRTQ_MODIFY_MASK_DIRTY_BITMAP_DUMP_ENABLE = (u64)1 << 4,
0144 };
0145
0146 enum {
0147 MLX5_VIRTIO_NET_Q_OBJECT_STATE_INIT = 0x0,
0148 MLX5_VIRTIO_NET_Q_OBJECT_STATE_RDY = 0x1,
0149 MLX5_VIRTIO_NET_Q_OBJECT_STATE_SUSPEND = 0x2,
0150 MLX5_VIRTIO_NET_Q_OBJECT_STATE_ERR = 0x3,
0151 };
0152
0153
0154
0155
0156
0157 enum {
0158 MLX5_VIRTIO_NET_Q_OBJECT_NONE = 0xffffffff
0159 };
0160
0161 enum {
0162 MLX5_RQTC_LIST_Q_TYPE_RQ = 0x0,
0163 MLX5_RQTC_LIST_Q_TYPE_VIRTIO_NET_Q = 0x1,
0164 };
0165
0166 struct mlx5_ifc_modify_virtio_net_q_in_bits {
0167 struct mlx5_ifc_general_obj_in_cmd_hdr_bits general_obj_in_cmd_hdr;
0168
0169 struct mlx5_ifc_virtio_net_q_object_bits obj_context;
0170 };
0171
0172 struct mlx5_ifc_modify_virtio_net_q_out_bits {
0173 struct mlx5_ifc_general_obj_out_cmd_hdr_bits general_obj_out_cmd_hdr;
0174 };
0175
0176 struct mlx5_ifc_virtio_q_counters_bits {
0177 u8 modify_field_select[0x40];
0178 u8 reserved_at_40[0x40];
0179 u8 received_desc[0x40];
0180 u8 completed_desc[0x40];
0181 u8 error_cqes[0x20];
0182 u8 bad_desc_errors[0x20];
0183 u8 exceed_max_chain[0x20];
0184 u8 invalid_buffer[0x20];
0185 u8 reserved_at_180[0x280];
0186 };
0187
0188 struct mlx5_ifc_create_virtio_q_counters_in_bits {
0189 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
0190 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
0191 };
0192
0193 struct mlx5_ifc_create_virtio_q_counters_out_bits {
0194 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
0195 struct mlx5_ifc_virtio_q_counters_bits virtio_q_counters;
0196 };
0197
0198 struct mlx5_ifc_destroy_virtio_q_counters_in_bits {
0199 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
0200 };
0201
0202 struct mlx5_ifc_destroy_virtio_q_counters_out_bits {
0203 struct mlx5_ifc_general_obj_out_cmd_hdr_bits hdr;
0204 };
0205
0206 struct mlx5_ifc_query_virtio_q_counters_in_bits {
0207 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
0208 };
0209
0210 struct mlx5_ifc_query_virtio_q_counters_out_bits {
0211 struct mlx5_ifc_general_obj_in_cmd_hdr_bits hdr;
0212 struct mlx5_ifc_virtio_q_counters_bits counters;
0213 };
0214
0215 #endif
