linux/mlx5/mlx5_ifc_fpga.h

0001 /*
0002  * Copyright (c) 2017, Mellanox Technologies, Ltd.  All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *      - Redistributions of source code must retain the above
0015  *        copyright notice, this list of conditions and the following
0016  *        disclaimer.
0017  *
0018  *      - Redistributions in binary form must reproduce the above
0019  *        copyright notice, this list of conditions and the following
0020  *        disclaimer in the documentation and/or other materials
0021  *        provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032 #ifndef MLX5_IFC_FPGA_H
0033 #define MLX5_IFC_FPGA_H
0034
0035 struct mlx5_ifc_ipv4_layout_bits {
0036     u8         reserved_at_0[0x60];
0037
0038     u8         ipv4[0x20];
0039 };
0040
0041 struct mlx5_ifc_ipv6_layout_bits {
0042     u8         ipv6[16][0x8];
0043 };
0044
0045 union mlx5_ifc_ipv6_layout_ipv4_layout_auto_bits {
0046     struct mlx5_ifc_ipv6_layout_bits ipv6_layout;
0047     struct mlx5_ifc_ipv4_layout_bits ipv4_layout;
0048     u8         reserved_at_0[0x80];
0049 };
0050
0051 enum {
0052     MLX5_FPGA_CAP_SANDBOX_VENDOR_ID_MLNX = 0x2c9,
0053 };
0054
0055 enum {
0056     MLX5_FPGA_CAP_SANDBOX_PRODUCT_ID_IPSEC    = 0x2,
0057 };
0058
0059 struct mlx5_ifc_fpga_shell_caps_bits {
0060     u8         max_num_qps[0x10];
0061     u8         reserved_at_10[0x8];
0062     u8         total_rcv_credits[0x8];
0063
0064     u8         reserved_at_20[0xe];
0065     u8         qp_type[0x2];
0066     u8         reserved_at_30[0x5];
0067     u8         rae[0x1];
0068     u8         rwe[0x1];
0069     u8         rre[0x1];
0070     u8         reserved_at_38[0x4];
0071     u8         dc[0x1];
0072     u8         ud[0x1];
0073     u8         uc[0x1];
0074     u8         rc[0x1];
0075
0076     u8         reserved_at_40[0x1a];
0077     u8         log_ddr_size[0x6];
0078
0079     u8         max_fpga_qp_msg_size[0x20];
0080
0081     u8         reserved_at_80[0x180];
0082 };
0083
0084 struct mlx5_ifc_fpga_cap_bits {
0085     u8         fpga_id[0x8];
0086     u8         fpga_device[0x18];
0087
0088     u8         register_file_ver[0x20];
0089
0090     u8         fpga_ctrl_modify[0x1];
0091     u8         reserved_at_41[0x5];
0092     u8         access_reg_query_mode[0x2];
0093     u8         reserved_at_48[0x6];
0094     u8         access_reg_modify_mode[0x2];
0095     u8         reserved_at_50[0x10];
0096
0097     u8         reserved_at_60[0x20];
0098
0099     u8         image_version[0x20];
0100
0101     u8         image_date[0x20];
0102
0103     u8         image_time[0x20];
0104
0105     u8         shell_version[0x20];
0106
0107     u8         reserved_at_100[0x80];
0108
0109     struct mlx5_ifc_fpga_shell_caps_bits shell_caps;
0110
0111     u8         reserved_at_380[0x8];
0112     u8         ieee_vendor_id[0x18];
0113
0114     u8         sandbox_product_version[0x10];
0115     u8         sandbox_product_id[0x10];
0116
0117     u8         sandbox_basic_caps[0x20];
0118
0119     u8         reserved_at_3e0[0x10];
0120     u8         sandbox_extended_caps_len[0x10];
0121
0122     u8         sandbox_extended_caps_addr[0x40];
0123
0124     u8         fpga_ddr_start_addr[0x40];
0125
0126     u8         fpga_cr_space_start_addr[0x40];
0127
0128     u8         fpga_ddr_size[0x20];
0129
0130     u8         fpga_cr_space_size[0x20];
0131
0132     u8         reserved_at_500[0x300];
0133 };
0134
0135 enum {
0136     MLX5_FPGA_CTRL_OPERATION_LOAD                = 0x1,
0137     MLX5_FPGA_CTRL_OPERATION_RESET               = 0x2,
0138     MLX5_FPGA_CTRL_OPERATION_FLASH_SELECT        = 0x3,
0139     MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_ON   = 0x4,
0140     MLX5_FPGA_CTRL_OPERATION_SANDBOX_BYPASS_OFF  = 0x5,
0141     MLX5_FPGA_CTRL_OPERATION_RESET_SANDBOX       = 0x6,
0142 };
0143
0144 struct mlx5_ifc_fpga_ctrl_bits {
0145     u8         reserved_at_0[0x8];
0146     u8         operation[0x8];
0147     u8         reserved_at_10[0x8];
0148     u8         status[0x8];
0149
0150     u8         reserved_at_20[0x8];
0151     u8         flash_select_admin[0x8];
0152     u8         reserved_at_30[0x8];
0153     u8         flash_select_oper[0x8];
0154
0155     u8         reserved_at_40[0x40];
0156 };
0157
0158 enum {
0159     MLX5_FPGA_ERROR_EVENT_SYNDROME_CORRUPTED_DDR        = 0x1,
0160     MLX5_FPGA_ERROR_EVENT_SYNDROME_FLASH_TIMEOUT        = 0x2,
0161     MLX5_FPGA_ERROR_EVENT_SYNDROME_INTERNAL_LINK_ERROR  = 0x3,
0162     MLX5_FPGA_ERROR_EVENT_SYNDROME_WATCHDOG_FAILURE     = 0x4,
0163     MLX5_FPGA_ERROR_EVENT_SYNDROME_I2C_FAILURE          = 0x5,
0164     MLX5_FPGA_ERROR_EVENT_SYNDROME_IMAGE_CHANGED        = 0x6,
0165     MLX5_FPGA_ERROR_EVENT_SYNDROME_TEMPERATURE_CRITICAL = 0x7,
0166 };
0167
0168 struct mlx5_ifc_fpga_error_event_bits {
0169     u8         reserved_at_0[0x40];
0170
0171     u8         reserved_at_40[0x18];
0172     u8         syndrome[0x8];
0173
0174     u8         reserved_at_60[0x80];
0175 };
0176
0177 #define MLX5_FPGA_ACCESS_REG_SIZE_MAX 64
0178
0179 struct mlx5_ifc_fpga_access_reg_bits {
0180     u8         reserved_at_0[0x20];
0181
0182     u8         reserved_at_20[0x10];
0183     u8         size[0x10];
0184
0185     u8         address[0x40];
0186
0187     u8         data[0][0x8];
0188 };
0189
0190 enum mlx5_ifc_fpga_qp_state {
0191     MLX5_FPGA_QPC_STATE_INIT    = 0x0,
0192     MLX5_FPGA_QPC_STATE_ACTIVE  = 0x1,
0193     MLX5_FPGA_QPC_STATE_ERROR   = 0x2,
0194 };
0195
0196 enum mlx5_ifc_fpga_qp_type {
0197     MLX5_FPGA_QPC_QP_TYPE_SHELL_QP    = 0x0,
0198     MLX5_FPGA_QPC_QP_TYPE_SANDBOX_QP  = 0x1,
0199 };
0200
0201 enum mlx5_ifc_fpga_qp_service_type {
0202     MLX5_FPGA_QPC_ST_RC  = 0x0,
0203 };
0204
0205 struct mlx5_ifc_fpga_qpc_bits {
0206     u8         state[0x4];
0207     u8         reserved_at_4[0x1b];
0208     u8         qp_type[0x1];
0209
0210     u8         reserved_at_20[0x4];
0211     u8         st[0x4];
0212     u8         reserved_at_28[0x10];
0213     u8         traffic_class[0x8];
0214
0215     u8         ether_type[0x10];
0216     u8         prio[0x3];
0217     u8         dei[0x1];
0218     u8         vid[0xc];
0219
0220     u8         reserved_at_60[0x20];
0221
0222     u8         reserved_at_80[0x8];
0223     u8         next_rcv_psn[0x18];
0224
0225     u8         reserved_at_a0[0x8];
0226     u8         next_send_psn[0x18];
0227
0228     u8         reserved_at_c0[0x10];
0229     u8         pkey[0x10];
0230
0231     u8         reserved_at_e0[0x8];
0232     u8         remote_qpn[0x18];
0233
0234     u8         reserved_at_100[0x15];
0235     u8         rnr_retry[0x3];
0236     u8         reserved_at_118[0x5];
0237     u8         retry_count[0x3];
0238
0239     u8         reserved_at_120[0x20];
0240
0241     u8         reserved_at_140[0x10];
0242     u8         remote_mac_47_32[0x10];
0243
0244     u8         remote_mac_31_0[0x20];
0245
0246     u8         remote_ip[16][0x8];
0247
0248     u8         reserved_at_200[0x40];
0249
0250     u8         reserved_at_240[0x10];
0251     u8         fpga_mac_47_32[0x10];
0252
0253     u8         fpga_mac_31_0[0x20];
0254
0255     u8         fpga_ip[16][0x8];
0256 };
0257
0258 struct mlx5_ifc_fpga_create_qp_in_bits {
0259     u8         opcode[0x10];
0260     u8         reserved_at_10[0x10];
0261
0262     u8         reserved_at_20[0x10];
0263     u8         op_mod[0x10];
0264
0265     u8         reserved_at_40[0x40];
0266
0267     struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
0268 };
0269
0270 struct mlx5_ifc_fpga_create_qp_out_bits {
0271     u8         status[0x8];
0272     u8         reserved_at_8[0x18];
0273
0274     u8         syndrome[0x20];
0275
0276     u8         reserved_at_40[0x8];
0277     u8         fpga_qpn[0x18];
0278
0279     u8         reserved_at_60[0x20];
0280
0281     struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
0282 };
0283
0284 struct mlx5_ifc_fpga_modify_qp_in_bits {
0285     u8         opcode[0x10];
0286     u8         reserved_at_10[0x10];
0287
0288     u8         reserved_at_20[0x10];
0289     u8         op_mod[0x10];
0290
0291     u8         reserved_at_40[0x8];
0292     u8         fpga_qpn[0x18];
0293
0294     u8         field_select[0x20];
0295
0296     struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
0297 };
0298
0299 struct mlx5_ifc_fpga_modify_qp_out_bits {
0300     u8         status[0x8];
0301     u8         reserved_at_8[0x18];
0302
0303     u8         syndrome[0x20];
0304
0305     u8         reserved_at_40[0x40];
0306 };
0307
0308 struct mlx5_ifc_fpga_query_qp_in_bits {
0309     u8         opcode[0x10];
0310     u8         reserved_at_10[0x10];
0311
0312     u8         reserved_at_20[0x10];
0313     u8         op_mod[0x10];
0314
0315     u8         reserved_at_40[0x8];
0316     u8         fpga_qpn[0x18];
0317
0318     u8         reserved_at_60[0x20];
0319 };
0320
0321 struct mlx5_ifc_fpga_query_qp_out_bits {
0322     u8         status[0x8];
0323     u8         reserved_at_8[0x18];
0324
0325     u8         syndrome[0x20];
0326
0327     u8         reserved_at_40[0x40];
0328
0329     struct mlx5_ifc_fpga_qpc_bits fpga_qpc;
0330 };
0331
0332 struct mlx5_ifc_fpga_query_qp_counters_in_bits {
0333     u8         opcode[0x10];
0334     u8         reserved_at_10[0x10];
0335
0336     u8         reserved_at_20[0x10];
0337     u8         op_mod[0x10];
0338
0339     u8         clear[0x1];
0340     u8         reserved_at_41[0x7];
0341     u8         fpga_qpn[0x18];
0342
0343     u8         reserved_at_60[0x20];
0344 };
0345
0346 struct mlx5_ifc_fpga_query_qp_counters_out_bits {
0347     u8         status[0x8];
0348     u8         reserved_at_8[0x18];
0349
0350     u8         syndrome[0x20];
0351
0352     u8         reserved_at_40[0x40];
0353
0354     u8         rx_ack_packets[0x40];
0355
0356     u8         rx_send_packets[0x40];
0357
0358     u8         tx_ack_packets[0x40];
0359
0360     u8         tx_send_packets[0x40];
0361
0362     u8         rx_total_drop[0x40];
0363
0364     u8         reserved_at_1c0[0x1c0];
0365 };
0366
0367 struct mlx5_ifc_fpga_destroy_qp_in_bits {
0368     u8         opcode[0x10];
0369     u8         reserved_at_10[0x10];
0370
0371     u8         reserved_at_20[0x10];
0372     u8         op_mod[0x10];
0373
0374     u8         reserved_at_40[0x8];
0375     u8         fpga_qpn[0x18];
0376
0377     u8         reserved_at_60[0x20];
0378 };
0379
0380 struct mlx5_ifc_fpga_destroy_qp_out_bits {
0381     u8         status[0x8];
0382     u8         reserved_at_8[0x18];
0383
0384     u8         syndrome[0x20];
0385
0386     u8         reserved_at_40[0x40];
0387 };
0388
0389 enum {
0390     MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RETRY_COUNTER_EXPIRED  = 0x1,
0391     MLX5_FPGA_QP_ERROR_EVENT_SYNDROME_RNR_EXPIRED            = 0x2,
0392 };
0393
0394 struct mlx5_ifc_fpga_qp_error_event_bits {
0395     u8         reserved_at_0[0x40];
0396
0397     u8         reserved_at_40[0x18];
0398     u8         syndrome[0x8];
0399
0400     u8         reserved_at_60[0x60];
0401
0402     u8         reserved_at_c0[0x8];
0403     u8         fpga_qpn[0x18];
0404 };
0405 #endif /* MLX5_IFC_FPGA_H */