linux/mlx5/eswitch.h

0001 /* SPDX-License-Identifier: (GPL-2.0+ OR BSD-3-Clause) */
0002 /*
0003  * Copyright (c) 2018 Mellanox Technologies. All rights reserved.
0004  */
0005
0006 #ifndef _MLX5_ESWITCH_
0007 #define _MLX5_ESWITCH_
0008
0009 #include <linux/mlx5/driver.h>
0010 #include <net/devlink.h>
0011
0012 #define MLX5_ESWITCH_MANAGER(mdev) MLX5_CAP_GEN(mdev, eswitch_manager)
0013
0014 enum {
0015     MLX5_ESWITCH_LEGACY,
0016     MLX5_ESWITCH_OFFLOADS
0017 };
0018
0019 enum {
0020     REP_ETH,
0021     REP_IB,
0022     NUM_REP_TYPES,
0023 };
0024
0025 enum {
0026     REP_UNREGISTERED,
0027     REP_REGISTERED,
0028     REP_LOADED,
0029 };
0030
0031 enum mlx5_switchdev_event {
0032     MLX5_SWITCHDEV_EVENT_PAIR,
0033     MLX5_SWITCHDEV_EVENT_UNPAIR,
0034 };
0035
0036 struct mlx5_eswitch_rep;
0037 struct mlx5_eswitch_rep_ops {
0038     int (*load)(struct mlx5_core_dev *dev, struct mlx5_eswitch_rep *rep);
0039     void (*unload)(struct mlx5_eswitch_rep *rep);
0040     void *(*get_proto_dev)(struct mlx5_eswitch_rep *rep);
0041     int (*event)(struct mlx5_eswitch *esw,
0042              struct mlx5_eswitch_rep *rep,
0043              enum mlx5_switchdev_event event,
0044              void *data);
0045 };
0046
0047 struct mlx5_eswitch_rep_data {
0048     void *priv;
0049     atomic_t state;
0050 };
0051
0052 struct mlx5_eswitch_rep {
0053     struct mlx5_eswitch_rep_data rep_data[NUM_REP_TYPES];
0054     u16            vport;
0055     u16            vlan;
0056     /* Only IB rep is using vport_index */
0057     u16            vport_index;
0058     u32            vlan_refcount;
0059     struct                 mlx5_eswitch *esw;
0060 };
0061
0062 void mlx5_eswitch_register_vport_reps(struct mlx5_eswitch *esw,
0063                       const struct mlx5_eswitch_rep_ops *ops,
0064                       u8 rep_type);
0065 void mlx5_eswitch_unregister_vport_reps(struct mlx5_eswitch *esw, u8 rep_type);
0066 void *mlx5_eswitch_get_proto_dev(struct mlx5_eswitch *esw,
0067                  u16 vport_num,
0068                  u8 rep_type);
0069 struct mlx5_eswitch_rep *mlx5_eswitch_vport_rep(struct mlx5_eswitch *esw,
0070                         u16 vport_num);
0071 void *mlx5_eswitch_uplink_get_proto_dev(struct mlx5_eswitch *esw, u8 rep_type);
0072 struct mlx5_flow_handle *
0073 mlx5_eswitch_add_send_to_vport_rule(struct mlx5_eswitch *on_esw,
0074                     struct mlx5_eswitch *from_esw,
0075                     struct mlx5_eswitch_rep *rep, u32 sqn);
0076
0077 #ifdef CONFIG_MLX5_ESWITCH
0078 enum devlink_eswitch_encap_mode
0079 mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev);
0080
0081 bool mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw);
0082 bool mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw);
0083
0084 /* Reg C0 usage:
0085  * Reg C0 = < ESW_PFNUM_BITS(4) | ESW_VPORT BITS(12) | ESW_REG_C0_OBJ(16) >
0086  *
0087  * Highest 4 bits of the reg c0 is the PF_NUM (range 0-15), 12 bits of
0088  * unique non-zero vport id (range 1-4095). The rest (lowest 16 bits) is left
0089  * for user data objects managed by a common mapping context.
0090  * PFNUM + VPORT comprise the SOURCE_PORT matching.
0091  */
0092 #define ESW_VPORT_BITS 12
0093 #define ESW_PFNUM_BITS 4
0094 #define ESW_SOURCE_PORT_METADATA_BITS (ESW_PFNUM_BITS + ESW_VPORT_BITS)
0095 #define ESW_SOURCE_PORT_METADATA_OFFSET (32 - ESW_SOURCE_PORT_METADATA_BITS)
0096 #define ESW_REG_C0_USER_DATA_METADATA_BITS (32 - ESW_SOURCE_PORT_METADATA_BITS)
0097 #define ESW_REG_C0_USER_DATA_METADATA_MASK GENMASK(ESW_REG_C0_USER_DATA_METADATA_BITS - 1, 0)
0098
0099 static inline u32 mlx5_eswitch_get_vport_metadata_mask(void)
0100 {
0101     return GENMASK(31, 32 - ESW_SOURCE_PORT_METADATA_BITS);
0102 }
0103
0104 u32 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw,
0105                           u16 vport_num);
0106 u32 mlx5_eswitch_get_vport_metadata_for_set(struct mlx5_eswitch *esw,
0107                         u16 vport_num);
0108
0109 /* Reg C1 usage:
0110  * Reg C1 = < Reserved(1) | ESW_TUN_ID(12) | ESW_TUN_OPTS(11) | ESW_ZONE_ID(8) >
0111  *
0112  * Highest bit is reserved for other offloads as marker bit, next 12 bits of reg c1
0113  * is the encapsulation tunnel id, next 11 bits is encapsulation tunnel options,
0114  * and the lowest 8 bits are used for zone id.
0115  *
0116  * Zone id is used to restore CT flow when packet misses on chain.
0117  *
0118  * Tunnel id and options are used together to restore the tunnel info metadata
0119  * on miss and to support inner header rewrite by means of implicit chain 0
0120  * flows.
0121  */
0122 #define ESW_RESERVED_BITS 1
0123 #define ESW_ZONE_ID_BITS 8
0124 #define ESW_TUN_OPTS_BITS 11
0125 #define ESW_TUN_ID_BITS 12
0126 #define ESW_TUN_OPTS_OFFSET ESW_ZONE_ID_BITS
0127 #define ESW_TUN_OFFSET ESW_TUN_OPTS_OFFSET
0128 #define ESW_ZONE_ID_MASK GENMASK(ESW_ZONE_ID_BITS - 1, 0)
0129 #define ESW_TUN_OPTS_MASK GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, ESW_TUN_OPTS_OFFSET)
0130 #define ESW_TUN_MASK GENMASK(31 - ESW_RESERVED_BITS, ESW_TUN_OFFSET)
0131 #define ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT 0 /* 0 is not a valid tunnel id */
0132 #define ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT
0133 /* 0x7FF is a reserved mapping */
0134 #define ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT GENMASK(ESW_TUN_OPTS_BITS - 1, 0)
0135 #define ESW_TUN_SLOW_TABLE_GOTO_VPORT ((ESW_TUN_ID_SLOW_TABLE_GOTO_VPORT << ESW_TUN_OPTS_BITS) | \
0136                        ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT)
0137 #define ESW_TUN_SLOW_TABLE_GOTO_VPORT_MARK ESW_TUN_OPTS_MASK
0138 /* 0x7FE is a reserved mapping for bridge ingress push vlan mark */
0139 #define ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN (ESW_TUN_OPTS_SLOW_TABLE_GOTO_VPORT - 1)
0140 #define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN ((ESW_TUN_ID_BRIDGE_INGRESS_PUSH_VLAN << \
0141                        ESW_TUN_OPTS_BITS) | \
0142                       ESW_TUN_OPTS_BRIDGE_INGRESS_PUSH_VLAN)
0143 #define ESW_TUN_BRIDGE_INGRESS_PUSH_VLAN_MARK \
0144     GENMASK(31 - ESW_TUN_ID_BITS - ESW_RESERVED_BITS, \
0145         ESW_TUN_OPTS_OFFSET + 1)
0146
0147 u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev);
0148 u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev);
0149 struct mlx5_core_dev *mlx5_eswitch_get_core_dev(struct mlx5_eswitch *esw);
0150
0151 #else  /* CONFIG_MLX5_ESWITCH */
0152
0153 static inline u8 mlx5_eswitch_mode(const struct mlx5_core_dev *dev)
0154 {
0155     return MLX5_ESWITCH_LEGACY;
0156 }
0157
0158 static inline enum devlink_eswitch_encap_mode
0159 mlx5_eswitch_get_encap_mode(const struct mlx5_core_dev *dev)
0160 {
0161     return DEVLINK_ESWITCH_ENCAP_MODE_NONE;
0162 }
0163
0164 static inline bool
0165 mlx5_eswitch_reg_c1_loopback_enabled(const struct mlx5_eswitch *esw)
0166 {
0167     return false;
0168 };
0169
0170 static inline bool
0171 mlx5_eswitch_vport_match_metadata_enabled(const struct mlx5_eswitch *esw)
0172 {
0173     return false;
0174 };
0175
0176 static inline u32
0177 mlx5_eswitch_get_vport_metadata_for_match(struct mlx5_eswitch *esw, u16 vport_num)
0178 {
0179     return 0;
0180 };
0181
0182 static inline u32
0183 mlx5_eswitch_get_vport_metadata_mask(void)
0184 {
0185     return 0;
0186 }
0187
0188 static inline u16 mlx5_eswitch_get_total_vports(const struct mlx5_core_dev *dev)
0189 {
0190     return 0;
0191 }
0192
0193 static inline struct mlx5_core_dev *mlx5_eswitch_get_core_dev(struct mlx5_eswitch *esw)
0194 {
0195     return NULL;
0196 }
0197
0198 #endif /* CONFIG_MLX5_ESWITCH */
0199
0200 static inline bool is_mdev_legacy_mode(struct mlx5_core_dev *dev)
0201 {
0202     return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_LEGACY;
0203 }
0204
0205 static inline bool is_mdev_switchdev_mode(struct mlx5_core_dev *dev)
0206 {
0207     return mlx5_eswitch_mode(dev) == MLX5_ESWITCH_OFFLOADS;
0208 }
0209
0210 #endif