linux/mlx4/qp.h

0001 /*
0002  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *  - Redistributions of source code must retain the above
0015  *    copyright notice, this list of conditions and the following
0016  *    disclaimer.
0017  *
0018  *  - Redistributions in binary form must reproduce the above
0019  *    copyright notice, this list of conditions and the following
0020  *    disclaimer in the documentation and/or other materials
0021  *    provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032
0033 #ifndef MLX4_QP_H
0034 #define MLX4_QP_H
0035
0036 #include <linux/types.h>
0037 #include <linux/if_ether.h>
0038
0039 #include <linux/mlx4/device.h>
0040
0041 #define MLX4_INVALID_LKEY   0x100
0042
0043 enum mlx4_qp_optpar {
0044     MLX4_QP_OPTPAR_ALT_ADDR_PATH        = 1 << 0,
0045     MLX4_QP_OPTPAR_RRE          = 1 << 1,
0046     MLX4_QP_OPTPAR_RAE          = 1 << 2,
0047     MLX4_QP_OPTPAR_RWE          = 1 << 3,
0048     MLX4_QP_OPTPAR_PKEY_INDEX       = 1 << 4,
0049     MLX4_QP_OPTPAR_Q_KEY            = 1 << 5,
0050     MLX4_QP_OPTPAR_RNR_TIMEOUT      = 1 << 6,
0051     MLX4_QP_OPTPAR_PRIMARY_ADDR_PATH    = 1 << 7,
0052     MLX4_QP_OPTPAR_SRA_MAX          = 1 << 8,
0053     MLX4_QP_OPTPAR_RRA_MAX          = 1 << 9,
0054     MLX4_QP_OPTPAR_PM_STATE         = 1 << 10,
0055     MLX4_QP_OPTPAR_RETRY_COUNT      = 1 << 12,
0056     MLX4_QP_OPTPAR_RNR_RETRY        = 1 << 13,
0057     MLX4_QP_OPTPAR_ACK_TIMEOUT      = 1 << 14,
0058     MLX4_QP_OPTPAR_SCHED_QUEUE      = 1 << 16,
0059     MLX4_QP_OPTPAR_COUNTER_INDEX        = 1 << 20,
0060     MLX4_QP_OPTPAR_VLAN_STRIPPING       = 1 << 21,
0061 };
0062
0063 enum mlx4_qp_state {
0064     MLX4_QP_STATE_RST           = 0,
0065     MLX4_QP_STATE_INIT          = 1,
0066     MLX4_QP_STATE_RTR           = 2,
0067     MLX4_QP_STATE_RTS           = 3,
0068     MLX4_QP_STATE_SQER          = 4,
0069     MLX4_QP_STATE_SQD           = 5,
0070     MLX4_QP_STATE_ERR           = 6,
0071     MLX4_QP_STATE_SQ_DRAINING       = 7,
0072     MLX4_QP_NUM_STATE
0073 };
0074
0075 enum {
0076     MLX4_QP_ST_RC               = 0x0,
0077     MLX4_QP_ST_UC               = 0x1,
0078     MLX4_QP_ST_RD               = 0x2,
0079     MLX4_QP_ST_UD               = 0x3,
0080     MLX4_QP_ST_XRC              = 0x6,
0081     MLX4_QP_ST_MLX              = 0x7
0082 };
0083
0084 enum {
0085     MLX4_QP_PM_MIGRATED         = 0x3,
0086     MLX4_QP_PM_ARMED            = 0x0,
0087     MLX4_QP_PM_REARM            = 0x1
0088 };
0089
0090 enum {
0091     /* params1 */
0092     MLX4_QP_BIT_SRE             = 1 << 15,
0093     MLX4_QP_BIT_SWE             = 1 << 14,
0094     MLX4_QP_BIT_SAE             = 1 << 13,
0095     /* params2 */
0096     MLX4_QP_BIT_RRE             = 1 << 15,
0097     MLX4_QP_BIT_RWE             = 1 << 14,
0098     MLX4_QP_BIT_RAE             = 1 << 13,
0099     MLX4_QP_BIT_FPP             = 1 <<  3,
0100     MLX4_QP_BIT_RIC             = 1 <<  4,
0101 };
0102
0103 enum {
0104     MLX4_RSS_HASH_XOR           = 0,
0105     MLX4_RSS_HASH_TOP           = 1,
0106
0107     MLX4_RSS_UDP_IPV6           = 1 << 0,
0108     MLX4_RSS_UDP_IPV4           = 1 << 1,
0109     MLX4_RSS_TCP_IPV6           = 1 << 2,
0110     MLX4_RSS_IPV6               = 1 << 3,
0111     MLX4_RSS_TCP_IPV4           = 1 << 4,
0112     MLX4_RSS_IPV4               = 1 << 5,
0113
0114     MLX4_RSS_BY_OUTER_HEADERS       = 0 << 6,
0115     MLX4_RSS_BY_INNER_HEADERS       = 2 << 6,
0116     MLX4_RSS_BY_INNER_HEADERS_IPONLY    = 3 << 6,
0117
0118     /* offset of mlx4_rss_context within mlx4_qp_context.pri_path */
0119     MLX4_RSS_OFFSET_IN_QPC_PRI_PATH     = 0x24,
0120     /* offset of being RSS indirection QP within mlx4_qp_context.flags */
0121     MLX4_RSS_QPC_FLAG_OFFSET        = 13,
0122 };
0123
0124 #define MLX4_EN_RSS_KEY_SIZE 40
0125
0126 struct mlx4_rss_context {
0127     __be32          base_qpn;
0128     __be32          default_qpn;
0129     u16         reserved;
0130     u8          hash_fn;
0131     u8          flags;
0132     __be32          rss_key[MLX4_EN_RSS_KEY_SIZE / sizeof(__be32)];
0133     __be32          base_qpn_udp;
0134 };
0135
0136 struct mlx4_qp_path {
0137     u8          fl;
0138     union {
0139         u8          vlan_control;
0140         u8          control;
0141     };
0142     u8          disable_pkey_check;
0143     u8          pkey_index;
0144     u8          counter_index;
0145     u8          grh_mylmc;
0146     __be16          rlid;
0147     u8          ackto;
0148     u8          mgid_index;
0149     u8          static_rate;
0150     u8          hop_limit;
0151     __be32          tclass_flowlabel;
0152     u8          rgid[16];
0153     u8          sched_queue;
0154     u8          vlan_index;
0155     u8          feup;
0156     u8          fvl_rx;
0157     u8          reserved4[2];
0158     u8          dmac[ETH_ALEN];
0159 };
0160
0161 enum { /* fl */
0162     MLX4_FL_CV  = 1 << 6,
0163     MLX4_FL_SV  = 1 << 5,
0164     MLX4_FL_ETH_HIDE_CQE_VLAN   = 1 << 2,
0165     MLX4_FL_ETH_SRC_CHECK_MC_LB = 1 << 1,
0166     MLX4_FL_ETH_SRC_CHECK_UC_LB = 1 << 0,
0167 };
0168
0169 enum { /* control */
0170     MLX4_CTRL_ETH_SRC_CHECK_IF_COUNTER  = 1 << 7,
0171 };
0172
0173 enum { /* vlan_control */
0174     MLX4_VLAN_CTRL_ETH_TX_BLOCK_TAGGED  = 1 << 6,
0175     MLX4_VLAN_CTRL_ETH_TX_BLOCK_PRIO_TAGGED = 1 << 5, /* 802.1p priority tag */
0176     MLX4_VLAN_CTRL_ETH_TX_BLOCK_UNTAGGED    = 1 << 4,
0177     MLX4_VLAN_CTRL_ETH_RX_BLOCK_TAGGED  = 1 << 2,
0178     MLX4_VLAN_CTRL_ETH_RX_BLOCK_PRIO_TAGGED = 1 << 1, /* 802.1p priority tag */
0179     MLX4_VLAN_CTRL_ETH_RX_BLOCK_UNTAGGED    = 1 << 0
0180 };
0181
0182 enum { /* feup */
0183     MLX4_FEUP_FORCE_ETH_UP          = 1 << 6, /* force Eth UP */
0184     MLX4_FSM_FORCE_ETH_SRC_MAC      = 1 << 5, /* force Source MAC */
0185     MLX4_FVL_FORCE_ETH_VLAN         = 1 << 3  /* force Eth vlan */
0186 };
0187
0188 enum { /* fvl_rx */
0189     MLX4_FVL_RX_FORCE_ETH_VLAN      = 1 << 0 /* enforce Eth rx vlan */
0190 };
0191
0192 struct mlx4_qp_context {
0193     __be32          flags;
0194     __be32          pd;
0195     u8          mtu_msgmax;
0196     u8          rq_size_stride;
0197     u8          sq_size_stride;
0198     u8          rlkey_roce_mode;
0199     __be32          usr_page;
0200     __be32          local_qpn;
0201     __be32          remote_qpn;
0202     struct          mlx4_qp_path pri_path;
0203     struct          mlx4_qp_path alt_path;
0204     __be32          params1;
0205     u32         reserved1;
0206     __be32          next_send_psn;
0207     __be32          cqn_send;
0208     __be16                  roce_entropy;
0209     __be16                  reserved2[3];
0210     __be32          last_acked_psn;
0211     __be32          ssn;
0212     __be32          params2;
0213     __be32          rnr_nextrecvpsn;
0214     __be32          xrcd;
0215     __be32          cqn_recv;
0216     __be64          db_rec_addr;
0217     __be32          qkey;
0218     __be32          srqn;
0219     __be32          msn;
0220     __be16          rq_wqe_counter;
0221     __be16          sq_wqe_counter;
0222     u32         reserved3;
0223     __be16          rate_limit_params;
0224     u8          reserved4;
0225     u8          qos_vport;
0226     __be32          param3;
0227     __be32          nummmcpeers_basemkey;
0228     u8          log_page_size;
0229     u8          reserved5[2];
0230     u8          mtt_base_addr_h;
0231     __be32          mtt_base_addr_l;
0232     u32         reserved6[10];
0233 };
0234
0235 struct mlx4_update_qp_context {
0236     __be64          qp_mask;
0237     __be64          primary_addr_path_mask;
0238     __be64          secondary_addr_path_mask;
0239     u64         reserved1;
0240     struct mlx4_qp_context  qp_context;
0241     u64         reserved2[58];
0242 };
0243
0244 enum {
0245     MLX4_UPD_QP_MASK_PM_STATE   = 32,
0246     MLX4_UPD_QP_MASK_VSD        = 33,
0247     MLX4_UPD_QP_MASK_QOS_VPP    = 34,
0248     MLX4_UPD_QP_MASK_RATE_LIMIT = 35,
0249 };
0250
0251 enum {
0252     MLX4_UPD_QP_PATH_MASK_PKEY_INDEX        = 0 + 32,
0253     MLX4_UPD_QP_PATH_MASK_FSM           = 1 + 32,
0254     MLX4_UPD_QP_PATH_MASK_MAC_INDEX         = 2 + 32,
0255     MLX4_UPD_QP_PATH_MASK_FVL           = 3 + 32,
0256     MLX4_UPD_QP_PATH_MASK_CV            = 4 + 32,
0257     MLX4_UPD_QP_PATH_MASK_VLAN_INDEX        = 5 + 32,
0258     MLX4_UPD_QP_PATH_MASK_ETH_HIDE_CQE_VLAN     = 6 + 32,
0259     MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_UNTAGGED = 7 + 32,
0260     MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_1P       = 8 + 32,
0261     MLX4_UPD_QP_PATH_MASK_ETH_TX_BLOCK_TAGGED   = 9 + 32,
0262     MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_UNTAGGED = 10 + 32,
0263     MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_1P       = 11 + 32,
0264     MLX4_UPD_QP_PATH_MASK_ETH_RX_BLOCK_TAGGED   = 12 + 32,
0265     MLX4_UPD_QP_PATH_MASK_FEUP          = 13 + 32,
0266     MLX4_UPD_QP_PATH_MASK_SCHED_QUEUE       = 14 + 32,
0267     MLX4_UPD_QP_PATH_MASK_IF_COUNTER_INDEX      = 15 + 32,
0268     MLX4_UPD_QP_PATH_MASK_FVL_RX            = 16 + 32,
0269     MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_UC_LB   = 18 + 32,
0270     MLX4_UPD_QP_PATH_MASK_ETH_SRC_CHECK_MC_LB   = 19 + 32,
0271     MLX4_UPD_QP_PATH_MASK_SV            = 22 + 32,
0272 };
0273
0274 enum { /* param3 */
0275     MLX4_STRIP_VLAN = 1 << 30
0276 };
0277
0278 /* Which firmware version adds support for NEC (NoErrorCompletion) bit */
0279 #define MLX4_FW_VER_WQE_CTRL_NEC mlx4_fw_ver(2, 2, 232)
0280
0281 enum {
0282     MLX4_WQE_CTRL_NEC       = 1 << 29,
0283     MLX4_WQE_CTRL_IIP       = 1 << 28,
0284     MLX4_WQE_CTRL_ILP       = 1 << 27,
0285     MLX4_WQE_CTRL_FENCE     = 1 << 6,
0286     MLX4_WQE_CTRL_CQ_UPDATE     = 3 << 2,
0287     MLX4_WQE_CTRL_SOLICITED     = 1 << 1,
0288     MLX4_WQE_CTRL_IP_CSUM       = 1 << 4,
0289     MLX4_WQE_CTRL_TCP_UDP_CSUM  = 1 << 5,
0290     MLX4_WQE_CTRL_INS_CVLAN     = 1 << 6,
0291     MLX4_WQE_CTRL_INS_SVLAN     = 1 << 7,
0292     MLX4_WQE_CTRL_STRONG_ORDER  = 1 << 7,
0293     MLX4_WQE_CTRL_FORCE_LOOPBACK    = 1 << 0,
0294 };
0295
0296 union mlx4_wqe_qpn_vlan {
0297     struct {
0298         __be16  vlan_tag;
0299         u8  ins_vlan;
0300         u8  fence_size;
0301     };
0302     __be32      bf_qpn;
0303 };
0304
0305 struct mlx4_wqe_ctrl_seg {
0306     __be32          owner_opcode;
0307     union mlx4_wqe_qpn_vlan qpn_vlan;
0308     /*
0309      * High 24 bits are SRC remote buffer; low 8 bits are flags:
0310      * [7]   SO (strong ordering)
0311      * [5]   TCP/UDP checksum
0312      * [4]   IP checksum
0313      * [3:2] C (generate completion queue entry)
0314      * [1]   SE (solicited event)
0315      * [0]   FL (force loopback)
0316      */
0317     union {
0318         __be32          srcrb_flags;
0319         __be16          srcrb_flags16[2];
0320     };
0321     /*
0322      * imm is immediate data for send/RDMA write w/ immediate;
0323      * also invalidation key for send with invalidate; input
0324      * modifier for WQEs on CCQs.
0325      */
0326     __be32          imm;
0327 };
0328
0329 enum {
0330     MLX4_WQE_MLX_VL15   = 1 << 17,
0331     MLX4_WQE_MLX_SLR    = 1 << 16
0332 };
0333
0334 struct mlx4_wqe_mlx_seg {
0335     u8          owner;
0336     u8          reserved1[2];
0337     u8          opcode;
0338     __be16          sched_prio;
0339     u8          reserved2;
0340     u8          size;
0341     /*
0342      * [17]    VL15
0343      * [16]    SLR
0344      * [15:12] static rate
0345      * [11:8]  SL
0346      * [4]     ICRC
0347      * [3:2]   C
0348      * [0]     FL (force loopback)
0349      */
0350     __be32          flags;
0351     __be16          rlid;
0352     u16         reserved3;
0353 };
0354
0355 struct mlx4_wqe_datagram_seg {
0356     __be32          av[8];
0357     __be32          dqpn;
0358     __be32          qkey;
0359     __be16          vlan;
0360     u8          mac[ETH_ALEN];
0361 };
0362
0363 struct mlx4_wqe_lso_seg {
0364     __be32          mss_hdr_size;
0365     __be32          header[];
0366 };
0367
0368 enum mlx4_wqe_bind_seg_flags2 {
0369     MLX4_WQE_BIND_ZERO_BASED = (1 << 30),
0370     MLX4_WQE_BIND_TYPE_2     = (1 << 31),
0371 };
0372
0373 struct mlx4_wqe_bind_seg {
0374     __be32          flags1;
0375     __be32          flags2;
0376     __be32          new_rkey;
0377     __be32          lkey;
0378     __be64          addr;
0379     __be64          length;
0380 };
0381
0382 enum {
0383     MLX4_WQE_FMR_PERM_LOCAL_READ    = 1 << 27,
0384     MLX4_WQE_FMR_PERM_LOCAL_WRITE   = 1 << 28,
0385     MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_READ  = 1 << 29,
0386     MLX4_WQE_FMR_AND_BIND_PERM_REMOTE_WRITE = 1 << 30,
0387     MLX4_WQE_FMR_AND_BIND_PERM_ATOMIC   = 1 << 31
0388 };
0389
0390 struct mlx4_wqe_fmr_seg {
0391     __be32          flags;
0392     __be32          mem_key;
0393     __be64          buf_list;
0394     __be64          start_addr;
0395     __be64          reg_len;
0396     __be32          offset;
0397     __be32          page_size;
0398     u32         reserved[2];
0399 };
0400
0401 struct mlx4_wqe_fmr_ext_seg {
0402     u8          flags;
0403     u8          reserved;
0404     __be16          app_mask;
0405     __be16          wire_app_tag;
0406     __be16          mem_app_tag;
0407     __be32          wire_ref_tag_base;
0408     __be32          mem_ref_tag_base;
0409 };
0410
0411 struct mlx4_wqe_local_inval_seg {
0412     u64         reserved1;
0413     __be32          mem_key;
0414     u32         reserved2;
0415     u64         reserved3[2];
0416 };
0417
0418 struct mlx4_wqe_raddr_seg {
0419     __be64          raddr;
0420     __be32          rkey;
0421     u32         reserved;
0422 };
0423
0424 struct mlx4_wqe_atomic_seg {
0425     __be64          swap_add;
0426     __be64          compare;
0427 };
0428
0429 struct mlx4_wqe_masked_atomic_seg {
0430     __be64          swap_add;
0431     __be64          compare;
0432     __be64          swap_add_mask;
0433     __be64          compare_mask;
0434 };
0435
0436 struct mlx4_wqe_data_seg {
0437     __be32          byte_count;
0438     __be32          lkey;
0439     __be64          addr;
0440 };
0441
0442 enum {
0443     MLX4_INLINE_ALIGN   = 64,
0444     MLX4_INLINE_SEG     = 1 << 31,
0445 };
0446
0447 struct mlx4_wqe_inline_seg {
0448     __be32          byte_count;
0449 };
0450
0451 enum mlx4_update_qp_attr {
0452     MLX4_UPDATE_QP_SMAC     = 1 << 0,
0453     MLX4_UPDATE_QP_VSD      = 1 << 1,
0454     MLX4_UPDATE_QP_RATE_LIMIT   = 1 << 2,
0455     MLX4_UPDATE_QP_QOS_VPORT    = 1 << 3,
0456     MLX4_UPDATE_QP_ETH_SRC_CHECK_MC_LB      = 1 << 4,
0457     MLX4_UPDATE_QP_SUPPORTED_ATTRS  = (1 << 5) - 1
0458 };
0459
0460 enum mlx4_update_qp_params_flags {
0461     MLX4_UPDATE_QP_PARAMS_FLAGS_ETH_CHECK_MC_LB     = 1 << 0,
0462     MLX4_UPDATE_QP_PARAMS_FLAGS_VSD_ENABLE      = 1 << 1,
0463 };
0464
0465 struct mlx4_update_qp_params {
0466     u8  smac_index;
0467     u8  qos_vport;
0468     u32 flags;
0469     u16 rate_unit;
0470     u16 rate_val;
0471 };
0472
0473 struct mlx4_qp *mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn);
0474 int mlx4_update_qp(struct mlx4_dev *dev, u32 qpn,
0475            enum mlx4_update_qp_attr attr,
0476            struct mlx4_update_qp_params *params);
0477 int mlx4_qp_modify(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
0478            enum mlx4_qp_state cur_state, enum mlx4_qp_state new_state,
0479            struct mlx4_qp_context *context, enum mlx4_qp_optpar optpar,
0480            int sqd_event, struct mlx4_qp *qp);
0481
0482 int mlx4_qp_query(struct mlx4_dev *dev, struct mlx4_qp *qp,
0483           struct mlx4_qp_context *context);
0484
0485 int mlx4_qp_to_ready(struct mlx4_dev *dev, struct mlx4_mtt *mtt,
0486              struct mlx4_qp_context *context,
0487              struct mlx4_qp *qp, enum mlx4_qp_state *qp_state);
0488
0489 static inline struct mlx4_qp *__mlx4_qp_lookup(struct mlx4_dev *dev, u32 qpn)
0490 {
0491     return radix_tree_lookup(&dev->qp_table_tree, qpn & (dev->caps.num_qps - 1));
0492 }
0493
0494 void mlx4_qp_remove(struct mlx4_dev *dev, struct mlx4_qp *qp);
0495
0496 static inline u16 folded_qp(u32 q)
0497 {
0498     u16 res;
0499
0500     res = ((q & 0xff) ^ ((q & 0xff0000) >> 16)) | (q & 0xff00);
0501     return res;
0502 }
0503
0504 u16 mlx4_qp_roce_entropy(struct mlx4_dev *dev, u32 qpn);
0505
0506 #endif /* MLX4_QP_H */