linux/mlx4/cq.h

0001 /*
0002  * Copyright (c) 2007 Cisco Systems, Inc.  All rights reserved.
0003  *
0004  * This software is available to you under a choice of one of two
0005  * licenses.  You may choose to be licensed under the terms of the GNU
0006  * General Public License (GPL) Version 2, available from the file
0007  * COPYING in the main directory of this source tree, or the
0008  * OpenIB.org BSD license below:
0009  *
0010  *     Redistribution and use in source and binary forms, with or
0011  *     without modification, are permitted provided that the following
0012  *     conditions are met:
0013  *
0014  *  - Redistributions of source code must retain the above
0015  *    copyright notice, this list of conditions and the following
0016  *    disclaimer.
0017  *
0018  *  - Redistributions in binary form must reproduce the above
0019  *    copyright notice, this list of conditions and the following
0020  *    disclaimer in the documentation and/or other materials
0021  *    provided with the distribution.
0022  *
0023  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
0024  * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
0025  * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
0026  * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
0027  * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
0028  * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
0029  * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
0030  * SOFTWARE.
0031  */
0032
0033 #ifndef MLX4_CQ_H
0034 #define MLX4_CQ_H
0035
0036 #include <linux/types.h>
0037 #include <uapi/linux/if_ether.h>
0038
0039 #include <linux/mlx4/device.h>
0040 #include <linux/mlx4/doorbell.h>
0041
0042 struct mlx4_cqe {
0043     __be32          vlan_my_qpn;
0044     __be32          immed_rss_invalid;
0045     __be32          g_mlpath_rqpn;
0046     __be16          sl_vid;
0047     union {
0048         struct {
0049             __be16  rlid;
0050             __be16  status;
0051             u8      ipv6_ext_mask;
0052             u8      badfcs_enc;
0053         };
0054         u8  smac[ETH_ALEN];
0055     };
0056     __be32          byte_cnt;
0057     __be16          wqe_index;
0058     __be16          checksum;
0059     u8          reserved[3];
0060     u8          owner_sr_opcode;
0061 };
0062
0063 struct mlx4_err_cqe {
0064     __be32          my_qpn;
0065     u32         reserved1[5];
0066     __be16          wqe_index;
0067     u8          vendor_err_syndrome;
0068     u8          syndrome;
0069     u8          reserved2[3];
0070     u8          owner_sr_opcode;
0071 };
0072
0073 struct mlx4_ts_cqe {
0074     __be32          vlan_my_qpn;
0075     __be32          immed_rss_invalid;
0076     __be32          g_mlpath_rqpn;
0077     __be32          timestamp_hi;
0078     __be16          status;
0079     u8          ipv6_ext_mask;
0080     u8          badfcs_enc;
0081     __be32          byte_cnt;
0082     __be16          wqe_index;
0083     __be16          checksum;
0084     u8          reserved;
0085     __be16          timestamp_lo;
0086     u8          owner_sr_opcode;
0087 } __packed;
0088
0089 enum {
0090     MLX4_CQE_L2_TUNNEL_IPOK     = 1 << 31,
0091     MLX4_CQE_CVLAN_PRESENT_MASK = 1 << 29,
0092     MLX4_CQE_SVLAN_PRESENT_MASK = 1 << 30,
0093     MLX4_CQE_L2_TUNNEL      = 1 << 27,
0094     MLX4_CQE_L2_TUNNEL_CSUM     = 1 << 26,
0095     MLX4_CQE_L2_TUNNEL_IPV4     = 1 << 25,
0096
0097     MLX4_CQE_QPN_MASK       = 0xffffff,
0098     MLX4_CQE_VID_MASK       = 0xfff,
0099 };
0100
0101 enum {
0102     MLX4_CQE_OWNER_MASK = 0x80,
0103     MLX4_CQE_IS_SEND_MASK   = 0x40,
0104     MLX4_CQE_OPCODE_MASK    = 0x1f
0105 };
0106
0107 enum {
0108     MLX4_CQE_SYNDROME_LOCAL_LENGTH_ERR      = 0x01,
0109     MLX4_CQE_SYNDROME_LOCAL_QP_OP_ERR       = 0x02,
0110     MLX4_CQE_SYNDROME_LOCAL_PROT_ERR        = 0x04,
0111     MLX4_CQE_SYNDROME_WR_FLUSH_ERR          = 0x05,
0112     MLX4_CQE_SYNDROME_MW_BIND_ERR           = 0x06,
0113     MLX4_CQE_SYNDROME_BAD_RESP_ERR          = 0x10,
0114     MLX4_CQE_SYNDROME_LOCAL_ACCESS_ERR      = 0x11,
0115     MLX4_CQE_SYNDROME_REMOTE_INVAL_REQ_ERR      = 0x12,
0116     MLX4_CQE_SYNDROME_REMOTE_ACCESS_ERR     = 0x13,
0117     MLX4_CQE_SYNDROME_REMOTE_OP_ERR         = 0x14,
0118     MLX4_CQE_SYNDROME_TRANSPORT_RETRY_EXC_ERR   = 0x15,
0119     MLX4_CQE_SYNDROME_RNR_RETRY_EXC_ERR     = 0x16,
0120     MLX4_CQE_SYNDROME_REMOTE_ABORTED_ERR        = 0x22,
0121 };
0122
0123 enum {
0124     MLX4_CQE_STATUS_IPV4        = 1 << 6,
0125     MLX4_CQE_STATUS_IPV4F       = 1 << 7,
0126     MLX4_CQE_STATUS_IPV6        = 1 << 8,
0127     MLX4_CQE_STATUS_IPV4OPT     = 1 << 9,
0128     MLX4_CQE_STATUS_TCP     = 1 << 10,
0129     MLX4_CQE_STATUS_UDP     = 1 << 11,
0130     MLX4_CQE_STATUS_IPOK        = 1 << 12,
0131 };
0132
0133 /* L4_CSUM is logically part of status, but has to checked against badfcs_enc */
0134 enum {
0135     MLX4_CQE_STATUS_L4_CSUM     = 1 << 2,
0136 };
0137
0138 enum {
0139     MLX4_CQE_LLC                     = 1,
0140     MLX4_CQE_SNAP                    = 1 << 1,
0141     MLX4_CQE_BAD_FCS                 = 1 << 4,
0142 };
0143
0144 #define MLX4_MAX_CQ_PERIOD (BIT(16) - 1)
0145 #define MLX4_MAX_CQ_COUNT (BIT(16) - 1)
0146
0147 static inline void mlx4_cq_arm(struct mlx4_cq *cq, u32 cmd,
0148                    void __iomem *uar_page,
0149                    spinlock_t *doorbell_lock)
0150 {
0151     __be32 doorbell[2];
0152     u32 sn;
0153     u32 ci;
0154
0155     sn = cq->arm_sn & 3;
0156     ci = cq->cons_index & 0xffffff;
0157
0158     *cq->arm_db = cpu_to_be32(sn << 28 | cmd | ci);
0159
0160     /*
0161      * Make sure that the doorbell record in host memory is
0162      * written before ringing the doorbell via PCI MMIO.
0163      */
0164     wmb();
0165
0166     doorbell[0] = cpu_to_be32(sn << 28 | cmd | cq->cqn);
0167     doorbell[1] = cpu_to_be32(ci);
0168
0169     mlx4_write64(doorbell, uar_page + MLX4_CQ_DOORBELL, doorbell_lock);
0170 }
0171
0172 static inline void mlx4_cq_set_ci(struct mlx4_cq *cq)
0173 {
0174     *cq->set_ci_db = cpu_to_be32(cq->cons_index & 0xffffff);
0175 }
0176
0177 enum {
0178     MLX4_CQ_DB_REQ_NOT_SOL      = 1 << 24,
0179     MLX4_CQ_DB_REQ_NOT      = 2 << 24
0180 };
0181
0182 int mlx4_cq_modify(struct mlx4_dev *dev, struct mlx4_cq *cq,
0183            u16 count, u16 period);
0184 int mlx4_cq_resize(struct mlx4_dev *dev, struct mlx4_cq *cq,
0185            int entries, struct mlx4_mtt *mtt);
0186
0187 #endif /* MLX4_CQ_H */