include/linux/microchipphy.h

0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * Copyright (C) 2015 Microchip Technology
0004  */
0005
0006 #ifndef _MICROCHIPPHY_H
0007 #define _MICROCHIPPHY_H
0008
0009 #define LAN88XX_INT_MASK            (0x19)
0010 #define LAN88XX_INT_MASK_MDINTPIN_EN_       (0x8000)
0011 #define LAN88XX_INT_MASK_SPEED_CHANGE_      (0x4000)
0012 #define LAN88XX_INT_MASK_LINK_CHANGE_       (0x2000)
0013 #define LAN88XX_INT_MASK_FDX_CHANGE_        (0x1000)
0014 #define LAN88XX_INT_MASK_AUTONEG_ERR_       (0x0800)
0015 #define LAN88XX_INT_MASK_AUTONEG_DONE_      (0x0400)
0016 #define LAN88XX_INT_MASK_POE_DETECT_        (0x0200)
0017 #define LAN88XX_INT_MASK_SYMBOL_ERR_        (0x0100)
0018 #define LAN88XX_INT_MASK_FAST_LINK_FAIL_    (0x0080)
0019 #define LAN88XX_INT_MASK_WOL_EVENT_     (0x0040)
0020 #define LAN88XX_INT_MASK_EXTENDED_INT_      (0x0020)
0021 #define LAN88XX_INT_MASK_RESERVED_      (0x0010)
0022 #define LAN88XX_INT_MASK_FALSE_CARRIER_     (0x0008)
0023 #define LAN88XX_INT_MASK_LINK_SPEED_DS_     (0x0004)
0024 #define LAN88XX_INT_MASK_MASTER_SLAVE_DONE_ (0x0002)
0025 #define LAN88XX_INT_MASK_RX__ER_        (0x0001)
0026
0027 #define LAN88XX_INT_STS             (0x1A)
0028 #define LAN88XX_INT_STS_INT_ACTIVE_     (0x8000)
0029 #define LAN88XX_INT_STS_SPEED_CHANGE_       (0x4000)
0030 #define LAN88XX_INT_STS_LINK_CHANGE_        (0x2000)
0031 #define LAN88XX_INT_STS_FDX_CHANGE_     (0x1000)
0032 #define LAN88XX_INT_STS_AUTONEG_ERR_        (0x0800)
0033 #define LAN88XX_INT_STS_AUTONEG_DONE_       (0x0400)
0034 #define LAN88XX_INT_STS_POE_DETECT_     (0x0200)
0035 #define LAN88XX_INT_STS_SYMBOL_ERR_     (0x0100)
0036 #define LAN88XX_INT_STS_FAST_LINK_FAIL_     (0x0080)
0037 #define LAN88XX_INT_STS_WOL_EVENT_      (0x0040)
0038 #define LAN88XX_INT_STS_EXTENDED_INT_       (0x0020)
0039 #define LAN88XX_INT_STS_RESERVED_       (0x0010)
0040 #define LAN88XX_INT_STS_FALSE_CARRIER_      (0x0008)
0041 #define LAN88XX_INT_STS_LINK_SPEED_DS_      (0x0004)
0042 #define LAN88XX_INT_STS_MASTER_SLAVE_DONE_  (0x0002)
0043 #define LAN88XX_INT_STS_RX_ER_          (0x0001)
0044
0045 #define LAN88XX_EXT_PAGE_ACCESS         (0x1F)
0046 #define LAN88XX_EXT_PAGE_SPACE_0        (0x0000)
0047 #define LAN88XX_EXT_PAGE_SPACE_1        (0x0001)
0048 #define LAN88XX_EXT_PAGE_SPACE_2        (0x0002)
0049
0050 /* Extended Register Page 1 space */
0051 #define LAN88XX_EXT_MODE_CTRL           (0x13)
0052 #define LAN88XX_EXT_MODE_CTRL_MDIX_MASK_    (0x000C)
0053 #define LAN88XX_EXT_MODE_CTRL_AUTO_MDIX_    (0x0000)
0054 #define LAN88XX_EXT_MODE_CTRL_MDI_      (0x0008)
0055 #define LAN88XX_EXT_MODE_CTRL_MDI_X_        (0x000C)
0056
0057 /* MMD 3 Registers */
0058 #define LAN88XX_MMD3_CHIP_ID            (32877)
0059 #define LAN88XX_MMD3_CHIP_REV           (32878)
0060
0061 /* Registers specific to the LAN7800/LAN7850 embedded phy */
0062 #define LAN78XX_PHY_LED_MODE_SELECT     (0x1D)
0063
0064 /* DSP registers */
0065 #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG      (0x806A)
0066 #define PHY_ARDENNES_MMD_DEV_3_PHY_CFG_ZD_DLY_EN_   (0x2000)
0067 #define LAN88XX_EXT_PAGE_ACCESS_TR      (0x52B5)
0068 #define LAN88XX_EXT_PAGE_TR_CR          16
0069 #define LAN88XX_EXT_PAGE_TR_LOW_DATA        17
0070 #define LAN88XX_EXT_PAGE_TR_HIGH_DATA       18
0071
0072 #endif /* _MICROCHIPPHY_H */