Back to home page

OSCL-LXR

 
 

    


0001 /* SPDX-License-Identifier: GPL-2.0-or-later */
0002 /*
0003  * include/linux/mfd/wm831x/irq.h -- Interrupt controller for WM831x
0004  *
0005  * Copyright 2009 Wolfson Microelectronics PLC.
0006  *
0007  * Author: Mark Brown <broonie@opensource.wolfsonmicro.com>
0008  */
0009 
0010 #ifndef __MFD_WM831X_IRQ_H__
0011 #define __MFD_WM831X_IRQ_H__
0012 
0013 /* Interrupt number assignments within Linux */
0014 #define WM831X_IRQ_TEMP_THW 0
0015 #define WM831X_IRQ_GPIO_1   1
0016 #define WM831X_IRQ_GPIO_2   2
0017 #define WM831X_IRQ_GPIO_3   3
0018 #define WM831X_IRQ_GPIO_4   4
0019 #define WM831X_IRQ_GPIO_5   5
0020 #define WM831X_IRQ_GPIO_6   6
0021 #define WM831X_IRQ_GPIO_7   7
0022 #define WM831X_IRQ_GPIO_8   8
0023 #define WM831X_IRQ_GPIO_9   9
0024 #define WM831X_IRQ_GPIO_10  10
0025 #define WM831X_IRQ_GPIO_11  11
0026 #define WM831X_IRQ_GPIO_12  12
0027 #define WM831X_IRQ_GPIO_13  13
0028 #define WM831X_IRQ_GPIO_14  14
0029 #define WM831X_IRQ_GPIO_15  15
0030 #define WM831X_IRQ_GPIO_16  16
0031 #define WM831X_IRQ_ON           17
0032 #define WM831X_IRQ_PPM_SYSLO    18
0033 #define WM831X_IRQ_PPM_PWR_SRC  19
0034 #define WM831X_IRQ_PPM_USB_CURR 20
0035 #define WM831X_IRQ_WDOG_TO      21
0036 #define WM831X_IRQ_RTC_PER      22
0037 #define WM831X_IRQ_RTC_ALM      23
0038 #define WM831X_IRQ_CHG_BATT_HOT  24
0039 #define WM831X_IRQ_CHG_BATT_COLD 25
0040 #define WM831X_IRQ_CHG_BATT_FAIL 26
0041 #define WM831X_IRQ_CHG_OV        27
0042 #define WM831X_IRQ_CHG_END       29
0043 #define WM831X_IRQ_CHG_TO        30
0044 #define WM831X_IRQ_CHG_MODE      31
0045 #define WM831X_IRQ_CHG_START     32
0046 #define WM831X_IRQ_TCHDATA       33
0047 #define WM831X_IRQ_TCHPD         34
0048 #define WM831X_IRQ_AUXADC_DATA   35
0049 #define WM831X_IRQ_AUXADC_DCOMP1 36
0050 #define WM831X_IRQ_AUXADC_DCOMP2 37
0051 #define WM831X_IRQ_AUXADC_DCOMP3 38
0052 #define WM831X_IRQ_AUXADC_DCOMP4 39
0053 #define WM831X_IRQ_CS1           40
0054 #define WM831X_IRQ_CS2           41
0055 #define WM831X_IRQ_HC_DC1        42
0056 #define WM831X_IRQ_HC_DC2        43
0057 #define WM831X_IRQ_UV_LDO1       44
0058 #define WM831X_IRQ_UV_LDO2       45
0059 #define WM831X_IRQ_UV_LDO3       46
0060 #define WM831X_IRQ_UV_LDO4       47
0061 #define WM831X_IRQ_UV_LDO5       48
0062 #define WM831X_IRQ_UV_LDO6       49
0063 #define WM831X_IRQ_UV_LDO7       50
0064 #define WM831X_IRQ_UV_LDO8       51
0065 #define WM831X_IRQ_UV_LDO9       52
0066 #define WM831X_IRQ_UV_LDO10      53
0067 #define WM831X_IRQ_UV_DC1        54
0068 #define WM831X_IRQ_UV_DC2        55
0069 #define WM831X_IRQ_UV_DC3        56
0070 #define WM831X_IRQ_UV_DC4        57
0071 
0072 #define WM831X_NUM_IRQS     58
0073 
0074 /*
0075  * R16400 (0x4010) - System Interrupts
0076  */
0077 #define WM831X_PS_INT                           0x8000  /* PS_INT */
0078 #define WM831X_PS_INT_MASK                      0x8000  /* PS_INT */
0079 #define WM831X_PS_INT_SHIFT                         15  /* PS_INT */
0080 #define WM831X_PS_INT_WIDTH                          1  /* PS_INT */
0081 #define WM831X_TEMP_INT                         0x4000  /* TEMP_INT */
0082 #define WM831X_TEMP_INT_MASK                    0x4000  /* TEMP_INT */
0083 #define WM831X_TEMP_INT_SHIFT                       14  /* TEMP_INT */
0084 #define WM831X_TEMP_INT_WIDTH                        1  /* TEMP_INT */
0085 #define WM831X_GP_INT                           0x2000  /* GP_INT */
0086 #define WM831X_GP_INT_MASK                      0x2000  /* GP_INT */
0087 #define WM831X_GP_INT_SHIFT                         13  /* GP_INT */
0088 #define WM831X_GP_INT_WIDTH                          1  /* GP_INT */
0089 #define WM831X_ON_PIN_INT                       0x1000  /* ON_PIN_INT */
0090 #define WM831X_ON_PIN_INT_MASK                  0x1000  /* ON_PIN_INT */
0091 #define WM831X_ON_PIN_INT_SHIFT                     12  /* ON_PIN_INT */
0092 #define WM831X_ON_PIN_INT_WIDTH                      1  /* ON_PIN_INT */
0093 #define WM831X_WDOG_INT                         0x0800  /* WDOG_INT */
0094 #define WM831X_WDOG_INT_MASK                    0x0800  /* WDOG_INT */
0095 #define WM831X_WDOG_INT_SHIFT                       11  /* WDOG_INT */
0096 #define WM831X_WDOG_INT_WIDTH                        1  /* WDOG_INT */
0097 #define WM831X_TCHDATA_INT                      0x0400  /* TCHDATA_INT */
0098 #define WM831X_TCHDATA_INT_MASK                 0x0400  /* TCHDATA_INT */
0099 #define WM831X_TCHDATA_INT_SHIFT                    10  /* TCHDATA_INT */
0100 #define WM831X_TCHDATA_INT_WIDTH                     1  /* TCHDATA_INT */
0101 #define WM831X_TCHPD_INT                        0x0200  /* TCHPD_INT */
0102 #define WM831X_TCHPD_INT_MASK                   0x0200  /* TCHPD_INT */
0103 #define WM831X_TCHPD_INT_SHIFT                       9  /* TCHPD_INT */
0104 #define WM831X_TCHPD_INT_WIDTH                       1  /* TCHPD_INT */
0105 #define WM831X_AUXADC_INT                       0x0100  /* AUXADC_INT */
0106 #define WM831X_AUXADC_INT_MASK                  0x0100  /* AUXADC_INT */
0107 #define WM831X_AUXADC_INT_SHIFT                      8  /* AUXADC_INT */
0108 #define WM831X_AUXADC_INT_WIDTH                      1  /* AUXADC_INT */
0109 #define WM831X_PPM_INT                          0x0080  /* PPM_INT */
0110 #define WM831X_PPM_INT_MASK                     0x0080  /* PPM_INT */
0111 #define WM831X_PPM_INT_SHIFT                         7  /* PPM_INT */
0112 #define WM831X_PPM_INT_WIDTH                         1  /* PPM_INT */
0113 #define WM831X_CS_INT                           0x0040  /* CS_INT */
0114 #define WM831X_CS_INT_MASK                      0x0040  /* CS_INT */
0115 #define WM831X_CS_INT_SHIFT                          6  /* CS_INT */
0116 #define WM831X_CS_INT_WIDTH                          1  /* CS_INT */
0117 #define WM831X_RTC_INT                          0x0020  /* RTC_INT */
0118 #define WM831X_RTC_INT_MASK                     0x0020  /* RTC_INT */
0119 #define WM831X_RTC_INT_SHIFT                         5  /* RTC_INT */
0120 #define WM831X_RTC_INT_WIDTH                         1  /* RTC_INT */
0121 #define WM831X_OTP_INT                          0x0010  /* OTP_INT */
0122 #define WM831X_OTP_INT_MASK                     0x0010  /* OTP_INT */
0123 #define WM831X_OTP_INT_SHIFT                         4  /* OTP_INT */
0124 #define WM831X_OTP_INT_WIDTH                         1  /* OTP_INT */
0125 #define WM831X_CHILD_INT                        0x0008  /* CHILD_INT */
0126 #define WM831X_CHILD_INT_MASK                   0x0008  /* CHILD_INT */
0127 #define WM831X_CHILD_INT_SHIFT                       3  /* CHILD_INT */
0128 #define WM831X_CHILD_INT_WIDTH                       1  /* CHILD_INT */
0129 #define WM831X_CHG_INT                          0x0004  /* CHG_INT */
0130 #define WM831X_CHG_INT_MASK                     0x0004  /* CHG_INT */
0131 #define WM831X_CHG_INT_SHIFT                         2  /* CHG_INT */
0132 #define WM831X_CHG_INT_WIDTH                         1  /* CHG_INT */
0133 #define WM831X_HC_INT                           0x0002  /* HC_INT */
0134 #define WM831X_HC_INT_MASK                      0x0002  /* HC_INT */
0135 #define WM831X_HC_INT_SHIFT                          1  /* HC_INT */
0136 #define WM831X_HC_INT_WIDTH                          1  /* HC_INT */
0137 #define WM831X_UV_INT                           0x0001  /* UV_INT */
0138 #define WM831X_UV_INT_MASK                      0x0001  /* UV_INT */
0139 #define WM831X_UV_INT_SHIFT                          0  /* UV_INT */
0140 #define WM831X_UV_INT_WIDTH                          1  /* UV_INT */
0141 
0142 /*
0143  * R16401 (0x4011) - Interrupt Status 1
0144  */
0145 #define WM831X_PPM_SYSLO_EINT                   0x8000  /* PPM_SYSLO_EINT */
0146 #define WM831X_PPM_SYSLO_EINT_MASK              0x8000  /* PPM_SYSLO_EINT */
0147 #define WM831X_PPM_SYSLO_EINT_SHIFT                 15  /* PPM_SYSLO_EINT */
0148 #define WM831X_PPM_SYSLO_EINT_WIDTH                  1  /* PPM_SYSLO_EINT */
0149 #define WM831X_PPM_PWR_SRC_EINT                 0x4000  /* PPM_PWR_SRC_EINT */
0150 #define WM831X_PPM_PWR_SRC_EINT_MASK            0x4000  /* PPM_PWR_SRC_EINT */
0151 #define WM831X_PPM_PWR_SRC_EINT_SHIFT               14  /* PPM_PWR_SRC_EINT */
0152 #define WM831X_PPM_PWR_SRC_EINT_WIDTH                1  /* PPM_PWR_SRC_EINT */
0153 #define WM831X_PPM_USB_CURR_EINT                0x2000  /* PPM_USB_CURR_EINT */
0154 #define WM831X_PPM_USB_CURR_EINT_MASK           0x2000  /* PPM_USB_CURR_EINT */
0155 #define WM831X_PPM_USB_CURR_EINT_SHIFT              13  /* PPM_USB_CURR_EINT */
0156 #define WM831X_PPM_USB_CURR_EINT_WIDTH               1  /* PPM_USB_CURR_EINT */
0157 #define WM831X_ON_PIN_EINT                      0x1000  /* ON_PIN_EINT */
0158 #define WM831X_ON_PIN_EINT_MASK                 0x1000  /* ON_PIN_EINT */
0159 #define WM831X_ON_PIN_EINT_SHIFT                    12  /* ON_PIN_EINT */
0160 #define WM831X_ON_PIN_EINT_WIDTH                     1  /* ON_PIN_EINT */
0161 #define WM831X_WDOG_TO_EINT                     0x0800  /* WDOG_TO_EINT */
0162 #define WM831X_WDOG_TO_EINT_MASK                0x0800  /* WDOG_TO_EINT */
0163 #define WM831X_WDOG_TO_EINT_SHIFT                   11  /* WDOG_TO_EINT */
0164 #define WM831X_WDOG_TO_EINT_WIDTH                    1  /* WDOG_TO_EINT */
0165 #define WM831X_TCHDATA_EINT                     0x0400  /* TCHDATA_EINT */
0166 #define WM831X_TCHDATA_EINT_MASK                0x0400  /* TCHDATA_EINT */
0167 #define WM831X_TCHDATA_EINT_SHIFT                   10  /* TCHDATA_EINT */
0168 #define WM831X_TCHDATA_EINT_WIDTH                    1  /* TCHDATA_EINT */
0169 #define WM831X_TCHPD_EINT                       0x0200  /* TCHPD_EINT */
0170 #define WM831X_TCHPD_EINT_MASK                  0x0200  /* TCHPD_EINT */
0171 #define WM831X_TCHPD_EINT_SHIFT                      9  /* TCHPD_EINT */
0172 #define WM831X_TCHPD_EINT_WIDTH                      1  /* TCHPD_EINT */
0173 #define WM831X_AUXADC_DATA_EINT                 0x0100  /* AUXADC_DATA_EINT */
0174 #define WM831X_AUXADC_DATA_EINT_MASK            0x0100  /* AUXADC_DATA_EINT */
0175 #define WM831X_AUXADC_DATA_EINT_SHIFT                8  /* AUXADC_DATA_EINT */
0176 #define WM831X_AUXADC_DATA_EINT_WIDTH                1  /* AUXADC_DATA_EINT */
0177 #define WM831X_AUXADC_DCOMP4_EINT               0x0080  /* AUXADC_DCOMP4_EINT */
0178 #define WM831X_AUXADC_DCOMP4_EINT_MASK          0x0080  /* AUXADC_DCOMP4_EINT */
0179 #define WM831X_AUXADC_DCOMP4_EINT_SHIFT              7  /* AUXADC_DCOMP4_EINT */
0180 #define WM831X_AUXADC_DCOMP4_EINT_WIDTH              1  /* AUXADC_DCOMP4_EINT */
0181 #define WM831X_AUXADC_DCOMP3_EINT               0x0040  /* AUXADC_DCOMP3_EINT */
0182 #define WM831X_AUXADC_DCOMP3_EINT_MASK          0x0040  /* AUXADC_DCOMP3_EINT */
0183 #define WM831X_AUXADC_DCOMP3_EINT_SHIFT              6  /* AUXADC_DCOMP3_EINT */
0184 #define WM831X_AUXADC_DCOMP3_EINT_WIDTH              1  /* AUXADC_DCOMP3_EINT */
0185 #define WM831X_AUXADC_DCOMP2_EINT               0x0020  /* AUXADC_DCOMP2_EINT */
0186 #define WM831X_AUXADC_DCOMP2_EINT_MASK          0x0020  /* AUXADC_DCOMP2_EINT */
0187 #define WM831X_AUXADC_DCOMP2_EINT_SHIFT              5  /* AUXADC_DCOMP2_EINT */
0188 #define WM831X_AUXADC_DCOMP2_EINT_WIDTH              1  /* AUXADC_DCOMP2_EINT */
0189 #define WM831X_AUXADC_DCOMP1_EINT               0x0010  /* AUXADC_DCOMP1_EINT */
0190 #define WM831X_AUXADC_DCOMP1_EINT_MASK          0x0010  /* AUXADC_DCOMP1_EINT */
0191 #define WM831X_AUXADC_DCOMP1_EINT_SHIFT              4  /* AUXADC_DCOMP1_EINT */
0192 #define WM831X_AUXADC_DCOMP1_EINT_WIDTH              1  /* AUXADC_DCOMP1_EINT */
0193 #define WM831X_RTC_PER_EINT                     0x0008  /* RTC_PER_EINT */
0194 #define WM831X_RTC_PER_EINT_MASK                0x0008  /* RTC_PER_EINT */
0195 #define WM831X_RTC_PER_EINT_SHIFT                    3  /* RTC_PER_EINT */
0196 #define WM831X_RTC_PER_EINT_WIDTH                    1  /* RTC_PER_EINT */
0197 #define WM831X_RTC_ALM_EINT                     0x0004  /* RTC_ALM_EINT */
0198 #define WM831X_RTC_ALM_EINT_MASK                0x0004  /* RTC_ALM_EINT */
0199 #define WM831X_RTC_ALM_EINT_SHIFT                    2  /* RTC_ALM_EINT */
0200 #define WM831X_RTC_ALM_EINT_WIDTH                    1  /* RTC_ALM_EINT */
0201 #define WM831X_TEMP_THW_EINT                    0x0002  /* TEMP_THW_EINT */
0202 #define WM831X_TEMP_THW_EINT_MASK               0x0002  /* TEMP_THW_EINT */
0203 #define WM831X_TEMP_THW_EINT_SHIFT                   1  /* TEMP_THW_EINT */
0204 #define WM831X_TEMP_THW_EINT_WIDTH                   1  /* TEMP_THW_EINT */
0205 
0206 /*
0207  * R16402 (0x4012) - Interrupt Status 2
0208  */
0209 #define WM831X_CHG_BATT_HOT_EINT                0x8000  /* CHG_BATT_HOT_EINT */
0210 #define WM831X_CHG_BATT_HOT_EINT_MASK           0x8000  /* CHG_BATT_HOT_EINT */
0211 #define WM831X_CHG_BATT_HOT_EINT_SHIFT              15  /* CHG_BATT_HOT_EINT */
0212 #define WM831X_CHG_BATT_HOT_EINT_WIDTH               1  /* CHG_BATT_HOT_EINT */
0213 #define WM831X_CHG_BATT_COLD_EINT               0x4000  /* CHG_BATT_COLD_EINT */
0214 #define WM831X_CHG_BATT_COLD_EINT_MASK          0x4000  /* CHG_BATT_COLD_EINT */
0215 #define WM831X_CHG_BATT_COLD_EINT_SHIFT             14  /* CHG_BATT_COLD_EINT */
0216 #define WM831X_CHG_BATT_COLD_EINT_WIDTH              1  /* CHG_BATT_COLD_EINT */
0217 #define WM831X_CHG_BATT_FAIL_EINT               0x2000  /* CHG_BATT_FAIL_EINT */
0218 #define WM831X_CHG_BATT_FAIL_EINT_MASK          0x2000  /* CHG_BATT_FAIL_EINT */
0219 #define WM831X_CHG_BATT_FAIL_EINT_SHIFT             13  /* CHG_BATT_FAIL_EINT */
0220 #define WM831X_CHG_BATT_FAIL_EINT_WIDTH              1  /* CHG_BATT_FAIL_EINT */
0221 #define WM831X_CHG_OV_EINT                      0x1000  /* CHG_OV_EINT */
0222 #define WM831X_CHG_OV_EINT_MASK                 0x1000  /* CHG_OV_EINT */
0223 #define WM831X_CHG_OV_EINT_SHIFT                    12  /* CHG_OV_EINT */
0224 #define WM831X_CHG_OV_EINT_WIDTH                     1  /* CHG_OV_EINT */
0225 #define WM831X_CHG_END_EINT                     0x0800  /* CHG_END_EINT */
0226 #define WM831X_CHG_END_EINT_MASK                0x0800  /* CHG_END_EINT */
0227 #define WM831X_CHG_END_EINT_SHIFT                   11  /* CHG_END_EINT */
0228 #define WM831X_CHG_END_EINT_WIDTH                    1  /* CHG_END_EINT */
0229 #define WM831X_CHG_TO_EINT                      0x0400  /* CHG_TO_EINT */
0230 #define WM831X_CHG_TO_EINT_MASK                 0x0400  /* CHG_TO_EINT */
0231 #define WM831X_CHG_TO_EINT_SHIFT                    10  /* CHG_TO_EINT */
0232 #define WM831X_CHG_TO_EINT_WIDTH                     1  /* CHG_TO_EINT */
0233 #define WM831X_CHG_MODE_EINT                    0x0200  /* CHG_MODE_EINT */
0234 #define WM831X_CHG_MODE_EINT_MASK               0x0200  /* CHG_MODE_EINT */
0235 #define WM831X_CHG_MODE_EINT_SHIFT                   9  /* CHG_MODE_EINT */
0236 #define WM831X_CHG_MODE_EINT_WIDTH                   1  /* CHG_MODE_EINT */
0237 #define WM831X_CHG_START_EINT                   0x0100  /* CHG_START_EINT */
0238 #define WM831X_CHG_START_EINT_MASK              0x0100  /* CHG_START_EINT */
0239 #define WM831X_CHG_START_EINT_SHIFT                  8  /* CHG_START_EINT */
0240 #define WM831X_CHG_START_EINT_WIDTH                  1  /* CHG_START_EINT */
0241 #define WM831X_CS2_EINT                         0x0080  /* CS2_EINT */
0242 #define WM831X_CS2_EINT_MASK                    0x0080  /* CS2_EINT */
0243 #define WM831X_CS2_EINT_SHIFT                        7  /* CS2_EINT */
0244 #define WM831X_CS2_EINT_WIDTH                        1  /* CS2_EINT */
0245 #define WM831X_CS1_EINT                         0x0040  /* CS1_EINT */
0246 #define WM831X_CS1_EINT_MASK                    0x0040  /* CS1_EINT */
0247 #define WM831X_CS1_EINT_SHIFT                        6  /* CS1_EINT */
0248 #define WM831X_CS1_EINT_WIDTH                        1  /* CS1_EINT */
0249 #define WM831X_OTP_CMD_END_EINT                 0x0020  /* OTP_CMD_END_EINT */
0250 #define WM831X_OTP_CMD_END_EINT_MASK            0x0020  /* OTP_CMD_END_EINT */
0251 #define WM831X_OTP_CMD_END_EINT_SHIFT                5  /* OTP_CMD_END_EINT */
0252 #define WM831X_OTP_CMD_END_EINT_WIDTH                1  /* OTP_CMD_END_EINT */
0253 #define WM831X_OTP_ERR_EINT                     0x0010  /* OTP_ERR_EINT */
0254 #define WM831X_OTP_ERR_EINT_MASK                0x0010  /* OTP_ERR_EINT */
0255 #define WM831X_OTP_ERR_EINT_SHIFT                    4  /* OTP_ERR_EINT */
0256 #define WM831X_OTP_ERR_EINT_WIDTH                    1  /* OTP_ERR_EINT */
0257 #define WM831X_PS_POR_EINT                      0x0004  /* PS_POR_EINT */
0258 #define WM831X_PS_POR_EINT_MASK                 0x0004  /* PS_POR_EINT */
0259 #define WM831X_PS_POR_EINT_SHIFT                     2  /* PS_POR_EINT */
0260 #define WM831X_PS_POR_EINT_WIDTH                     1  /* PS_POR_EINT */
0261 #define WM831X_PS_SLEEP_OFF_EINT                0x0002  /* PS_SLEEP_OFF_EINT */
0262 #define WM831X_PS_SLEEP_OFF_EINT_MASK           0x0002  /* PS_SLEEP_OFF_EINT */
0263 #define WM831X_PS_SLEEP_OFF_EINT_SHIFT               1  /* PS_SLEEP_OFF_EINT */
0264 #define WM831X_PS_SLEEP_OFF_EINT_WIDTH               1  /* PS_SLEEP_OFF_EINT */
0265 #define WM831X_PS_ON_WAKE_EINT                  0x0001  /* PS_ON_WAKE_EINT */
0266 #define WM831X_PS_ON_WAKE_EINT_MASK             0x0001  /* PS_ON_WAKE_EINT */
0267 #define WM831X_PS_ON_WAKE_EINT_SHIFT                 0  /* PS_ON_WAKE_EINT */
0268 #define WM831X_PS_ON_WAKE_EINT_WIDTH                 1  /* PS_ON_WAKE_EINT */
0269 
0270 /*
0271  * R16403 (0x4013) - Interrupt Status 3
0272  */
0273 #define WM831X_UV_LDO10_EINT                    0x0200  /* UV_LDO10_EINT */
0274 #define WM831X_UV_LDO10_EINT_MASK               0x0200  /* UV_LDO10_EINT */
0275 #define WM831X_UV_LDO10_EINT_SHIFT                   9  /* UV_LDO10_EINT */
0276 #define WM831X_UV_LDO10_EINT_WIDTH                   1  /* UV_LDO10_EINT */
0277 #define WM831X_UV_LDO9_EINT                     0x0100  /* UV_LDO9_EINT */
0278 #define WM831X_UV_LDO9_EINT_MASK                0x0100  /* UV_LDO9_EINT */
0279 #define WM831X_UV_LDO9_EINT_SHIFT                    8  /* UV_LDO9_EINT */
0280 #define WM831X_UV_LDO9_EINT_WIDTH                    1  /* UV_LDO9_EINT */
0281 #define WM831X_UV_LDO8_EINT                     0x0080  /* UV_LDO8_EINT */
0282 #define WM831X_UV_LDO8_EINT_MASK                0x0080  /* UV_LDO8_EINT */
0283 #define WM831X_UV_LDO8_EINT_SHIFT                    7  /* UV_LDO8_EINT */
0284 #define WM831X_UV_LDO8_EINT_WIDTH                    1  /* UV_LDO8_EINT */
0285 #define WM831X_UV_LDO7_EINT                     0x0040  /* UV_LDO7_EINT */
0286 #define WM831X_UV_LDO7_EINT_MASK                0x0040  /* UV_LDO7_EINT */
0287 #define WM831X_UV_LDO7_EINT_SHIFT                    6  /* UV_LDO7_EINT */
0288 #define WM831X_UV_LDO7_EINT_WIDTH                    1  /* UV_LDO7_EINT */
0289 #define WM831X_UV_LDO6_EINT                     0x0020  /* UV_LDO6_EINT */
0290 #define WM831X_UV_LDO6_EINT_MASK                0x0020  /* UV_LDO6_EINT */
0291 #define WM831X_UV_LDO6_EINT_SHIFT                    5  /* UV_LDO6_EINT */
0292 #define WM831X_UV_LDO6_EINT_WIDTH                    1  /* UV_LDO6_EINT */
0293 #define WM831X_UV_LDO5_EINT                     0x0010  /* UV_LDO5_EINT */
0294 #define WM831X_UV_LDO5_EINT_MASK                0x0010  /* UV_LDO5_EINT */
0295 #define WM831X_UV_LDO5_EINT_SHIFT                    4  /* UV_LDO5_EINT */
0296 #define WM831X_UV_LDO5_EINT_WIDTH                    1  /* UV_LDO5_EINT */
0297 #define WM831X_UV_LDO4_EINT                     0x0008  /* UV_LDO4_EINT */
0298 #define WM831X_UV_LDO4_EINT_MASK                0x0008  /* UV_LDO4_EINT */
0299 #define WM831X_UV_LDO4_EINT_SHIFT                    3  /* UV_LDO4_EINT */
0300 #define WM831X_UV_LDO4_EINT_WIDTH                    1  /* UV_LDO4_EINT */
0301 #define WM831X_UV_LDO3_EINT                     0x0004  /* UV_LDO3_EINT */
0302 #define WM831X_UV_LDO3_EINT_MASK                0x0004  /* UV_LDO3_EINT */
0303 #define WM831X_UV_LDO3_EINT_SHIFT                    2  /* UV_LDO3_EINT */
0304 #define WM831X_UV_LDO3_EINT_WIDTH                    1  /* UV_LDO3_EINT */
0305 #define WM831X_UV_LDO2_EINT                     0x0002  /* UV_LDO2_EINT */
0306 #define WM831X_UV_LDO2_EINT_MASK                0x0002  /* UV_LDO2_EINT */
0307 #define WM831X_UV_LDO2_EINT_SHIFT                    1  /* UV_LDO2_EINT */
0308 #define WM831X_UV_LDO2_EINT_WIDTH                    1  /* UV_LDO2_EINT */
0309 #define WM831X_UV_LDO1_EINT                     0x0001  /* UV_LDO1_EINT */
0310 #define WM831X_UV_LDO1_EINT_MASK                0x0001  /* UV_LDO1_EINT */
0311 #define WM831X_UV_LDO1_EINT_SHIFT                    0  /* UV_LDO1_EINT */
0312 #define WM831X_UV_LDO1_EINT_WIDTH                    1  /* UV_LDO1_EINT */
0313 
0314 /*
0315  * R16404 (0x4014) - Interrupt Status 4
0316  */
0317 #define WM831X_HC_DC2_EINT                      0x0200  /* HC_DC2_EINT */
0318 #define WM831X_HC_DC2_EINT_MASK                 0x0200  /* HC_DC2_EINT */
0319 #define WM831X_HC_DC2_EINT_SHIFT                     9  /* HC_DC2_EINT */
0320 #define WM831X_HC_DC2_EINT_WIDTH                     1  /* HC_DC2_EINT */
0321 #define WM831X_HC_DC1_EINT                      0x0100  /* HC_DC1_EINT */
0322 #define WM831X_HC_DC1_EINT_MASK                 0x0100  /* HC_DC1_EINT */
0323 #define WM831X_HC_DC1_EINT_SHIFT                     8  /* HC_DC1_EINT */
0324 #define WM831X_HC_DC1_EINT_WIDTH                     1  /* HC_DC1_EINT */
0325 #define WM831X_UV_DC4_EINT                      0x0008  /* UV_DC4_EINT */
0326 #define WM831X_UV_DC4_EINT_MASK                 0x0008  /* UV_DC4_EINT */
0327 #define WM831X_UV_DC4_EINT_SHIFT                     3  /* UV_DC4_EINT */
0328 #define WM831X_UV_DC4_EINT_WIDTH                     1  /* UV_DC4_EINT */
0329 #define WM831X_UV_DC3_EINT                      0x0004  /* UV_DC3_EINT */
0330 #define WM831X_UV_DC3_EINT_MASK                 0x0004  /* UV_DC3_EINT */
0331 #define WM831X_UV_DC3_EINT_SHIFT                     2  /* UV_DC3_EINT */
0332 #define WM831X_UV_DC3_EINT_WIDTH                     1  /* UV_DC3_EINT */
0333 #define WM831X_UV_DC2_EINT                      0x0002  /* UV_DC2_EINT */
0334 #define WM831X_UV_DC2_EINT_MASK                 0x0002  /* UV_DC2_EINT */
0335 #define WM831X_UV_DC2_EINT_SHIFT                     1  /* UV_DC2_EINT */
0336 #define WM831X_UV_DC2_EINT_WIDTH                     1  /* UV_DC2_EINT */
0337 #define WM831X_UV_DC1_EINT                      0x0001  /* UV_DC1_EINT */
0338 #define WM831X_UV_DC1_EINT_MASK                 0x0001  /* UV_DC1_EINT */
0339 #define WM831X_UV_DC1_EINT_SHIFT                     0  /* UV_DC1_EINT */
0340 #define WM831X_UV_DC1_EINT_WIDTH                     1  /* UV_DC1_EINT */
0341 
0342 /*
0343  * R16405 (0x4015) - Interrupt Status 5
0344  */
0345 #define WM831X_GP16_EINT                        0x8000  /* GP16_EINT */
0346 #define WM831X_GP16_EINT_MASK                   0x8000  /* GP16_EINT */
0347 #define WM831X_GP16_EINT_SHIFT                      15  /* GP16_EINT */
0348 #define WM831X_GP16_EINT_WIDTH                       1  /* GP16_EINT */
0349 #define WM831X_GP15_EINT                        0x4000  /* GP15_EINT */
0350 #define WM831X_GP15_EINT_MASK                   0x4000  /* GP15_EINT */
0351 #define WM831X_GP15_EINT_SHIFT                      14  /* GP15_EINT */
0352 #define WM831X_GP15_EINT_WIDTH                       1  /* GP15_EINT */
0353 #define WM831X_GP14_EINT                        0x2000  /* GP14_EINT */
0354 #define WM831X_GP14_EINT_MASK                   0x2000  /* GP14_EINT */
0355 #define WM831X_GP14_EINT_SHIFT                      13  /* GP14_EINT */
0356 #define WM831X_GP14_EINT_WIDTH                       1  /* GP14_EINT */
0357 #define WM831X_GP13_EINT                        0x1000  /* GP13_EINT */
0358 #define WM831X_GP13_EINT_MASK                   0x1000  /* GP13_EINT */
0359 #define WM831X_GP13_EINT_SHIFT                      12  /* GP13_EINT */
0360 #define WM831X_GP13_EINT_WIDTH                       1  /* GP13_EINT */
0361 #define WM831X_GP12_EINT                        0x0800  /* GP12_EINT */
0362 #define WM831X_GP12_EINT_MASK                   0x0800  /* GP12_EINT */
0363 #define WM831X_GP12_EINT_SHIFT                      11  /* GP12_EINT */
0364 #define WM831X_GP12_EINT_WIDTH                       1  /* GP12_EINT */
0365 #define WM831X_GP11_EINT                        0x0400  /* GP11_EINT */
0366 #define WM831X_GP11_EINT_MASK                   0x0400  /* GP11_EINT */
0367 #define WM831X_GP11_EINT_SHIFT                      10  /* GP11_EINT */
0368 #define WM831X_GP11_EINT_WIDTH                       1  /* GP11_EINT */
0369 #define WM831X_GP10_EINT                        0x0200  /* GP10_EINT */
0370 #define WM831X_GP10_EINT_MASK                   0x0200  /* GP10_EINT */
0371 #define WM831X_GP10_EINT_SHIFT                       9  /* GP10_EINT */
0372 #define WM831X_GP10_EINT_WIDTH                       1  /* GP10_EINT */
0373 #define WM831X_GP9_EINT                         0x0100  /* GP9_EINT */
0374 #define WM831X_GP9_EINT_MASK                    0x0100  /* GP9_EINT */
0375 #define WM831X_GP9_EINT_SHIFT                        8  /* GP9_EINT */
0376 #define WM831X_GP9_EINT_WIDTH                        1  /* GP9_EINT */
0377 #define WM831X_GP8_EINT                         0x0080  /* GP8_EINT */
0378 #define WM831X_GP8_EINT_MASK                    0x0080  /* GP8_EINT */
0379 #define WM831X_GP8_EINT_SHIFT                        7  /* GP8_EINT */
0380 #define WM831X_GP8_EINT_WIDTH                        1  /* GP8_EINT */
0381 #define WM831X_GP7_EINT                         0x0040  /* GP7_EINT */
0382 #define WM831X_GP7_EINT_MASK                    0x0040  /* GP7_EINT */
0383 #define WM831X_GP7_EINT_SHIFT                        6  /* GP7_EINT */
0384 #define WM831X_GP7_EINT_WIDTH                        1  /* GP7_EINT */
0385 #define WM831X_GP6_EINT                         0x0020  /* GP6_EINT */
0386 #define WM831X_GP6_EINT_MASK                    0x0020  /* GP6_EINT */
0387 #define WM831X_GP6_EINT_SHIFT                        5  /* GP6_EINT */
0388 #define WM831X_GP6_EINT_WIDTH                        1  /* GP6_EINT */
0389 #define WM831X_GP5_EINT                         0x0010  /* GP5_EINT */
0390 #define WM831X_GP5_EINT_MASK                    0x0010  /* GP5_EINT */
0391 #define WM831X_GP5_EINT_SHIFT                        4  /* GP5_EINT */
0392 #define WM831X_GP5_EINT_WIDTH                        1  /* GP5_EINT */
0393 #define WM831X_GP4_EINT                         0x0008  /* GP4_EINT */
0394 #define WM831X_GP4_EINT_MASK                    0x0008  /* GP4_EINT */
0395 #define WM831X_GP4_EINT_SHIFT                        3  /* GP4_EINT */
0396 #define WM831X_GP4_EINT_WIDTH                        1  /* GP4_EINT */
0397 #define WM831X_GP3_EINT                         0x0004  /* GP3_EINT */
0398 #define WM831X_GP3_EINT_MASK                    0x0004  /* GP3_EINT */
0399 #define WM831X_GP3_EINT_SHIFT                        2  /* GP3_EINT */
0400 #define WM831X_GP3_EINT_WIDTH                        1  /* GP3_EINT */
0401 #define WM831X_GP2_EINT                         0x0002  /* GP2_EINT */
0402 #define WM831X_GP2_EINT_MASK                    0x0002  /* GP2_EINT */
0403 #define WM831X_GP2_EINT_SHIFT                        1  /* GP2_EINT */
0404 #define WM831X_GP2_EINT_WIDTH                        1  /* GP2_EINT */
0405 #define WM831X_GP1_EINT                         0x0001  /* GP1_EINT */
0406 #define WM831X_GP1_EINT_MASK                    0x0001  /* GP1_EINT */
0407 #define WM831X_GP1_EINT_SHIFT                        0  /* GP1_EINT */
0408 #define WM831X_GP1_EINT_WIDTH                        1  /* GP1_EINT */
0409 
0410 /*
0411  * R16407 (0x4017) - IRQ Config
0412  */
0413 #define WM831X_IRQ_OD                           0x0002  /* IRQ_OD */
0414 #define WM831X_IRQ_OD_MASK                      0x0002  /* IRQ_OD */
0415 #define WM831X_IRQ_OD_SHIFT                          1  /* IRQ_OD */
0416 #define WM831X_IRQ_OD_WIDTH                          1  /* IRQ_OD */
0417 #define WM831X_IM_IRQ                           0x0001  /* IM_IRQ */
0418 #define WM831X_IM_IRQ_MASK                      0x0001  /* IM_IRQ */
0419 #define WM831X_IM_IRQ_SHIFT                          0  /* IM_IRQ */
0420 #define WM831X_IM_IRQ_WIDTH                          1  /* IM_IRQ */
0421 
0422 /*
0423  * R16408 (0x4018) - System Interrupts Mask
0424  */
0425 #define WM831X_IM_PS_INT                        0x8000  /* IM_PS_INT */
0426 #define WM831X_IM_PS_INT_MASK                   0x8000  /* IM_PS_INT */
0427 #define WM831X_IM_PS_INT_SHIFT                      15  /* IM_PS_INT */
0428 #define WM831X_IM_PS_INT_WIDTH                       1  /* IM_PS_INT */
0429 #define WM831X_IM_TEMP_INT                      0x4000  /* IM_TEMP_INT */
0430 #define WM831X_IM_TEMP_INT_MASK                 0x4000  /* IM_TEMP_INT */
0431 #define WM831X_IM_TEMP_INT_SHIFT                    14  /* IM_TEMP_INT */
0432 #define WM831X_IM_TEMP_INT_WIDTH                     1  /* IM_TEMP_INT */
0433 #define WM831X_IM_GP_INT                        0x2000  /* IM_GP_INT */
0434 #define WM831X_IM_GP_INT_MASK                   0x2000  /* IM_GP_INT */
0435 #define WM831X_IM_GP_INT_SHIFT                      13  /* IM_GP_INT */
0436 #define WM831X_IM_GP_INT_WIDTH                       1  /* IM_GP_INT */
0437 #define WM831X_IM_ON_PIN_INT                    0x1000  /* IM_ON_PIN_INT */
0438 #define WM831X_IM_ON_PIN_INT_MASK               0x1000  /* IM_ON_PIN_INT */
0439 #define WM831X_IM_ON_PIN_INT_SHIFT                  12  /* IM_ON_PIN_INT */
0440 #define WM831X_IM_ON_PIN_INT_WIDTH                   1  /* IM_ON_PIN_INT */
0441 #define WM831X_IM_WDOG_INT                      0x0800  /* IM_WDOG_INT */
0442 #define WM831X_IM_WDOG_INT_MASK                 0x0800  /* IM_WDOG_INT */
0443 #define WM831X_IM_WDOG_INT_SHIFT                    11  /* IM_WDOG_INT */
0444 #define WM831X_IM_WDOG_INT_WIDTH                     1  /* IM_WDOG_INT */
0445 #define WM831X_IM_TCHDATA_INT                   0x0400  /* IM_TCHDATA_INT */
0446 #define WM831X_IM_TCHDATA_INT_MASK              0x0400  /* IM_TCHDATA_INT */
0447 #define WM831X_IM_TCHDATA_INT_SHIFT                 10  /* IM_TCHDATA_INT */
0448 #define WM831X_IM_TCHDATA_INT_WIDTH                  1  /* IM_TCHDATA_INT */
0449 #define WM831X_IM_TCHPD_INT                     0x0200  /* IM_TCHPD_INT */
0450 #define WM831X_IM_TCHPD_INT_MASK                0x0200  /* IM_TCHPD_INT */
0451 #define WM831X_IM_TCHPD_INT_SHIFT                    9  /* IM_TCHPD_INT */
0452 #define WM831X_IM_TCHPD_INT_WIDTH                    1  /* IM_TCHPD_INT */
0453 #define WM831X_IM_AUXADC_INT                    0x0100  /* IM_AUXADC_INT */
0454 #define WM831X_IM_AUXADC_INT_MASK               0x0100  /* IM_AUXADC_INT */
0455 #define WM831X_IM_AUXADC_INT_SHIFT                   8  /* IM_AUXADC_INT */
0456 #define WM831X_IM_AUXADC_INT_WIDTH                   1  /* IM_AUXADC_INT */
0457 #define WM831X_IM_PPM_INT                       0x0080  /* IM_PPM_INT */
0458 #define WM831X_IM_PPM_INT_MASK                  0x0080  /* IM_PPM_INT */
0459 #define WM831X_IM_PPM_INT_SHIFT                      7  /* IM_PPM_INT */
0460 #define WM831X_IM_PPM_INT_WIDTH                      1  /* IM_PPM_INT */
0461 #define WM831X_IM_CS_INT                        0x0040  /* IM_CS_INT */
0462 #define WM831X_IM_CS_INT_MASK                   0x0040  /* IM_CS_INT */
0463 #define WM831X_IM_CS_INT_SHIFT                       6  /* IM_CS_INT */
0464 #define WM831X_IM_CS_INT_WIDTH                       1  /* IM_CS_INT */
0465 #define WM831X_IM_RTC_INT                       0x0020  /* IM_RTC_INT */
0466 #define WM831X_IM_RTC_INT_MASK                  0x0020  /* IM_RTC_INT */
0467 #define WM831X_IM_RTC_INT_SHIFT                      5  /* IM_RTC_INT */
0468 #define WM831X_IM_RTC_INT_WIDTH                      1  /* IM_RTC_INT */
0469 #define WM831X_IM_OTP_INT                       0x0010  /* IM_OTP_INT */
0470 #define WM831X_IM_OTP_INT_MASK                  0x0010  /* IM_OTP_INT */
0471 #define WM831X_IM_OTP_INT_SHIFT                      4  /* IM_OTP_INT */
0472 #define WM831X_IM_OTP_INT_WIDTH                      1  /* IM_OTP_INT */
0473 #define WM831X_IM_CHILD_INT                     0x0008  /* IM_CHILD_INT */
0474 #define WM831X_IM_CHILD_INT_MASK                0x0008  /* IM_CHILD_INT */
0475 #define WM831X_IM_CHILD_INT_SHIFT                    3  /* IM_CHILD_INT */
0476 #define WM831X_IM_CHILD_INT_WIDTH                    1  /* IM_CHILD_INT */
0477 #define WM831X_IM_CHG_INT                       0x0004  /* IM_CHG_INT */
0478 #define WM831X_IM_CHG_INT_MASK                  0x0004  /* IM_CHG_INT */
0479 #define WM831X_IM_CHG_INT_SHIFT                      2  /* IM_CHG_INT */
0480 #define WM831X_IM_CHG_INT_WIDTH                      1  /* IM_CHG_INT */
0481 #define WM831X_IM_HC_INT                        0x0002  /* IM_HC_INT */
0482 #define WM831X_IM_HC_INT_MASK                   0x0002  /* IM_HC_INT */
0483 #define WM831X_IM_HC_INT_SHIFT                       1  /* IM_HC_INT */
0484 #define WM831X_IM_HC_INT_WIDTH                       1  /* IM_HC_INT */
0485 #define WM831X_IM_UV_INT                        0x0001  /* IM_UV_INT */
0486 #define WM831X_IM_UV_INT_MASK                   0x0001  /* IM_UV_INT */
0487 #define WM831X_IM_UV_INT_SHIFT                       0  /* IM_UV_INT */
0488 #define WM831X_IM_UV_INT_WIDTH                       1  /* IM_UV_INT */
0489 
0490 /*
0491  * R16409 (0x4019) - Interrupt Status 1 Mask
0492  */
0493 #define WM831X_IM_PPM_SYSLO_EINT                0x8000  /* IM_PPM_SYSLO_EINT */
0494 #define WM831X_IM_PPM_SYSLO_EINT_MASK           0x8000  /* IM_PPM_SYSLO_EINT */
0495 #define WM831X_IM_PPM_SYSLO_EINT_SHIFT              15  /* IM_PPM_SYSLO_EINT */
0496 #define WM831X_IM_PPM_SYSLO_EINT_WIDTH               1  /* IM_PPM_SYSLO_EINT */
0497 #define WM831X_IM_PPM_PWR_SRC_EINT              0x4000  /* IM_PPM_PWR_SRC_EINT */
0498 #define WM831X_IM_PPM_PWR_SRC_EINT_MASK         0x4000  /* IM_PPM_PWR_SRC_EINT */
0499 #define WM831X_IM_PPM_PWR_SRC_EINT_SHIFT            14  /* IM_PPM_PWR_SRC_EINT */
0500 #define WM831X_IM_PPM_PWR_SRC_EINT_WIDTH             1  /* IM_PPM_PWR_SRC_EINT */
0501 #define WM831X_IM_PPM_USB_CURR_EINT             0x2000  /* IM_PPM_USB_CURR_EINT */
0502 #define WM831X_IM_PPM_USB_CURR_EINT_MASK        0x2000  /* IM_PPM_USB_CURR_EINT */
0503 #define WM831X_IM_PPM_USB_CURR_EINT_SHIFT           13  /* IM_PPM_USB_CURR_EINT */
0504 #define WM831X_IM_PPM_USB_CURR_EINT_WIDTH            1  /* IM_PPM_USB_CURR_EINT */
0505 #define WM831X_IM_ON_PIN_EINT                   0x1000  /* IM_ON_PIN_EINT */
0506 #define WM831X_IM_ON_PIN_EINT_MASK              0x1000  /* IM_ON_PIN_EINT */
0507 #define WM831X_IM_ON_PIN_EINT_SHIFT                 12  /* IM_ON_PIN_EINT */
0508 #define WM831X_IM_ON_PIN_EINT_WIDTH                  1  /* IM_ON_PIN_EINT */
0509 #define WM831X_IM_WDOG_TO_EINT                  0x0800  /* IM_WDOG_TO_EINT */
0510 #define WM831X_IM_WDOG_TO_EINT_MASK             0x0800  /* IM_WDOG_TO_EINT */
0511 #define WM831X_IM_WDOG_TO_EINT_SHIFT                11  /* IM_WDOG_TO_EINT */
0512 #define WM831X_IM_WDOG_TO_EINT_WIDTH                 1  /* IM_WDOG_TO_EINT */
0513 #define WM831X_IM_TCHDATA_EINT                  0x0400  /* IM_TCHDATA_EINT */
0514 #define WM831X_IM_TCHDATA_EINT_MASK             0x0400  /* IM_TCHDATA_EINT */
0515 #define WM831X_IM_TCHDATA_EINT_SHIFT                10  /* IM_TCHDATA_EINT */
0516 #define WM831X_IM_TCHDATA_EINT_WIDTH                 1  /* IM_TCHDATA_EINT */
0517 #define WM831X_IM_TCHPD_EINT                    0x0200  /* IM_TCHPD_EINT */
0518 #define WM831X_IM_TCHPD_EINT_MASK               0x0200  /* IM_TCHPD_EINT */
0519 #define WM831X_IM_TCHPD_EINT_SHIFT                   9  /* IM_TCHPD_EINT */
0520 #define WM831X_IM_TCHPD_EINT_WIDTH                   1  /* IM_TCHPD_EINT */
0521 #define WM831X_IM_AUXADC_DATA_EINT              0x0100  /* IM_AUXADC_DATA_EINT */
0522 #define WM831X_IM_AUXADC_DATA_EINT_MASK         0x0100  /* IM_AUXADC_DATA_EINT */
0523 #define WM831X_IM_AUXADC_DATA_EINT_SHIFT             8  /* IM_AUXADC_DATA_EINT */
0524 #define WM831X_IM_AUXADC_DATA_EINT_WIDTH             1  /* IM_AUXADC_DATA_EINT */
0525 #define WM831X_IM_AUXADC_DCOMP4_EINT            0x0080  /* IM_AUXADC_DCOMP4_EINT */
0526 #define WM831X_IM_AUXADC_DCOMP4_EINT_MASK       0x0080  /* IM_AUXADC_DCOMP4_EINT */
0527 #define WM831X_IM_AUXADC_DCOMP4_EINT_SHIFT           7  /* IM_AUXADC_DCOMP4_EINT */
0528 #define WM831X_IM_AUXADC_DCOMP4_EINT_WIDTH           1  /* IM_AUXADC_DCOMP4_EINT */
0529 #define WM831X_IM_AUXADC_DCOMP3_EINT            0x0040  /* IM_AUXADC_DCOMP3_EINT */
0530 #define WM831X_IM_AUXADC_DCOMP3_EINT_MASK       0x0040  /* IM_AUXADC_DCOMP3_EINT */
0531 #define WM831X_IM_AUXADC_DCOMP3_EINT_SHIFT           6  /* IM_AUXADC_DCOMP3_EINT */
0532 #define WM831X_IM_AUXADC_DCOMP3_EINT_WIDTH           1  /* IM_AUXADC_DCOMP3_EINT */
0533 #define WM831X_IM_AUXADC_DCOMP2_EINT            0x0020  /* IM_AUXADC_DCOMP2_EINT */
0534 #define WM831X_IM_AUXADC_DCOMP2_EINT_MASK       0x0020  /* IM_AUXADC_DCOMP2_EINT */
0535 #define WM831X_IM_AUXADC_DCOMP2_EINT_SHIFT           5  /* IM_AUXADC_DCOMP2_EINT */
0536 #define WM831X_IM_AUXADC_DCOMP2_EINT_WIDTH           1  /* IM_AUXADC_DCOMP2_EINT */
0537 #define WM831X_IM_AUXADC_DCOMP1_EINT            0x0010  /* IM_AUXADC_DCOMP1_EINT */
0538 #define WM831X_IM_AUXADC_DCOMP1_EINT_MASK       0x0010  /* IM_AUXADC_DCOMP1_EINT */
0539 #define WM831X_IM_AUXADC_DCOMP1_EINT_SHIFT           4  /* IM_AUXADC_DCOMP1_EINT */
0540 #define WM831X_IM_AUXADC_DCOMP1_EINT_WIDTH           1  /* IM_AUXADC_DCOMP1_EINT */
0541 #define WM831X_IM_RTC_PER_EINT                  0x0008  /* IM_RTC_PER_EINT */
0542 #define WM831X_IM_RTC_PER_EINT_MASK             0x0008  /* IM_RTC_PER_EINT */
0543 #define WM831X_IM_RTC_PER_EINT_SHIFT                 3  /* IM_RTC_PER_EINT */
0544 #define WM831X_IM_RTC_PER_EINT_WIDTH                 1  /* IM_RTC_PER_EINT */
0545 #define WM831X_IM_RTC_ALM_EINT                  0x0004  /* IM_RTC_ALM_EINT */
0546 #define WM831X_IM_RTC_ALM_EINT_MASK             0x0004  /* IM_RTC_ALM_EINT */
0547 #define WM831X_IM_RTC_ALM_EINT_SHIFT                 2  /* IM_RTC_ALM_EINT */
0548 #define WM831X_IM_RTC_ALM_EINT_WIDTH                 1  /* IM_RTC_ALM_EINT */
0549 #define WM831X_IM_TEMP_THW_EINT                 0x0002  /* IM_TEMP_THW_EINT */
0550 #define WM831X_IM_TEMP_THW_EINT_MASK            0x0002  /* IM_TEMP_THW_EINT */
0551 #define WM831X_IM_TEMP_THW_EINT_SHIFT                1  /* IM_TEMP_THW_EINT */
0552 #define WM831X_IM_TEMP_THW_EINT_WIDTH                1  /* IM_TEMP_THW_EINT */
0553 
0554 /*
0555  * R16410 (0x401A) - Interrupt Status 2 Mask
0556  */
0557 #define WM831X_IM_CHG_BATT_HOT_EINT             0x8000  /* IM_CHG_BATT_HOT_EINT */
0558 #define WM831X_IM_CHG_BATT_HOT_EINT_MASK        0x8000  /* IM_CHG_BATT_HOT_EINT */
0559 #define WM831X_IM_CHG_BATT_HOT_EINT_SHIFT           15  /* IM_CHG_BATT_HOT_EINT */
0560 #define WM831X_IM_CHG_BATT_HOT_EINT_WIDTH            1  /* IM_CHG_BATT_HOT_EINT */
0561 #define WM831X_IM_CHG_BATT_COLD_EINT            0x4000  /* IM_CHG_BATT_COLD_EINT */
0562 #define WM831X_IM_CHG_BATT_COLD_EINT_MASK       0x4000  /* IM_CHG_BATT_COLD_EINT */
0563 #define WM831X_IM_CHG_BATT_COLD_EINT_SHIFT          14  /* IM_CHG_BATT_COLD_EINT */
0564 #define WM831X_IM_CHG_BATT_COLD_EINT_WIDTH           1  /* IM_CHG_BATT_COLD_EINT */
0565 #define WM831X_IM_CHG_BATT_FAIL_EINT            0x2000  /* IM_CHG_BATT_FAIL_EINT */
0566 #define WM831X_IM_CHG_BATT_FAIL_EINT_MASK       0x2000  /* IM_CHG_BATT_FAIL_EINT */
0567 #define WM831X_IM_CHG_BATT_FAIL_EINT_SHIFT          13  /* IM_CHG_BATT_FAIL_EINT */
0568 #define WM831X_IM_CHG_BATT_FAIL_EINT_WIDTH           1  /* IM_CHG_BATT_FAIL_EINT */
0569 #define WM831X_IM_CHG_OV_EINT                   0x1000  /* IM_CHG_OV_EINT */
0570 #define WM831X_IM_CHG_OV_EINT_MASK              0x1000  /* IM_CHG_OV_EINT */
0571 #define WM831X_IM_CHG_OV_EINT_SHIFT                 12  /* IM_CHG_OV_EINT */
0572 #define WM831X_IM_CHG_OV_EINT_WIDTH                  1  /* IM_CHG_OV_EINT */
0573 #define WM831X_IM_CHG_END_EINT                  0x0800  /* IM_CHG_END_EINT */
0574 #define WM831X_IM_CHG_END_EINT_MASK             0x0800  /* IM_CHG_END_EINT */
0575 #define WM831X_IM_CHG_END_EINT_SHIFT                11  /* IM_CHG_END_EINT */
0576 #define WM831X_IM_CHG_END_EINT_WIDTH                 1  /* IM_CHG_END_EINT */
0577 #define WM831X_IM_CHG_TO_EINT                   0x0400  /* IM_CHG_TO_EINT */
0578 #define WM831X_IM_CHG_TO_EINT_MASK              0x0400  /* IM_CHG_TO_EINT */
0579 #define WM831X_IM_CHG_TO_EINT_SHIFT                 10  /* IM_CHG_TO_EINT */
0580 #define WM831X_IM_CHG_TO_EINT_WIDTH                  1  /* IM_CHG_TO_EINT */
0581 #define WM831X_IM_CHG_MODE_EINT                 0x0200  /* IM_CHG_MODE_EINT */
0582 #define WM831X_IM_CHG_MODE_EINT_MASK            0x0200  /* IM_CHG_MODE_EINT */
0583 #define WM831X_IM_CHG_MODE_EINT_SHIFT                9  /* IM_CHG_MODE_EINT */
0584 #define WM831X_IM_CHG_MODE_EINT_WIDTH                1  /* IM_CHG_MODE_EINT */
0585 #define WM831X_IM_CHG_START_EINT                0x0100  /* IM_CHG_START_EINT */
0586 #define WM831X_IM_CHG_START_EINT_MASK           0x0100  /* IM_CHG_START_EINT */
0587 #define WM831X_IM_CHG_START_EINT_SHIFT               8  /* IM_CHG_START_EINT */
0588 #define WM831X_IM_CHG_START_EINT_WIDTH               1  /* IM_CHG_START_EINT */
0589 #define WM831X_IM_CS2_EINT                      0x0080  /* IM_CS2_EINT */
0590 #define WM831X_IM_CS2_EINT_MASK                 0x0080  /* IM_CS2_EINT */
0591 #define WM831X_IM_CS2_EINT_SHIFT                     7  /* IM_CS2_EINT */
0592 #define WM831X_IM_CS2_EINT_WIDTH                     1  /* IM_CS2_EINT */
0593 #define WM831X_IM_CS1_EINT                      0x0040  /* IM_CS1_EINT */
0594 #define WM831X_IM_CS1_EINT_MASK                 0x0040  /* IM_CS1_EINT */
0595 #define WM831X_IM_CS1_EINT_SHIFT                     6  /* IM_CS1_EINT */
0596 #define WM831X_IM_CS1_EINT_WIDTH                     1  /* IM_CS1_EINT */
0597 #define WM831X_IM_OTP_CMD_END_EINT              0x0020  /* IM_OTP_CMD_END_EINT */
0598 #define WM831X_IM_OTP_CMD_END_EINT_MASK         0x0020  /* IM_OTP_CMD_END_EINT */
0599 #define WM831X_IM_OTP_CMD_END_EINT_SHIFT             5  /* IM_OTP_CMD_END_EINT */
0600 #define WM831X_IM_OTP_CMD_END_EINT_WIDTH             1  /* IM_OTP_CMD_END_EINT */
0601 #define WM831X_IM_OTP_ERR_EINT                  0x0010  /* IM_OTP_ERR_EINT */
0602 #define WM831X_IM_OTP_ERR_EINT_MASK             0x0010  /* IM_OTP_ERR_EINT */
0603 #define WM831X_IM_OTP_ERR_EINT_SHIFT                 4  /* IM_OTP_ERR_EINT */
0604 #define WM831X_IM_OTP_ERR_EINT_WIDTH                 1  /* IM_OTP_ERR_EINT */
0605 #define WM831X_IM_PS_POR_EINT                   0x0004  /* IM_PS_POR_EINT */
0606 #define WM831X_IM_PS_POR_EINT_MASK              0x0004  /* IM_PS_POR_EINT */
0607 #define WM831X_IM_PS_POR_EINT_SHIFT                  2  /* IM_PS_POR_EINT */
0608 #define WM831X_IM_PS_POR_EINT_WIDTH                  1  /* IM_PS_POR_EINT */
0609 #define WM831X_IM_PS_SLEEP_OFF_EINT             0x0002  /* IM_PS_SLEEP_OFF_EINT */
0610 #define WM831X_IM_PS_SLEEP_OFF_EINT_MASK        0x0002  /* IM_PS_SLEEP_OFF_EINT */
0611 #define WM831X_IM_PS_SLEEP_OFF_EINT_SHIFT            1  /* IM_PS_SLEEP_OFF_EINT */
0612 #define WM831X_IM_PS_SLEEP_OFF_EINT_WIDTH            1  /* IM_PS_SLEEP_OFF_EINT */
0613 #define WM831X_IM_PS_ON_WAKE_EINT               0x0001  /* IM_PS_ON_WAKE_EINT */
0614 #define WM831X_IM_PS_ON_WAKE_EINT_MASK          0x0001  /* IM_PS_ON_WAKE_EINT */
0615 #define WM831X_IM_PS_ON_WAKE_EINT_SHIFT              0  /* IM_PS_ON_WAKE_EINT */
0616 #define WM831X_IM_PS_ON_WAKE_EINT_WIDTH              1  /* IM_PS_ON_WAKE_EINT */
0617 
0618 /*
0619  * R16411 (0x401B) - Interrupt Status 3 Mask
0620  */
0621 #define WM831X_IM_UV_LDO10_EINT                 0x0200  /* IM_UV_LDO10_EINT */
0622 #define WM831X_IM_UV_LDO10_EINT_MASK            0x0200  /* IM_UV_LDO10_EINT */
0623 #define WM831X_IM_UV_LDO10_EINT_SHIFT                9  /* IM_UV_LDO10_EINT */
0624 #define WM831X_IM_UV_LDO10_EINT_WIDTH                1  /* IM_UV_LDO10_EINT */
0625 #define WM831X_IM_UV_LDO9_EINT                  0x0100  /* IM_UV_LDO9_EINT */
0626 #define WM831X_IM_UV_LDO9_EINT_MASK             0x0100  /* IM_UV_LDO9_EINT */
0627 #define WM831X_IM_UV_LDO9_EINT_SHIFT                 8  /* IM_UV_LDO9_EINT */
0628 #define WM831X_IM_UV_LDO9_EINT_WIDTH                 1  /* IM_UV_LDO9_EINT */
0629 #define WM831X_IM_UV_LDO8_EINT                  0x0080  /* IM_UV_LDO8_EINT */
0630 #define WM831X_IM_UV_LDO8_EINT_MASK             0x0080  /* IM_UV_LDO8_EINT */
0631 #define WM831X_IM_UV_LDO8_EINT_SHIFT                 7  /* IM_UV_LDO8_EINT */
0632 #define WM831X_IM_UV_LDO8_EINT_WIDTH                 1  /* IM_UV_LDO8_EINT */
0633 #define WM831X_IM_UV_LDO7_EINT                  0x0040  /* IM_UV_LDO7_EINT */
0634 #define WM831X_IM_UV_LDO7_EINT_MASK             0x0040  /* IM_UV_LDO7_EINT */
0635 #define WM831X_IM_UV_LDO7_EINT_SHIFT                 6  /* IM_UV_LDO7_EINT */
0636 #define WM831X_IM_UV_LDO7_EINT_WIDTH                 1  /* IM_UV_LDO7_EINT */
0637 #define WM831X_IM_UV_LDO6_EINT                  0x0020  /* IM_UV_LDO6_EINT */
0638 #define WM831X_IM_UV_LDO6_EINT_MASK             0x0020  /* IM_UV_LDO6_EINT */
0639 #define WM831X_IM_UV_LDO6_EINT_SHIFT                 5  /* IM_UV_LDO6_EINT */
0640 #define WM831X_IM_UV_LDO6_EINT_WIDTH                 1  /* IM_UV_LDO6_EINT */
0641 #define WM831X_IM_UV_LDO5_EINT                  0x0010  /* IM_UV_LDO5_EINT */
0642 #define WM831X_IM_UV_LDO5_EINT_MASK             0x0010  /* IM_UV_LDO5_EINT */
0643 #define WM831X_IM_UV_LDO5_EINT_SHIFT                 4  /* IM_UV_LDO5_EINT */
0644 #define WM831X_IM_UV_LDO5_EINT_WIDTH                 1  /* IM_UV_LDO5_EINT */
0645 #define WM831X_IM_UV_LDO4_EINT                  0x0008  /* IM_UV_LDO4_EINT */
0646 #define WM831X_IM_UV_LDO4_EINT_MASK             0x0008  /* IM_UV_LDO4_EINT */
0647 #define WM831X_IM_UV_LDO4_EINT_SHIFT                 3  /* IM_UV_LDO4_EINT */
0648 #define WM831X_IM_UV_LDO4_EINT_WIDTH                 1  /* IM_UV_LDO4_EINT */
0649 #define WM831X_IM_UV_LDO3_EINT                  0x0004  /* IM_UV_LDO3_EINT */
0650 #define WM831X_IM_UV_LDO3_EINT_MASK             0x0004  /* IM_UV_LDO3_EINT */
0651 #define WM831X_IM_UV_LDO3_EINT_SHIFT                 2  /* IM_UV_LDO3_EINT */
0652 #define WM831X_IM_UV_LDO3_EINT_WIDTH                 1  /* IM_UV_LDO3_EINT */
0653 #define WM831X_IM_UV_LDO2_EINT                  0x0002  /* IM_UV_LDO2_EINT */
0654 #define WM831X_IM_UV_LDO2_EINT_MASK             0x0002  /* IM_UV_LDO2_EINT */
0655 #define WM831X_IM_UV_LDO2_EINT_SHIFT                 1  /* IM_UV_LDO2_EINT */
0656 #define WM831X_IM_UV_LDO2_EINT_WIDTH                 1  /* IM_UV_LDO2_EINT */
0657 #define WM831X_IM_UV_LDO1_EINT                  0x0001  /* IM_UV_LDO1_EINT */
0658 #define WM831X_IM_UV_LDO1_EINT_MASK             0x0001  /* IM_UV_LDO1_EINT */
0659 #define WM831X_IM_UV_LDO1_EINT_SHIFT                 0  /* IM_UV_LDO1_EINT */
0660 #define WM831X_IM_UV_LDO1_EINT_WIDTH                 1  /* IM_UV_LDO1_EINT */
0661 
0662 /*
0663  * R16412 (0x401C) - Interrupt Status 4 Mask
0664  */
0665 #define WM831X_IM_HC_DC2_EINT                   0x0200  /* IM_HC_DC2_EINT */
0666 #define WM831X_IM_HC_DC2_EINT_MASK              0x0200  /* IM_HC_DC2_EINT */
0667 #define WM831X_IM_HC_DC2_EINT_SHIFT                  9  /* IM_HC_DC2_EINT */
0668 #define WM831X_IM_HC_DC2_EINT_WIDTH                  1  /* IM_HC_DC2_EINT */
0669 #define WM831X_IM_HC_DC1_EINT                   0x0100  /* IM_HC_DC1_EINT */
0670 #define WM831X_IM_HC_DC1_EINT_MASK              0x0100  /* IM_HC_DC1_EINT */
0671 #define WM831X_IM_HC_DC1_EINT_SHIFT                  8  /* IM_HC_DC1_EINT */
0672 #define WM831X_IM_HC_DC1_EINT_WIDTH                  1  /* IM_HC_DC1_EINT */
0673 #define WM831X_IM_UV_DC4_EINT                   0x0008  /* IM_UV_DC4_EINT */
0674 #define WM831X_IM_UV_DC4_EINT_MASK              0x0008  /* IM_UV_DC4_EINT */
0675 #define WM831X_IM_UV_DC4_EINT_SHIFT                  3  /* IM_UV_DC4_EINT */
0676 #define WM831X_IM_UV_DC4_EINT_WIDTH                  1  /* IM_UV_DC4_EINT */
0677 #define WM831X_IM_UV_DC3_EINT                   0x0004  /* IM_UV_DC3_EINT */
0678 #define WM831X_IM_UV_DC3_EINT_MASK              0x0004  /* IM_UV_DC3_EINT */
0679 #define WM831X_IM_UV_DC3_EINT_SHIFT                  2  /* IM_UV_DC3_EINT */
0680 #define WM831X_IM_UV_DC3_EINT_WIDTH                  1  /* IM_UV_DC3_EINT */
0681 #define WM831X_IM_UV_DC2_EINT                   0x0002  /* IM_UV_DC2_EINT */
0682 #define WM831X_IM_UV_DC2_EINT_MASK              0x0002  /* IM_UV_DC2_EINT */
0683 #define WM831X_IM_UV_DC2_EINT_SHIFT                  1  /* IM_UV_DC2_EINT */
0684 #define WM831X_IM_UV_DC2_EINT_WIDTH                  1  /* IM_UV_DC2_EINT */
0685 #define WM831X_IM_UV_DC1_EINT                   0x0001  /* IM_UV_DC1_EINT */
0686 #define WM831X_IM_UV_DC1_EINT_MASK              0x0001  /* IM_UV_DC1_EINT */
0687 #define WM831X_IM_UV_DC1_EINT_SHIFT                  0  /* IM_UV_DC1_EINT */
0688 #define WM831X_IM_UV_DC1_EINT_WIDTH                  1  /* IM_UV_DC1_EINT */
0689 
0690 /*
0691  * R16413 (0x401D) - Interrupt Status 5 Mask
0692  */
0693 #define WM831X_IM_GP16_EINT                     0x8000  /* IM_GP16_EINT */
0694 #define WM831X_IM_GP16_EINT_MASK                0x8000  /* IM_GP16_EINT */
0695 #define WM831X_IM_GP16_EINT_SHIFT                   15  /* IM_GP16_EINT */
0696 #define WM831X_IM_GP16_EINT_WIDTH                    1  /* IM_GP16_EINT */
0697 #define WM831X_IM_GP15_EINT                     0x4000  /* IM_GP15_EINT */
0698 #define WM831X_IM_GP15_EINT_MASK                0x4000  /* IM_GP15_EINT */
0699 #define WM831X_IM_GP15_EINT_SHIFT                   14  /* IM_GP15_EINT */
0700 #define WM831X_IM_GP15_EINT_WIDTH                    1  /* IM_GP15_EINT */
0701 #define WM831X_IM_GP14_EINT                     0x2000  /* IM_GP14_EINT */
0702 #define WM831X_IM_GP14_EINT_MASK                0x2000  /* IM_GP14_EINT */
0703 #define WM831X_IM_GP14_EINT_SHIFT                   13  /* IM_GP14_EINT */
0704 #define WM831X_IM_GP14_EINT_WIDTH                    1  /* IM_GP14_EINT */
0705 #define WM831X_IM_GP13_EINT                     0x1000  /* IM_GP13_EINT */
0706 #define WM831X_IM_GP13_EINT_MASK                0x1000  /* IM_GP13_EINT */
0707 #define WM831X_IM_GP13_EINT_SHIFT                   12  /* IM_GP13_EINT */
0708 #define WM831X_IM_GP13_EINT_WIDTH                    1  /* IM_GP13_EINT */
0709 #define WM831X_IM_GP12_EINT                     0x0800  /* IM_GP12_EINT */
0710 #define WM831X_IM_GP12_EINT_MASK                0x0800  /* IM_GP12_EINT */
0711 #define WM831X_IM_GP12_EINT_SHIFT                   11  /* IM_GP12_EINT */
0712 #define WM831X_IM_GP12_EINT_WIDTH                    1  /* IM_GP12_EINT */
0713 #define WM831X_IM_GP11_EINT                     0x0400  /* IM_GP11_EINT */
0714 #define WM831X_IM_GP11_EINT_MASK                0x0400  /* IM_GP11_EINT */
0715 #define WM831X_IM_GP11_EINT_SHIFT                   10  /* IM_GP11_EINT */
0716 #define WM831X_IM_GP11_EINT_WIDTH                    1  /* IM_GP11_EINT */
0717 #define WM831X_IM_GP10_EINT                     0x0200  /* IM_GP10_EINT */
0718 #define WM831X_IM_GP10_EINT_MASK                0x0200  /* IM_GP10_EINT */
0719 #define WM831X_IM_GP10_EINT_SHIFT                    9  /* IM_GP10_EINT */
0720 #define WM831X_IM_GP10_EINT_WIDTH                    1  /* IM_GP10_EINT */
0721 #define WM831X_IM_GP9_EINT                      0x0100  /* IM_GP9_EINT */
0722 #define WM831X_IM_GP9_EINT_MASK                 0x0100  /* IM_GP9_EINT */
0723 #define WM831X_IM_GP9_EINT_SHIFT                     8  /* IM_GP9_EINT */
0724 #define WM831X_IM_GP9_EINT_WIDTH                     1  /* IM_GP9_EINT */
0725 #define WM831X_IM_GP8_EINT                      0x0080  /* IM_GP8_EINT */
0726 #define WM831X_IM_GP8_EINT_MASK                 0x0080  /* IM_GP8_EINT */
0727 #define WM831X_IM_GP8_EINT_SHIFT                     7  /* IM_GP8_EINT */
0728 #define WM831X_IM_GP8_EINT_WIDTH                     1  /* IM_GP8_EINT */
0729 #define WM831X_IM_GP7_EINT                      0x0040  /* IM_GP7_EINT */
0730 #define WM831X_IM_GP7_EINT_MASK                 0x0040  /* IM_GP7_EINT */
0731 #define WM831X_IM_GP7_EINT_SHIFT                     6  /* IM_GP7_EINT */
0732 #define WM831X_IM_GP7_EINT_WIDTH                     1  /* IM_GP7_EINT */
0733 #define WM831X_IM_GP6_EINT                      0x0020  /* IM_GP6_EINT */
0734 #define WM831X_IM_GP6_EINT_MASK                 0x0020  /* IM_GP6_EINT */
0735 #define WM831X_IM_GP6_EINT_SHIFT                     5  /* IM_GP6_EINT */
0736 #define WM831X_IM_GP6_EINT_WIDTH                     1  /* IM_GP6_EINT */
0737 #define WM831X_IM_GP5_EINT                      0x0010  /* IM_GP5_EINT */
0738 #define WM831X_IM_GP5_EINT_MASK                 0x0010  /* IM_GP5_EINT */
0739 #define WM831X_IM_GP5_EINT_SHIFT                     4  /* IM_GP5_EINT */
0740 #define WM831X_IM_GP5_EINT_WIDTH                     1  /* IM_GP5_EINT */
0741 #define WM831X_IM_GP4_EINT                      0x0008  /* IM_GP4_EINT */
0742 #define WM831X_IM_GP4_EINT_MASK                 0x0008  /* IM_GP4_EINT */
0743 #define WM831X_IM_GP4_EINT_SHIFT                     3  /* IM_GP4_EINT */
0744 #define WM831X_IM_GP4_EINT_WIDTH                     1  /* IM_GP4_EINT */
0745 #define WM831X_IM_GP3_EINT                      0x0004  /* IM_GP3_EINT */
0746 #define WM831X_IM_GP3_EINT_MASK                 0x0004  /* IM_GP3_EINT */
0747 #define WM831X_IM_GP3_EINT_SHIFT                     2  /* IM_GP3_EINT */
0748 #define WM831X_IM_GP3_EINT_WIDTH                     1  /* IM_GP3_EINT */
0749 #define WM831X_IM_GP2_EINT                      0x0002  /* IM_GP2_EINT */
0750 #define WM831X_IM_GP2_EINT_MASK                 0x0002  /* IM_GP2_EINT */
0751 #define WM831X_IM_GP2_EINT_SHIFT                     1  /* IM_GP2_EINT */
0752 #define WM831X_IM_GP2_EINT_WIDTH                     1  /* IM_GP2_EINT */
0753 #define WM831X_IM_GP1_EINT                      0x0001  /* IM_GP1_EINT */
0754 #define WM831X_IM_GP1_EINT_MASK                 0x0001  /* IM_GP1_EINT */
0755 #define WM831X_IM_GP1_EINT_SHIFT                     0  /* IM_GP1_EINT */
0756 #define WM831X_IM_GP1_EINT_WIDTH                     1  /* IM_GP1_EINT */
0757 
0758 
0759 #endif