linux/mfd/ucb1x00.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  *  linux/include/mfd/ucb1x00.h
0004  *
0005  *  Copyright (C) 2001 Russell King, All Rights Reserved.
0006  */
0007 #ifndef UCB1200_H
0008 #define UCB1200_H
0009
0010 #include <linux/device.h>
0011 #include <linux/mfd/mcp.h>
0012 #include <linux/gpio.h>
0013 #include <linux/mutex.h>
0014
0015 #define UCB_IO_DATA 0x00
0016 #define UCB_IO_DIR  0x01
0017
0018 #define UCB_IO_0        (1 << 0)
0019 #define UCB_IO_1        (1 << 1)
0020 #define UCB_IO_2        (1 << 2)
0021 #define UCB_IO_3        (1 << 3)
0022 #define UCB_IO_4        (1 << 4)
0023 #define UCB_IO_5        (1 << 5)
0024 #define UCB_IO_6        (1 << 6)
0025 #define UCB_IO_7        (1 << 7)
0026 #define UCB_IO_8        (1 << 8)
0027 #define UCB_IO_9        (1 << 9)
0028
0029 #define UCB_IE_RIS  0x02
0030 #define UCB_IE_FAL  0x03
0031 #define UCB_IE_STATUS   0x04
0032 #define UCB_IE_CLEAR    0x04
0033 #define UCB_IE_ADC      (1 << 11)
0034 #define UCB_IE_TSPX     (1 << 12)
0035 #define UCB_IE_TSMX     (1 << 13)
0036 #define UCB_IE_TCLIP        (1 << 14)
0037 #define UCB_IE_ACLIP        (1 << 15)
0038
0039 #define UCB_IRQ_TSPX        12
0040
0041 #define UCB_TC_A    0x05
0042 #define UCB_TC_A_LOOP       (1 << 7)    /* UCB1200 */
0043 #define UCB_TC_A_AMPL       (1 << 7)    /* UCB1300 */
0044
0045 #define UCB_TC_B    0x06
0046 #define UCB_TC_B_VOICE_ENA  (1 << 3)
0047 #define UCB_TC_B_CLIP       (1 << 4)
0048 #define UCB_TC_B_ATT        (1 << 6)
0049 #define UCB_TC_B_SIDE_ENA   (1 << 11)
0050 #define UCB_TC_B_MUTE       (1 << 13)
0051 #define UCB_TC_B_IN_ENA     (1 << 14)
0052 #define UCB_TC_B_OUT_ENA    (1 << 15)
0053
0054 #define UCB_AC_A    0x07
0055 #define UCB_AC_B    0x08
0056 #define UCB_AC_B_LOOP       (1 << 8)
0057 #define UCB_AC_B_MUTE       (1 << 13)
0058 #define UCB_AC_B_IN_ENA     (1 << 14)
0059 #define UCB_AC_B_OUT_ENA    (1 << 15)
0060
0061 #define UCB_TS_CR   0x09
0062 #define UCB_TS_CR_TSMX_POW  (1 << 0)
0063 #define UCB_TS_CR_TSPX_POW  (1 << 1)
0064 #define UCB_TS_CR_TSMY_POW  (1 << 2)
0065 #define UCB_TS_CR_TSPY_POW  (1 << 3)
0066 #define UCB_TS_CR_TSMX_GND  (1 << 4)
0067 #define UCB_TS_CR_TSPX_GND  (1 << 5)
0068 #define UCB_TS_CR_TSMY_GND  (1 << 6)
0069 #define UCB_TS_CR_TSPY_GND  (1 << 7)
0070 #define UCB_TS_CR_MODE_INT  (0 << 8)
0071 #define UCB_TS_CR_MODE_PRES (1 << 8)
0072 #define UCB_TS_CR_MODE_POS  (2 << 8)
0073 #define UCB_TS_CR_BIAS_ENA  (1 << 11)
0074 #define UCB_TS_CR_TSPX_LOW  (1 << 12)
0075 #define UCB_TS_CR_TSMX_LOW  (1 << 13)
0076
0077 #define UCB_ADC_CR  0x0a
0078 #define UCB_ADC_SYNC_ENA    (1 << 0)
0079 #define UCB_ADC_VREFBYP_CON (1 << 1)
0080 #define UCB_ADC_INP_TSPX    (0 << 2)
0081 #define UCB_ADC_INP_TSMX    (1 << 2)
0082 #define UCB_ADC_INP_TSPY    (2 << 2)
0083 #define UCB_ADC_INP_TSMY    (3 << 2)
0084 #define UCB_ADC_INP_AD0     (4 << 2)
0085 #define UCB_ADC_INP_AD1     (5 << 2)
0086 #define UCB_ADC_INP_AD2     (6 << 2)
0087 #define UCB_ADC_INP_AD3     (7 << 2)
0088 #define UCB_ADC_EXT_REF     (1 << 5)
0089 #define UCB_ADC_START       (1 << 7)
0090 #define UCB_ADC_ENA     (1 << 15)
0091
0092 #define UCB_ADC_DATA    0x0b
0093 #define UCB_ADC_DAT_VAL     (1 << 15)
0094 #define UCB_ADC_DAT(x)      (((x) & 0x7fe0) >> 5)
0095
0096 #define UCB_ID      0x0c
0097 #define UCB_ID_1200     0x1004
0098 #define UCB_ID_1300     0x1005
0099 #define UCB_ID_TC35143          0x9712
0100
0101 #define UCB_MODE    0x0d
0102 #define UCB_MODE_DYN_VFLAG_ENA  (1 << 12)
0103 #define UCB_MODE_AUD_OFF_CAN    (1 << 13)
0104
0105 enum ucb1x00_reset {
0106     UCB_RST_PROBE,
0107     UCB_RST_RESUME,
0108     UCB_RST_SUSPEND,
0109     UCB_RST_REMOVE,
0110     UCB_RST_PROBE_FAIL,
0111 };
0112
0113 struct ucb1x00_plat_data {
0114     void            (*reset)(enum ucb1x00_reset);
0115     unsigned        irq_base;
0116     int         gpio_base;
0117     unsigned        can_wakeup;
0118 };
0119
0120 struct ucb1x00 {
0121     raw_spinlock_t      irq_lock;
0122     struct mcp      *mcp;
0123     unsigned int        irq;
0124     int         irq_base;
0125     struct mutex        adc_mutex;
0126     spinlock_t      io_lock;
0127     u16         id;
0128     u16         io_dir;
0129     u16         io_out;
0130     u16         adc_cr;
0131     u16         irq_fal_enbl;
0132     u16         irq_ris_enbl;
0133     u16         irq_mask;
0134     u16         irq_wake;
0135     struct device       dev;
0136     struct list_head    node;
0137     struct list_head    devs;
0138     struct gpio_chip    gpio;
0139 };
0140
0141 struct ucb1x00_driver;
0142
0143 struct ucb1x00_dev {
0144     struct list_head    dev_node;
0145     struct list_head    drv_node;
0146     struct ucb1x00      *ucb;
0147     struct ucb1x00_driver   *drv;
0148     void            *priv;
0149 };
0150
0151 struct ucb1x00_driver {
0152     struct list_head    node;
0153     struct list_head    devs;
0154     int (*add)(struct ucb1x00_dev *dev);
0155     void    (*remove)(struct ucb1x00_dev *dev);
0156     int (*suspend)(struct ucb1x00_dev *dev);
0157     int (*resume)(struct ucb1x00_dev *dev);
0158 };
0159
0160 #define classdev_to_ucb1x00(cd) container_of(cd, struct ucb1x00, dev)
0161
0162 int ucb1x00_register_driver(struct ucb1x00_driver *);
0163 void ucb1x00_unregister_driver(struct ucb1x00_driver *);
0164
0165 /**
0166  *  ucb1x00_clkrate - return the UCB1x00 SIB clock rate
0167  *  @ucb: UCB1x00 structure describing chip
0168  *
0169  *  Return the SIB clock rate in Hz.
0170  */
0171 static inline unsigned int ucb1x00_clkrate(struct ucb1x00 *ucb)
0172 {
0173     return mcp_get_sclk_rate(ucb->mcp);
0174 }
0175
0176 /**
0177  *  ucb1x00_enable - enable the UCB1x00 SIB clock
0178  *  @ucb: UCB1x00 structure describing chip
0179  *
0180  *  Enable the SIB clock.  This can be called multiple times.
0181  */
0182 static inline void ucb1x00_enable(struct ucb1x00 *ucb)
0183 {
0184     mcp_enable(ucb->mcp);
0185 }
0186
0187 /**
0188  *  ucb1x00_disable - disable the UCB1x00 SIB clock
0189  *  @ucb: UCB1x00 structure describing chip
0190  *
0191  *  Disable the SIB clock.  The SIB clock will only be disabled
0192  *  when the number of ucb1x00_enable calls match the number of
0193  *  ucb1x00_disable calls.
0194  */
0195 static inline void ucb1x00_disable(struct ucb1x00 *ucb)
0196 {
0197     mcp_disable(ucb->mcp);
0198 }
0199
0200 /**
0201  *  ucb1x00_reg_write - write a UCB1x00 register
0202  *  @ucb: UCB1x00 structure describing chip
0203  *  @reg: UCB1x00 4-bit register index to write
0204  *  @val: UCB1x00 16-bit value to write
0205  *
0206  *  Write the UCB1x00 register @reg with value @val.  The SIB
0207  *  clock must be running for this function to return.
0208  */
0209 static inline void ucb1x00_reg_write(struct ucb1x00 *ucb, unsigned int reg, unsigned int val)
0210 {
0211     mcp_reg_write(ucb->mcp, reg, val);
0212 }
0213
0214 /**
0215  *  ucb1x00_reg_read - read a UCB1x00 register
0216  *  @ucb: UCB1x00 structure describing chip
0217  *  @reg: UCB1x00 4-bit register index to write
0218  *
0219  *  Read the UCB1x00 register @reg and return its value.  The SIB
0220  *  clock must be running for this function to return.
0221  */
0222 static inline unsigned int ucb1x00_reg_read(struct ucb1x00 *ucb, unsigned int reg)
0223 {
0224     return mcp_reg_read(ucb->mcp, reg);
0225 }
0226 /**
0227  *  ucb1x00_set_audio_divisor -
0228  *  @ucb: UCB1x00 structure describing chip
0229  *  @div: SIB clock divisor
0230  */
0231 static inline void ucb1x00_set_audio_divisor(struct ucb1x00 *ucb, unsigned int div)
0232 {
0233     mcp_set_audio_divisor(ucb->mcp, div);
0234 }
0235
0236 /**
0237  *  ucb1x00_set_telecom_divisor -
0238  *  @ucb: UCB1x00 structure describing chip
0239  *  @div: SIB clock divisor
0240  */
0241 static inline void ucb1x00_set_telecom_divisor(struct ucb1x00 *ucb, unsigned int div)
0242 {
0243     mcp_set_telecom_divisor(ucb->mcp, div);
0244 }
0245
0246 void ucb1x00_io_set_dir(struct ucb1x00 *ucb, unsigned int, unsigned int);
0247 void ucb1x00_io_write(struct ucb1x00 *ucb, unsigned int, unsigned int);
0248 unsigned int ucb1x00_io_read(struct ucb1x00 *ucb);
0249
0250 #define UCB_NOSYNC  (0)
0251 #define UCB_SYNC    (1)
0252
0253 unsigned int ucb1x00_adc_read(struct ucb1x00 *ucb, int adc_channel, int sync);
0254 void ucb1x00_adc_enable(struct ucb1x00 *ucb);
0255 void ucb1x00_adc_disable(struct ucb1x00 *ucb);
0256
0257 #endif