linux/mfd/twl4030-audio.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * MFD driver for twl4030 audio submodule
0004  *
0005  * Author: Peter Ujfalusi <peter.ujfalusi@ti.com>
0006  *
0007  * Copyright:   (C) 2009 Nokia Corporation
0008  */
0009
0010 #ifndef __TWL4030_CODEC_H__
0011 #define __TWL4030_CODEC_H__
0012
0013 /* Codec registers */
0014 #define TWL4030_REG_CODEC_MODE      0x01
0015 #define TWL4030_REG_OPTION      0x02
0016 #define TWL4030_REG_UNKNOWN     0x03
0017 #define TWL4030_REG_MICBIAS_CTL     0x04
0018 #define TWL4030_REG_ANAMICL     0x05
0019 #define TWL4030_REG_ANAMICR     0x06
0020 #define TWL4030_REG_AVADC_CTL       0x07
0021 #define TWL4030_REG_ADCMICSEL       0x08
0022 #define TWL4030_REG_DIGMIXING       0x09
0023 #define TWL4030_REG_ATXL1PGA        0x0A
0024 #define TWL4030_REG_ATXR1PGA        0x0B
0025 #define TWL4030_REG_AVTXL2PGA       0x0C
0026 #define TWL4030_REG_AVTXR2PGA       0x0D
0027 #define TWL4030_REG_AUDIO_IF        0x0E
0028 #define TWL4030_REG_VOICE_IF        0x0F
0029 #define TWL4030_REG_ARXR1PGA        0x10
0030 #define TWL4030_REG_ARXL1PGA        0x11
0031 #define TWL4030_REG_ARXR2PGA        0x12
0032 #define TWL4030_REG_ARXL2PGA        0x13
0033 #define TWL4030_REG_VRXPGA      0x14
0034 #define TWL4030_REG_VSTPGA      0x15
0035 #define TWL4030_REG_VRX2ARXPGA      0x16
0036 #define TWL4030_REG_AVDAC_CTL       0x17
0037 #define TWL4030_REG_ARX2VTXPGA      0x18
0038 #define TWL4030_REG_ARXL1_APGA_CTL  0x19
0039 #define TWL4030_REG_ARXR1_APGA_CTL  0x1A
0040 #define TWL4030_REG_ARXL2_APGA_CTL  0x1B
0041 #define TWL4030_REG_ARXR2_APGA_CTL  0x1C
0042 #define TWL4030_REG_ATX2ARXPGA      0x1D
0043 #define TWL4030_REG_BT_IF       0x1E
0044 #define TWL4030_REG_BTPGA       0x1F
0045 #define TWL4030_REG_BTSTPGA     0x20
0046 #define TWL4030_REG_EAR_CTL     0x21
0047 #define TWL4030_REG_HS_SEL      0x22
0048 #define TWL4030_REG_HS_GAIN_SET     0x23
0049 #define TWL4030_REG_HS_POPN_SET     0x24
0050 #define TWL4030_REG_PREDL_CTL       0x25
0051 #define TWL4030_REG_PREDR_CTL       0x26
0052 #define TWL4030_REG_PRECKL_CTL      0x27
0053 #define TWL4030_REG_PRECKR_CTL      0x28
0054 #define TWL4030_REG_HFL_CTL     0x29
0055 #define TWL4030_REG_HFR_CTL     0x2A
0056 #define TWL4030_REG_ALC_CTL     0x2B
0057 #define TWL4030_REG_ALC_SET1        0x2C
0058 #define TWL4030_REG_ALC_SET2        0x2D
0059 #define TWL4030_REG_BOOST_CTL       0x2E
0060 #define TWL4030_REG_SOFTVOL_CTL     0x2F
0061 #define TWL4030_REG_DTMF_FREQSEL    0x30
0062 #define TWL4030_REG_DTMF_TONEXT1H   0x31
0063 #define TWL4030_REG_DTMF_TONEXT1L   0x32
0064 #define TWL4030_REG_DTMF_TONEXT2H   0x33
0065 #define TWL4030_REG_DTMF_TONEXT2L   0x34
0066 #define TWL4030_REG_DTMF_TONOFF     0x35
0067 #define TWL4030_REG_DTMF_WANONOFF   0x36
0068 #define TWL4030_REG_I2S_RX_SCRAMBLE_H   0x37
0069 #define TWL4030_REG_I2S_RX_SCRAMBLE_M   0x38
0070 #define TWL4030_REG_I2S_RX_SCRAMBLE_L   0x39
0071 #define TWL4030_REG_APLL_CTL        0x3A
0072 #define TWL4030_REG_DTMF_CTL        0x3B
0073 #define TWL4030_REG_DTMF_PGA_CTL2   0x3C
0074 #define TWL4030_REG_DTMF_PGA_CTL1   0x3D
0075 #define TWL4030_REG_MISC_SET_1      0x3E
0076 #define TWL4030_REG_PCMBTMUX        0x3F
0077 #define TWL4030_REG_RX_PATH_SEL     0x43
0078 #define TWL4030_REG_VDL_APGA_CTL    0x44
0079 #define TWL4030_REG_VIBRA_CTL       0x45
0080 #define TWL4030_REG_VIBRA_SET       0x46
0081 #define TWL4030_REG_VIBRA_PWM_SET   0x47
0082 #define TWL4030_REG_ANAMIC_GAIN     0x48
0083 #define TWL4030_REG_MISC_SET_2      0x49
0084
0085 /* Bitfield Definitions */
0086
0087 /* TWL4030_CODEC_MODE (0x01) Fields */
0088 #define TWL4030_APLL_RATE       0xF0
0089 #define TWL4030_APLL_RATE_8000      0x00
0090 #define TWL4030_APLL_RATE_11025     0x10
0091 #define TWL4030_APLL_RATE_12000     0x20
0092 #define TWL4030_APLL_RATE_16000     0x40
0093 #define TWL4030_APLL_RATE_22050     0x50
0094 #define TWL4030_APLL_RATE_24000     0x60
0095 #define TWL4030_APLL_RATE_32000     0x80
0096 #define TWL4030_APLL_RATE_44100     0x90
0097 #define TWL4030_APLL_RATE_48000     0xA0
0098 #define TWL4030_APLL_RATE_96000     0xE0
0099 #define TWL4030_SEL_16K         0x08
0100 #define TWL4030_CODECPDZ        0x02
0101 #define TWL4030_OPT_MODE        0x01
0102 #define TWL4030_OPTION_1        (1 << 0)
0103 #define TWL4030_OPTION_2        (0 << 0)
0104
0105 /* TWL4030_OPTION (0x02) Fields */
0106 #define TWL4030_ATXL1_EN        (1 << 0)
0107 #define TWL4030_ATXR1_EN        (1 << 1)
0108 #define TWL4030_ATXL2_VTXL_EN       (1 << 2)
0109 #define TWL4030_ATXR2_VTXR_EN       (1 << 3)
0110 #define TWL4030_ARXL1_VRX_EN        (1 << 4)
0111 #define TWL4030_ARXR1_EN        (1 << 5)
0112 #define TWL4030_ARXL2_EN        (1 << 6)
0113 #define TWL4030_ARXR2_EN        (1 << 7)
0114
0115 /* TWL4030_REG_MICBIAS_CTL (0x04) Fields */
0116 #define TWL4030_MICBIAS2_CTL        0x40
0117 #define TWL4030_MICBIAS1_CTL        0x20
0118 #define TWL4030_HSMICBIAS_EN        0x04
0119 #define TWL4030_MICBIAS2_EN     0x02
0120 #define TWL4030_MICBIAS1_EN     0x01
0121
0122 /* ANAMICL (0x05) Fields */
0123 #define TWL4030_CNCL_OFFSET_START   0x80
0124 #define TWL4030_OFFSET_CNCL_SEL     0x60
0125 #define TWL4030_OFFSET_CNCL_SEL_ARX1    0x00
0126 #define TWL4030_OFFSET_CNCL_SEL_ARX2    0x20
0127 #define TWL4030_OFFSET_CNCL_SEL_VRX 0x40
0128 #define TWL4030_OFFSET_CNCL_SEL_ALL 0x60
0129 #define TWL4030_MICAMPL_EN      0x10
0130 #define TWL4030_CKMIC_EN        0x08
0131 #define TWL4030_AUXL_EN         0x04
0132 #define TWL4030_HSMIC_EN        0x02
0133 #define TWL4030_MAINMIC_EN      0x01
0134
0135 /* ANAMICR (0x06) Fields */
0136 #define TWL4030_MICAMPR_EN      0x10
0137 #define TWL4030_AUXR_EN         0x04
0138 #define TWL4030_SUBMIC_EN       0x01
0139
0140 /* AVADC_CTL (0x07) Fields */
0141 #define TWL4030_ADCL_EN         0x08
0142 #define TWL4030_AVADC_CLK_PRIORITY  0x04
0143 #define TWL4030_ADCR_EN         0x02
0144
0145 /* TWL4030_REG_ADCMICSEL (0x08) Fields */
0146 #define TWL4030_DIGMIC1_EN      0x08
0147 #define TWL4030_TX2IN_SEL       0x04
0148 #define TWL4030_DIGMIC0_EN      0x02
0149 #define TWL4030_TX1IN_SEL       0x01
0150
0151 /* AUDIO_IF (0x0E) Fields */
0152 #define TWL4030_AIF_SLAVE_EN        0x80
0153 #define TWL4030_DATA_WIDTH      0x60
0154 #define TWL4030_DATA_WIDTH_16S_16W  0x00
0155 #define TWL4030_DATA_WIDTH_32S_16W  0x40
0156 #define TWL4030_DATA_WIDTH_32S_24W  0x60
0157 #define TWL4030_AIF_FORMAT      0x18
0158 #define TWL4030_AIF_FORMAT_CODEC    0x00
0159 #define TWL4030_AIF_FORMAT_LEFT     0x08
0160 #define TWL4030_AIF_FORMAT_RIGHT    0x10
0161 #define TWL4030_AIF_FORMAT_TDM      0x18
0162 #define TWL4030_AIF_TRI_EN      0x04
0163 #define TWL4030_CLK256FS_EN     0x02
0164 #define TWL4030_AIF_EN          0x01
0165
0166 /* VOICE_IF (0x0F) Fields */
0167 #define TWL4030_VIF_SLAVE_EN        0x80
0168 #define TWL4030_VIF_DIN_EN      0x40
0169 #define TWL4030_VIF_DOUT_EN     0x20
0170 #define TWL4030_VIF_SWAP        0x10
0171 #define TWL4030_VIF_FORMAT      0x08
0172 #define TWL4030_VIF_TRI_EN      0x04
0173 #define TWL4030_VIF_SUB_EN      0x02
0174 #define TWL4030_VIF_EN          0x01
0175
0176 /* EAR_CTL (0x21) */
0177 #define TWL4030_EAR_GAIN        0x30
0178
0179 /* HS_GAIN_SET (0x23) Fields */
0180 #define TWL4030_HSR_GAIN        0x0C
0181 #define TWL4030_HSR_GAIN_PWR_DOWN   0x00
0182 #define TWL4030_HSR_GAIN_PLUS_6DB   0x04
0183 #define TWL4030_HSR_GAIN_0DB        0x08
0184 #define TWL4030_HSR_GAIN_MINUS_6DB  0x0C
0185 #define TWL4030_HSL_GAIN        0x03
0186 #define TWL4030_HSL_GAIN_PWR_DOWN   0x00
0187 #define TWL4030_HSL_GAIN_PLUS_6DB   0x01
0188 #define TWL4030_HSL_GAIN_0DB        0x02
0189 #define TWL4030_HSL_GAIN_MINUS_6DB  0x03
0190
0191 /* HS_POPN_SET (0x24) Fields */
0192 #define TWL4030_VMID_EN         0x40
0193 #define TWL4030_EXTMUTE         0x20
0194 #define TWL4030_RAMP_DELAY      0x1C
0195 #define TWL4030_RAMP_DELAY_20MS     0x00
0196 #define TWL4030_RAMP_DELAY_40MS     0x04
0197 #define TWL4030_RAMP_DELAY_81MS     0x08
0198 #define TWL4030_RAMP_DELAY_161MS    0x0C
0199 #define TWL4030_RAMP_DELAY_323MS    0x10
0200 #define TWL4030_RAMP_DELAY_645MS    0x14
0201 #define TWL4030_RAMP_DELAY_1291MS   0x18
0202 #define TWL4030_RAMP_DELAY_2581MS   0x1C
0203 #define TWL4030_RAMP_EN         0x02
0204
0205 /* PREDL_CTL (0x25) */
0206 #define TWL4030_PREDL_GAIN      0x30
0207
0208 /* PREDR_CTL (0x26) */
0209 #define TWL4030_PREDR_GAIN      0x30
0210
0211 /* PRECKL_CTL (0x27) */
0212 #define TWL4030_PRECKL_GAIN     0x30
0213
0214 /* PRECKR_CTL (0x28) */
0215 #define TWL4030_PRECKR_GAIN     0x30
0216
0217 /* HFL_CTL (0x29, 0x2A) Fields */
0218 #define TWL4030_HF_CTL_HB_EN        0x04
0219 #define TWL4030_HF_CTL_LOOP_EN      0x08
0220 #define TWL4030_HF_CTL_RAMP_EN      0x10
0221 #define TWL4030_HF_CTL_REF_EN       0x20
0222
0223 /* APLL_CTL (0x3A) Fields */
0224 #define TWL4030_APLL_EN         0x10
0225 #define TWL4030_APLL_INFREQ     0x0F
0226 #define TWL4030_APLL_INFREQ_19200KHZ    0x05
0227 #define TWL4030_APLL_INFREQ_26000KHZ    0x06
0228 #define TWL4030_APLL_INFREQ_38400KHZ    0x0F
0229
0230 /* REG_MISC_SET_1 (0x3E) Fields */
0231 #define TWL4030_CLK64_EN        0x80
0232 #define TWL4030_SCRAMBLE_EN     0x40
0233 #define TWL4030_FMLOOP_EN       0x20
0234 #define TWL4030_SMOOTH_ANAVOL_EN    0x02
0235 #define TWL4030_DIGMIC_LR_SWAP_EN   0x01
0236
0237 /* VIBRA_CTL (0x45) */
0238 #define TWL4030_VIBRA_EN        0x01
0239 #define TWL4030_VIBRA_DIR       0x02
0240 #define TWL4030_VIBRA_AUDIO_SEL_L1  (0x00 << 2)
0241 #define TWL4030_VIBRA_AUDIO_SEL_R1  (0x01 << 2)
0242 #define TWL4030_VIBRA_AUDIO_SEL_L2  (0x02 << 2)
0243 #define TWL4030_VIBRA_AUDIO_SEL_R2  (0x03 << 2)
0244 #define TWL4030_VIBRA_SEL       0x10
0245 #define TWL4030_VIBRA_DIR_SEL       0x20
0246
0247 /* TWL4030 codec resource IDs */
0248 enum twl4030_audio_res {
0249     TWL4030_AUDIO_RES_POWER = 0,
0250     TWL4030_AUDIO_RES_APLL,
0251     TWL4030_AUDIO_RES_MAX,
0252 };
0253
0254 int twl4030_audio_disable_resource(enum twl4030_audio_res id);
0255 int twl4030_audio_enable_resource(enum twl4030_audio_res id);
0256 unsigned int twl4030_audio_get_mclk(void);
0257
0258 #endif  /* End of __TWL4030_CODEC_H__ */