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0005 #ifndef __LINUX_MFD_TPS68470_H
0006 #define __LINUX_MFD_TPS68470_H
0007
0008
0009 #define TPS68470_REG_POSTDIV2 0x06
0010 #define TPS68470_REG_BOOSTDIV 0x07
0011 #define TPS68470_REG_BUCKDIV 0x08
0012 #define TPS68470_REG_PLLSWR 0x09
0013 #define TPS68470_REG_XTALDIV 0x0A
0014 #define TPS68470_REG_PLLDIV 0x0B
0015 #define TPS68470_REG_POSTDIV 0x0C
0016 #define TPS68470_REG_PLLCTL 0x0D
0017 #define TPS68470_REG_PLLCTL2 0x0E
0018 #define TPS68470_REG_CLKCFG1 0x0F
0019 #define TPS68470_REG_CLKCFG2 0x10
0020 #define TPS68470_REG_GPCTL0A 0x14
0021 #define TPS68470_REG_GPCTL0B 0x15
0022 #define TPS68470_REG_GPCTL1A 0x16
0023 #define TPS68470_REG_GPCTL1B 0x17
0024 #define TPS68470_REG_GPCTL2A 0x18
0025 #define TPS68470_REG_GPCTL2B 0x19
0026 #define TPS68470_REG_GPCTL3A 0x1A
0027 #define TPS68470_REG_GPCTL3B 0x1B
0028 #define TPS68470_REG_GPCTL4A 0x1C
0029 #define TPS68470_REG_GPCTL4B 0x1D
0030 #define TPS68470_REG_GPCTL5A 0x1E
0031 #define TPS68470_REG_GPCTL5B 0x1F
0032 #define TPS68470_REG_GPCTL6A 0x20
0033 #define TPS68470_REG_GPCTL6B 0x21
0034 #define TPS68470_REG_SGPO 0x22
0035 #define TPS68470_REG_GPDI 0x26
0036 #define TPS68470_REG_GPDO 0x27
0037 #define TPS68470_REG_VCMVAL 0x3C
0038 #define TPS68470_REG_VAUX1VAL 0x3D
0039 #define TPS68470_REG_VAUX2VAL 0x3E
0040 #define TPS68470_REG_VIOVAL 0x3F
0041 #define TPS68470_REG_VSIOVAL 0x40
0042 #define TPS68470_REG_VAVAL 0x41
0043 #define TPS68470_REG_VDVAL 0x42
0044 #define TPS68470_REG_S_I2C_CTL 0x43
0045 #define TPS68470_REG_VCMCTL 0x44
0046 #define TPS68470_REG_VAUX1CTL 0x45
0047 #define TPS68470_REG_VAUX2CTL 0x46
0048 #define TPS68470_REG_VACTL 0x47
0049 #define TPS68470_REG_VDCTL 0x48
0050 #define TPS68470_REG_RESET 0x50
0051 #define TPS68470_REG_REVID 0xFF
0052
0053 #define TPS68470_REG_MAX TPS68470_REG_REVID
0054
0055
0056
0057 #define TPS68470_REG_RESET_MASK GENMASK(7, 0)
0058 #define TPS68470_VAVAL_AVOLT_MASK GENMASK(6, 0)
0059
0060 #define TPS68470_VDVAL_DVOLT_MASK GENMASK(5, 0)
0061 #define TPS68470_VCMVAL_VCVOLT_MASK GENMASK(6, 0)
0062 #define TPS68470_VIOVAL_IOVOLT_MASK GENMASK(6, 0)
0063 #define TPS68470_VSIOVAL_IOVOLT_MASK GENMASK(6, 0)
0064 #define TPS68470_VAUX1VAL_AUX1VOLT_MASK GENMASK(6, 0)
0065 #define TPS68470_VAUX2VAL_AUX2VOLT_MASK GENMASK(6, 0)
0066
0067 #define TPS68470_VACTL_EN_MASK GENMASK(0, 0)
0068 #define TPS68470_VDCTL_EN_MASK GENMASK(0, 0)
0069 #define TPS68470_VCMCTL_EN_MASK GENMASK(0, 0)
0070 #define TPS68470_S_I2C_CTL_EN_MASK GENMASK(1, 0)
0071 #define TPS68470_VAUX1CTL_EN_MASK GENMASK(0, 0)
0072 #define TPS68470_VAUX2CTL_EN_MASK GENMASK(0, 0)
0073 #define TPS68470_PLL_EN_MASK GENMASK(0, 0)
0074
0075 #define TPS68470_CLKCFG1_MODE_A_MASK GENMASK(1, 0)
0076 #define TPS68470_CLKCFG1_MODE_B_MASK GENMASK(3, 2)
0077
0078 #define TPS68470_CLKCFG2_DRV_STR_2MA 0x05
0079 #define TPS68470_PLL_OUTPUT_ENABLE 0x02
0080 #define TPS68470_CLK_SRC_XTAL BIT(0)
0081 #define TPS68470_PLLSWR_DEFAULT GENMASK(1, 0)
0082 #define TPS68470_OSC_EXT_CAP_DEFAULT 0x05
0083
0084 #define TPS68470_OUTPUT_A_SHIFT 0x00
0085 #define TPS68470_OUTPUT_B_SHIFT 0x02
0086 #define TPS68470_CLK_SRC_SHIFT GENMASK(2, 0)
0087 #define TPS68470_OSC_EXT_CAP_SHIFT BIT(2)
0088
0089 #define TPS68470_GPIO_CTL_REG_A(x) (TPS68470_REG_GPCTL0A + (x) * 2)
0090 #define TPS68470_GPIO_CTL_REG_B(x) (TPS68470_REG_GPCTL0B + (x) * 2)
0091 #define TPS68470_GPIO_MODE_MASK GENMASK(1, 0)
0092 #define TPS68470_GPIO_MODE_IN 0
0093 #define TPS68470_GPIO_MODE_IN_PULLUP 1
0094 #define TPS68470_GPIO_MODE_OUT_CMOS 2
0095 #define TPS68470_GPIO_MODE_OUT_ODRAIN 3
0096
0097 #endif