linux/mfd/tmio.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 #ifndef MFD_TMIO_H
0003 #define MFD_TMIO_H
0004
0005 #include <linux/device.h>
0006 #include <linux/fb.h>
0007 #include <linux/io.h>
0008 #include <linux/jiffies.h>
0009 #include <linux/mmc/card.h>
0010 #include <linux/platform_device.h>
0011 #include <linux/pm_runtime.h>
0012
0013 #define tmio_ioread8(addr) readb(addr)
0014 #define tmio_ioread16(addr) readw(addr)
0015 #define tmio_ioread16_rep(r, b, l) readsw(r, b, l)
0016 #define tmio_ioread32(addr) \
0017     (((u32)readw((addr))) | (((u32)readw((addr) + 2)) << 16))
0018
0019 #define tmio_iowrite8(val, addr) writeb((val), (addr))
0020 #define tmio_iowrite16(val, addr) writew((val), (addr))
0021 #define tmio_iowrite16_rep(r, b, l) writesw(r, b, l)
0022 #define tmio_iowrite32(val, addr) \
0023     do { \
0024         writew((val),       (addr)); \
0025         writew((val) >> 16, (addr) + 2); \
0026     } while (0)
0027
0028 #define sd_config_write8(base, shift, reg, val) \
0029     tmio_iowrite8((val), (base) + ((reg) << (shift)))
0030 #define sd_config_write16(base, shift, reg, val) \
0031     tmio_iowrite16((val), (base) + ((reg) << (shift)))
0032 #define sd_config_write32(base, shift, reg, val) \
0033     do { \
0034         tmio_iowrite16((val), (base) + ((reg) << (shift)));   \
0035         tmio_iowrite16((val) >> 16, (base) + ((reg + 2) << (shift))); \
0036     } while (0)
0037
0038 /* tmio MMC platform flags */
0039 /*
0040  * Some controllers can support a 2-byte block size when the bus width
0041  * is configured in 4-bit mode.
0042  */
0043 #define TMIO_MMC_BLKSZ_2BYTES       BIT(1)
0044 /*
0045  * Some controllers can support SDIO IRQ signalling.
0046  */
0047 #define TMIO_MMC_SDIO_IRQ       BIT(2)
0048
0049 /* Some features are only available or tested on R-Car Gen2 or later */
0050 #define TMIO_MMC_MIN_RCAR2      BIT(3)
0051
0052 /*
0053  * Some controllers require waiting for the SD bus to become
0054  * idle before writing to some registers.
0055  */
0056 #define TMIO_MMC_HAS_IDLE_WAIT      BIT(4)
0057
0058 /*
0059  * Use the busy timeout feature. Probably all TMIO versions support it. Yet,
0060  * we don't have documentation for old variants, so we enable only known good
0061  * variants with this flag. Can be removed once all variants are known good.
0062  */
0063 #define TMIO_MMC_USE_BUSY_TIMEOUT   BIT(5)
0064
0065 /*
0066  * Some controllers have CMD12 automatically
0067  * issue/non-issue register
0068  */
0069 #define TMIO_MMC_HAVE_CMD12_CTRL    BIT(7)
0070
0071 /* Controller has some SDIO status bits which must be 1 */
0072 #define TMIO_MMC_SDIO_STATUS_SETBITS    BIT(8)
0073
0074 /*
0075  * Some controllers have a 32-bit wide data port register
0076  */
0077 #define TMIO_MMC_32BIT_DATA_PORT    BIT(9)
0078
0079 /*
0080  * Some controllers allows to set SDx actual clock
0081  */
0082 #define TMIO_MMC_CLK_ACTUAL     BIT(10)
0083
0084 /* Some controllers have a CBSY bit */
0085 #define TMIO_MMC_HAVE_CBSY      BIT(11)
0086
0087 int tmio_core_mmc_enable(void __iomem *cnf, int shift, unsigned long base);
0088 int tmio_core_mmc_resume(void __iomem *cnf, int shift, unsigned long base);
0089 void tmio_core_mmc_pwr(void __iomem *cnf, int shift, int state);
0090 void tmio_core_mmc_clk_div(void __iomem *cnf, int shift, int state);
0091
0092 struct dma_chan;
0093
0094 /*
0095  * data for the MMC controller
0096  */
0097 struct tmio_mmc_data {
0098     void                *chan_priv_tx;
0099     void                *chan_priv_rx;
0100     unsigned int            hclk;
0101     unsigned long           capabilities;
0102     unsigned long           capabilities2;
0103     unsigned long           flags;
0104     u32             ocr_mask;   /* available voltages */
0105     int             alignment_shift;
0106     dma_addr_t          dma_rx_offset;
0107     unsigned int            max_blk_count;
0108     unsigned short          max_segs;
0109     void (*set_pwr)(struct platform_device *host, int state);
0110     void (*set_clk_div)(struct platform_device *host, int state);
0111 };
0112
0113 /*
0114  * data for the NAND controller
0115  */
0116 struct tmio_nand_data {
0117     struct nand_bbt_descr   *badblock_pattern;
0118     struct mtd_partition    *partition;
0119     unsigned int        num_partitions;
0120     const char *const   *part_parsers;
0121 };
0122
0123 #define FBIO_TMIO_ACC_WRITE 0x7C639300
0124 #define FBIO_TMIO_ACC_SYNC  0x7C639301
0125
0126 struct tmio_fb_data {
0127     int         (*lcd_set_power)(struct platform_device *fb_dev,
0128                          bool on);
0129     int         (*lcd_mode)(struct platform_device *fb_dev,
0130                         const struct fb_videomode *mode);
0131     int         num_modes;
0132     struct fb_videomode *modes;
0133
0134     /* in mm: size of screen */
0135     int         height;
0136     int         width;
0137 };
0138
0139 #endif