linux/mfd/ti_am335x_tscadc.h

0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /*
0003  * TI Touch Screen / ADC MFD driver
0004  *
0005  * Copyright (C) 2012 Texas Instruments Incorporated - https://www.ti.com/
0006  */
0007
0008 #ifndef __LINUX_TI_AM335X_TSCADC_MFD_H
0009 #define __LINUX_TI_AM335X_TSCADC_MFD_H
0010
0011 #include <linux/bitfield.h>
0012 #include <linux/mfd/core.h>
0013 #include <linux/units.h>
0014
0015 #define REG_RAWIRQSTATUS    0x024
0016 #define REG_IRQSTATUS       0x028
0017 #define REG_IRQENABLE       0x02C
0018 #define REG_IRQCLR      0x030
0019 #define REG_IRQWAKEUP       0x034
0020 #define REG_DMAENABLE_SET   0x038
0021 #define REG_DMAENABLE_CLEAR 0x03c
0022 #define REG_CTRL        0x040
0023 #define REG_ADCFSM      0x044
0024 #define REG_CLKDIV      0x04C
0025 #define REG_SE          0x054
0026 #define REG_IDLECONFIG      0x058
0027 #define REG_CHARGECONFIG    0x05C
0028 #define REG_CHARGEDELAY     0x060
0029 #define REG_STEPCONFIG(n)   (0x64 + ((n) * 8))
0030 #define REG_STEPDELAY(n)    (0x68 + ((n) * 8))
0031 #define REG_FIFO0CNT        0xE4
0032 #define REG_FIFO0THR        0xE8
0033 #define REG_FIFO1CNT        0xF0
0034 #define REG_FIFO1THR        0xF4
0035 #define REG_DMA1REQ     0xF8
0036 #define REG_FIFO0       0x100
0037 #define REG_FIFO1       0x200
0038
0039 /*  Register Bitfields  */
0040 /* IRQ wakeup enable */
0041 #define IRQWKUP_ENB     BIT(0)
0042
0043 /* IRQ enable */
0044 #define IRQENB_HW_PEN       BIT(0)
0045 #define IRQENB_EOS      BIT(1)
0046 #define IRQENB_FIFO0THRES   BIT(2)
0047 #define IRQENB_FIFO0OVRRUN  BIT(3)
0048 #define IRQENB_FIFO0UNDRFLW BIT(4)
0049 #define IRQENB_FIFO1THRES   BIT(5)
0050 #define IRQENB_FIFO1OVRRUN  BIT(6)
0051 #define IRQENB_FIFO1UNDRFLW BIT(7)
0052 #define IRQENB_PENUP        BIT(9)
0053
0054 /* Step Configuration */
0055 #define STEPCONFIG_MODE(val)    FIELD_PREP(GENMASK(1, 0), (val))
0056 #define STEPCONFIG_MODE_SWCNT   STEPCONFIG_MODE(1)
0057 #define STEPCONFIG_MODE_HWSYNC  STEPCONFIG_MODE(2)
0058 #define STEPCONFIG_AVG(val) FIELD_PREP(GENMASK(4, 2), (val))
0059 #define STEPCONFIG_AVG_16   STEPCONFIG_AVG(4)
0060 #define STEPCONFIG_XPP      BIT(5)
0061 #define STEPCONFIG_XNN      BIT(6)
0062 #define STEPCONFIG_YPP      BIT(7)
0063 #define STEPCONFIG_YNN      BIT(8)
0064 #define STEPCONFIG_XNP      BIT(9)
0065 #define STEPCONFIG_YPN      BIT(10)
0066 #define STEPCONFIG_RFP(val) FIELD_PREP(GENMASK(13, 12), (val))
0067 #define STEPCONFIG_RFP_VREFP    STEPCONFIG_RFP(3)
0068 #define STEPCONFIG_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
0069 #define STEPCONFIG_INM_ADCREFM  STEPCONFIG_INM(8)
0070 #define STEPCONFIG_INP(val) FIELD_PREP(GENMASK(22, 19), (val))
0071 #define STEPCONFIG_INP_AN4  STEPCONFIG_INP(4)
0072 #define STEPCONFIG_INP_ADCREFM  STEPCONFIG_INP(8)
0073 #define STEPCONFIG_FIFO1    BIT(26)
0074 #define STEPCONFIG_RFM(val) FIELD_PREP(GENMASK(24, 23), (val))
0075 #define STEPCONFIG_RFM_VREFN    STEPCONFIG_RFM(3)
0076
0077 /* Delay register */
0078 #define STEPDELAY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))
0079 #define STEPCONFIG_OPENDLY  STEPDELAY_OPEN(0x098)
0080 #define STEPCONFIG_MAX_OPENDLY  GENMASK(17, 0)
0081 #define STEPDELAY_SAMPLE(val)   FIELD_PREP(GENMASK(31, 24), (val))
0082 #define STEPCONFIG_SAMPLEDLY    STEPDELAY_SAMPLE(0)
0083 #define STEPCONFIG_MAX_SAMPLE   GENMASK(7, 0)
0084
0085 /* Charge Config */
0086 #define STEPCHARGE_RFP(val) FIELD_PREP(GENMASK(14, 12), (val))
0087 #define STEPCHARGE_RFP_XPUL STEPCHARGE_RFP(1)
0088 #define STEPCHARGE_INM(val) FIELD_PREP(GENMASK(18, 15), (val))
0089 #define STEPCHARGE_INM_AN1  STEPCHARGE_INM(1)
0090 #define STEPCHARGE_INP(val) FIELD_PREP(GENMASK(22, 19), (val))
0091 #define STEPCHARGE_RFM(val) FIELD_PREP(GENMASK(24, 23), (val))
0092 #define STEPCHARGE_RFM_XNUR STEPCHARGE_RFM(1)
0093
0094 /* Charge delay */
0095 #define CHARGEDLY_OPEN(val) FIELD_PREP(GENMASK(17, 0), (val))
0096 #define CHARGEDLY_OPENDLY   CHARGEDLY_OPEN(0x400)
0097
0098 /* Control register */
0099 #define CNTRLREG_SSENB      BIT(0)
0100 #define CNTRLREG_STEPID     BIT(1)
0101 #define CNTRLREG_TSC_STEPCONFIGWRT BIT(2)
0102 #define CNTRLREG_POWERDOWN  BIT(4)
0103 #define CNTRLREG_TSC_AFE_CTRL(val) FIELD_PREP(GENMASK(6, 5), (val))
0104 #define CNTRLREG_TSC_4WIRE  CNTRLREG_TSC_AFE_CTRL(1)
0105 #define CNTRLREG_TSC_5WIRE  CNTRLREG_TSC_AFE_CTRL(2)
0106 #define CNTRLREG_TSC_ENB    BIT(7)
0107
0108 /*Control registers bitfields  for MAGADC IP */
0109 #define CNTRLREG_MAGADCENB      BIT(0)
0110 #define CNTRLREG_MAG_PREAMP_PWRDOWN BIT(5)
0111 #define CNTRLREG_MAG_PREAMP_BYPASS  BIT(6)
0112
0113 /* FIFO READ Register */
0114 #define FIFOREAD_DATA_MASK  GENMASK(11, 0)
0115 #define FIFOREAD_CHNLID_MASK    GENMASK(19, 16)
0116
0117 /* DMA ENABLE/CLEAR Register */
0118 #define DMA_FIFO0       BIT(0)
0119 #define DMA_FIFO1       BIT(1)
0120
0121 /* Sequencer Status */
0122 #define SEQ_STATUS      BIT(5)
0123 #define CHARGE_STEP     0x11
0124
0125 #define TSC_ADC_CLK     (3 * HZ_PER_MHZ)
0126 #define MAG_ADC_CLK     (13 * HZ_PER_MHZ)
0127 #define TOTAL_STEPS     16
0128 #define TOTAL_CHANNELS      8
0129 #define FIFO1_THRESHOLD     19
0130
0131 /*
0132  * time in us for processing a single channel, calculated as follows:
0133  *
0134  * max num cycles = open delay + (sample delay + conv time) * averaging
0135  *
0136  * max num cycles: 262143 + (255 + 13) * 16 = 266431
0137  *
0138  * clock frequency: 26MHz / 8 = 3.25MHz
0139  * clock period: 1 / 3.25MHz = 308ns
0140  *
0141  * max processing time: 266431 * 308ns = 83ms(approx)
0142  */
0143 #define IDLE_TIMEOUT_MS     83 /* milliseconds */
0144
0145 #define TSCADC_CELLS        2
0146
0147 struct ti_tscadc_data {
0148     char *adc_feature_name;
0149     char *adc_feature_compatible;
0150     char *secondary_feature_name;
0151     char *secondary_feature_compatible;
0152     unsigned int target_clk_rate;
0153 };
0154
0155 struct ti_tscadc_dev {
0156     struct device *dev;
0157     struct regmap *regmap;
0158     void __iomem *tscadc_base;
0159     phys_addr_t tscadc_phys_base;
0160     const struct ti_tscadc_data *data;
0161     int irq;
0162     struct mfd_cell cells[TSCADC_CELLS];
0163     u32 ctrl;
0164     u32 reg_se_cache;
0165     bool adc_waiting;
0166     bool adc_in_use;
0167     wait_queue_head_t reg_se_wait;
0168     spinlock_t reg_lock;
0169     unsigned int clk_div;
0170
0171     /* tsc device */
0172     struct titsc *tsc;
0173
0174     /* adc device */
0175     struct adc_device *adc;
0176 };
0177
0178 static inline struct ti_tscadc_dev *ti_tscadc_dev_get(struct platform_device *p)
0179 {
0180     struct ti_tscadc_dev **tscadc_dev = p->dev.platform_data;
0181
0182     return *tscadc_dev;
0183 }
0184
0185 static inline bool ti_adc_with_touchscreen(struct ti_tscadc_dev *tscadc)
0186 {
0187     return of_device_is_compatible(tscadc->dev->of_node,
0188                        "ti,am3359-tscadc");
0189 }
0190
0191 void am335x_tsc_se_set_cache(struct ti_tscadc_dev *tsadc, u32 val);
0192 void am335x_tsc_se_set_once(struct ti_tscadc_dev *tsadc, u32 val);
0193 void am335x_tsc_se_clr(struct ti_tscadc_dev *tsadc, u32 val);
0194 void am335x_tsc_se_adc_done(struct ti_tscadc_dev *tsadc);
0195
0196 #endif