mfd/syscon/atmel-mc.h

0001 /* SPDX-License-Identifier: GPL-2.0+ */
0002 /*
0003  * Copyright (C) 2005 Ivan Kokshaysky
0004  * Copyright (C) SAN People
0005  *
0006  * Memory Controllers (MC, EBI, SMC, SDRAMC, BFC) - System peripherals
0007  * registers.
0008  * Based on AT91RM9200 datasheet revision E.
0009  */
0010
0011 #ifndef _LINUX_MFD_SYSCON_ATMEL_MC_H_
0012 #define _LINUX_MFD_SYSCON_ATMEL_MC_H_
0013
0014 /* Memory Controller */
0015 #define AT91_MC_RCR         0x00
0016 #define AT91_MC_RCB         BIT(0)
0017
0018 #define AT91_MC_ASR         0x04
0019 #define AT91_MC_UNADD           BIT(0)
0020 #define AT91_MC_MISADD          BIT(1)
0021 #define AT91_MC_ABTSZ           GENMASK(9, 8)
0022 #define AT91_MC_ABTSZ_BYTE      (0 << 8)
0023 #define AT91_MC_ABTSZ_HALFWORD      (1 << 8)
0024 #define AT91_MC_ABTSZ_WORD      (2 << 8)
0025 #define AT91_MC_ABTTYP          GENMASK(11, 10)
0026 #define AT91_MC_ABTTYP_DATAREAD     (0 << 10)
0027 #define AT91_MC_ABTTYP_DATAWRITE    (1 << 10)
0028 #define AT91_MC_ABTTYP_FETCH        (2 << 10)
0029 #define AT91_MC_MST(n)          BIT(16 + (n))
0030 #define AT91_MC_SVMST(n)        BIT(24 + (n))
0031
0032 #define AT91_MC_AASR            0x08
0033
0034 #define AT91_MC_MPR         0x0c
0035 #define AT91_MPR_MSTP(n)        GENMASK(2 + ((x) * 4), ((x) * 4))
0036
0037 /* External Bus Interface (EBI) registers */
0038 #define AT91_MC_EBI_CSA         0x60
0039 #define AT91_MC_EBI_CS(n)       BIT(x)
0040 #define AT91_MC_EBI_NUM_CS      8
0041
0042 #define AT91_MC_EBI_CFGR        0x64
0043 #define AT91_MC_EBI_DBPUC       BIT(0)
0044
0045 /* Static Memory Controller (SMC) registers */
0046 #define AT91_MC_SMC_CSR(n)      (0x70 + ((n) * 4))
0047 #define AT91_MC_SMC_NWS         GENMASK(6, 0)
0048 #define AT91_MC_SMC_NWS_(x)     ((x) << 0)
0049 #define AT91_MC_SMC_WSEN        BIT(7)
0050 #define AT91_MC_SMC_TDF         GENMASK(11, 8)
0051 #define AT91_MC_SMC_TDF_(x)     ((x) << 8)
0052 #define AT91_MC_SMC_TDF_MAX     0xf
0053 #define AT91_MC_SMC_BAT         BIT(12)
0054 #define AT91_MC_SMC_DBW         GENMASK(14, 13)
0055 #define AT91_MC_SMC_DBW_16      (1 << 13)
0056 #define AT91_MC_SMC_DBW_8       (2 << 13)
0057 #define AT91_MC_SMC_DPR         BIT(15)
0058 #define AT91_MC_SMC_ACSS        GENMASK(17, 16)
0059 #define AT91_MC_SMC_ACSS_(x)        ((x) << 16)
0060 #define AT91_MC_SMC_ACSS_MAX        3
0061 #define AT91_MC_SMC_RWSETUP     GENMASK(26, 24)
0062 #define AT91_MC_SMC_RWSETUP_(x)     ((x) << 24)
0063 #define AT91_MC_SMC_RWHOLD      GENMASK(30, 28)
0064 #define AT91_MC_SMC_RWHOLD_(x)      ((x) << 28)
0065 #define AT91_MC_SMC_RWHOLDSETUP_MAX 7
0066
0067 /* SDRAM Controller registers */
0068 #define AT91_MC_SDRAMC_MR       0x90
0069 #define AT91_MC_SDRAMC_MODE     GENMASK(3, 0)
0070 #define AT91_MC_SDRAMC_MODE_NORMAL  (0 << 0)
0071 #define AT91_MC_SDRAMC_MODE_NOP     (1 << 0)
0072 #define AT91_MC_SDRAMC_MODE_PRECHARGE   (2 << 0)
0073 #define AT91_MC_SDRAMC_MODE_LMR     (3 << 0)
0074 #define AT91_MC_SDRAMC_MODE_REFRESH (4 << 0)
0075 #define AT91_MC_SDRAMC_DBW_16       BIT(4)
0076
0077 #define AT91_MC_SDRAMC_TR       0x94
0078 #define AT91_MC_SDRAMC_COUNT        GENMASK(11, 0)
0079
0080 #define AT91_MC_SDRAMC_CR       0x98
0081 #define AT91_MC_SDRAMC_NC       GENMASK(1, 0)
0082 #define AT91_MC_SDRAMC_NC_8     (0 << 0)
0083 #define AT91_MC_SDRAMC_NC_9     (1 << 0)
0084 #define AT91_MC_SDRAMC_NC_10        (2 << 0)
0085 #define AT91_MC_SDRAMC_NC_11        (3 << 0)
0086 #define AT91_MC_SDRAMC_NR       GENMASK(3, 2)
0087 #define AT91_MC_SDRAMC_NR_11        (0 << 2)
0088 #define AT91_MC_SDRAMC_NR_12        (1 << 2)
0089 #define AT91_MC_SDRAMC_NR_13        (2 << 2)
0090 #define AT91_MC_SDRAMC_NB       BIT(4)
0091 #define AT91_MC_SDRAMC_NB_2     (0 << 4)
0092 #define AT91_MC_SDRAMC_NB_4     (1 << 4)
0093 #define AT91_MC_SDRAMC_CAS      GENMASK(6, 5)
0094 #define AT91_MC_SDRAMC_CAS_2        (2 << 5)
0095 #define AT91_MC_SDRAMC_TWR      GENMASK(10,  7)
0096 #define AT91_MC_SDRAMC_TRC      GENMASK(14, 11)
0097 #define AT91_MC_SDRAMC_TRP      GENMASK(18, 15)
0098 #define AT91_MC_SDRAMC_TRCD     GENMASK(22, 19)
0099 #define AT91_MC_SDRAMC_TRAS     GENMASK(26, 23)
0100 #define AT91_MC_SDRAMC_TXSR     GENMASK(30, 27)
0101
0102 #define AT91_MC_SDRAMC_SRR      0x9c
0103 #define AT91_MC_SDRAMC_SRCB     BIT(0)
0104
0105 #define AT91_MC_SDRAMC_LPR      0xa0
0106 #define AT91_MC_SDRAMC_LPCB     BIT(0)
0107
0108 #define AT91_MC_SDRAMC_IER      0xa4
0109 #define AT91_MC_SDRAMC_IDR      0xa8
0110 #define AT91_MC_SDRAMC_IMR      0xac
0111 #define AT91_MC_SDRAMC_ISR      0xb0
0112 #define AT91_MC_SDRAMC_RES      BIT(0)
0113
0114 /* Burst Flash Controller register */
0115 #define AT91_MC_BFC_MR          0xc0
0116 #define AT91_MC_BFC_BFCOM       GENMASK(1, 0)
0117 #define AT91_MC_BFC_BFCOM_DISABLED  (0 << 0)
0118 #define AT91_MC_BFC_BFCOM_ASYNC     (1 << 0)
0119 #define AT91_MC_BFC_BFCOM_BURST     (2 << 0)
0120 #define AT91_MC_BFC_BFCC        GENMASK(3, 2)
0121 #define AT91_MC_BFC_BFCC_MCK        (1 << 2)
0122 #define AT91_MC_BFC_BFCC_DIV2       (2 << 2)
0123 #define AT91_MC_BFC_BFCC_DIV4       (3 << 2)
0124 #define AT91_MC_BFC_AVL         GENMASK(7,  4)
0125 #define AT91_MC_BFC_PAGES       GENMASK(10, 8)
0126 #define AT91_MC_BFC_PAGES_NO_PAGE   (0 << 8)
0127 #define AT91_MC_BFC_PAGES_16        (1 << 8)
0128 #define AT91_MC_BFC_PAGES_32        (2 << 8)
0129 #define AT91_MC_BFC_PAGES_64        (3 << 8)
0130 #define AT91_MC_BFC_PAGES_128       (4 << 8)
0131 #define AT91_MC_BFC_PAGES_256       (5 << 8)
0132 #define AT91_MC_BFC_PAGES_512       (6 << 8)
0133 #define AT91_MC_BFC_PAGES_1024      (7 << 8)
0134 #define AT91_MC_BFC_OEL         GENMASK(13, 12)
0135 #define AT91_MC_BFC_BAAEN       BIT(16)
0136 #define AT91_MC_BFC_BFOEH       BIT(17)
0137 #define AT91_MC_BFC_MUXEN       BIT(18)
0138 #define AT91_MC_BFC_RDYEN       BIT(19)
0139
0140 #endif /* _LINUX_MFD_SYSCON_ATMEL_MC_H_ */