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0001 /* SPDX-License-Identifier: GPL-2.0-only */
0002 /* Header of ADC MFD core driver for sunxi platforms
0003  *
0004  * Copyright (c) 2016 Quentin Schulz <quentin.schulz@free-electrons.com>
0005  */
0006 
0007 #ifndef __SUN4I_GPADC__H__
0008 #define __SUN4I_GPADC__H__
0009 
0010 #define SUN4I_GPADC_CTRL0               0x00
0011 
0012 #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY(x)      ((GENMASK(7, 0) & (x)) << 24)
0013 #define SUN4I_GPADC_CTRL0_ADC_FIRST_DLY_MODE        BIT(23)
0014 #define SUN4I_GPADC_CTRL0_ADC_CLK_SELECT        BIT(22)
0015 #define SUN4I_GPADC_CTRL0_ADC_CLK_DIVIDER(x)        ((GENMASK(1, 0) & (x)) << 20)
0016 #define SUN4I_GPADC_CTRL0_FS_DIV(x)         ((GENMASK(3, 0) & (x)) << 16)
0017 #define SUN4I_GPADC_CTRL0_T_ACQ(x)          (GENMASK(15, 0) & (x))
0018 
0019 #define SUN4I_GPADC_CTRL1               0x04
0020 
0021 #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE(x)     ((GENMASK(7, 0) & (x)) << 12)
0022 #define SUN4I_GPADC_CTRL1_STYLUS_UP_DEBOUNCE_EN     BIT(9)
0023 #define SUN4I_GPADC_CTRL1_TOUCH_PAN_CALI_EN     BIT(6)
0024 #define SUN4I_GPADC_CTRL1_TP_DUAL_EN            BIT(5)
0025 #define SUN4I_GPADC_CTRL1_TP_MODE_EN            BIT(4)
0026 #define SUN4I_GPADC_CTRL1_TP_ADC_SELECT         BIT(3)
0027 #define SUN4I_GPADC_CTRL1_ADC_CHAN_SELECT(x)        (GENMASK(2, 0) & (x))
0028 #define SUN4I_GPADC_CTRL1_ADC_CHAN_MASK         GENMASK(2, 0)
0029 
0030 /* TP_CTRL1 bits for sun6i SOCs */
0031 #define SUN6I_GPADC_CTRL1_TOUCH_PAN_CALI_EN     BIT(7)
0032 #define SUN6I_GPADC_CTRL1_TP_DUAL_EN            BIT(6)
0033 #define SUN6I_GPADC_CTRL1_TP_MODE_EN            BIT(5)
0034 #define SUN6I_GPADC_CTRL1_TP_ADC_SELECT         BIT(4)
0035 #define SUN6I_GPADC_CTRL1_ADC_CHAN_SELECT(x)        (GENMASK(3, 0) & BIT(x))
0036 #define SUN6I_GPADC_CTRL1_ADC_CHAN_MASK         GENMASK(3, 0)
0037 
0038 /* TP_CTRL1 bits for sun8i SoCs */
0039 #define SUN8I_GPADC_CTRL1_CHOP_TEMP_EN          BIT(8)
0040 #define SUN8I_GPADC_CTRL1_GPADC_CALI_EN         BIT(7)
0041 
0042 #define SUN4I_GPADC_CTRL2               0x08
0043 
0044 #define SUN4I_GPADC_CTRL2_TP_SENSITIVE_ADJUST(x)    ((GENMASK(3, 0) & (x)) << 28)
0045 #define SUN4I_GPADC_CTRL2_TP_MODE_SELECT(x)     ((GENMASK(1, 0) & (x)) << 26)
0046 #define SUN4I_GPADC_CTRL2_PRE_MEA_EN            BIT(24)
0047 #define SUN4I_GPADC_CTRL2_PRE_MEA_THRE_CNT(x)       (GENMASK(23, 0) & (x))
0048 
0049 #define SUN4I_GPADC_CTRL3               0x0c
0050 
0051 #define SUN4I_GPADC_CTRL3_FILTER_EN         BIT(2)
0052 #define SUN4I_GPADC_CTRL3_FILTER_TYPE(x)        (GENMASK(1, 0) & (x))
0053 
0054 #define SUN4I_GPADC_TPR                 0x18
0055 
0056 #define SUN4I_GPADC_TPR_TEMP_ENABLE         BIT(16)
0057 #define SUN4I_GPADC_TPR_TEMP_PERIOD(x)          (GENMASK(15, 0) & (x))
0058 
0059 #define SUN4I_GPADC_INT_FIFOC               0x10
0060 
0061 #define SUN4I_GPADC_INT_FIFOC_TEMP_IRQ_EN       BIT(18)
0062 #define SUN4I_GPADC_INT_FIFOC_TP_OVERRUN_IRQ_EN     BIT(17)
0063 #define SUN4I_GPADC_INT_FIFOC_TP_DATA_IRQ_EN        BIT(16)
0064 #define SUN4I_GPADC_INT_FIFOC_TP_DATA_XY_CHANGE     BIT(13)
0065 #define SUN4I_GPADC_INT_FIFOC_TP_FIFO_TRIG_LEVEL(x) ((GENMASK(4, 0) & (x)) << 8)
0066 #define SUN4I_GPADC_INT_FIFOC_TP_DATA_DRQ_EN        BIT(7)
0067 #define SUN4I_GPADC_INT_FIFOC_TP_FIFO_FLUSH     BIT(4)
0068 #define SUN4I_GPADC_INT_FIFOC_TP_UP_IRQ_EN      BIT(1)
0069 #define SUN4I_GPADC_INT_FIFOC_TP_DOWN_IRQ_EN        BIT(0)
0070 
0071 #define SUN4I_GPADC_INT_FIFOS               0x14
0072 
0073 #define SUN4I_GPADC_INT_FIFOS_TEMP_DATA_PENDING     BIT(18)
0074 #define SUN4I_GPADC_INT_FIFOS_FIFO_OVERRUN_PENDING  BIT(17)
0075 #define SUN4I_GPADC_INT_FIFOS_FIFO_DATA_PENDING     BIT(16)
0076 #define SUN4I_GPADC_INT_FIFOS_TP_IDLE_FLG       BIT(2)
0077 #define SUN4I_GPADC_INT_FIFOS_TP_UP_PENDING     BIT(1)
0078 #define SUN4I_GPADC_INT_FIFOS_TP_DOWN_PENDING       BIT(0)
0079 
0080 #define SUN4I_GPADC_CDAT                0x1c
0081 #define SUN4I_GPADC_TEMP_DATA               0x20
0082 #define SUN4I_GPADC_DATA                0x24
0083 
0084 #define SUN4I_GPADC_IRQ_FIFO_DATA           0
0085 #define SUN4I_GPADC_IRQ_TEMP_DATA           1
0086 
0087 /* 10s delay before suspending the IP */
0088 #define SUN4I_GPADC_AUTOSUSPEND_DELAY           10000
0089 
0090 struct sun4i_gpadc_dev {
0091     struct device           *dev;
0092     struct regmap           *regmap;
0093     struct regmap_irq_chip_data *regmap_irqc;
0094     void __iomem            *base;
0095 };
0096 
0097 #endif