linux/mfd/stmfx.h

0001 /* SPDX-License-Identifier: GPL-2.0 */
0002 /*
0003  * Copyright (C) 2019 STMicroelectronics
0004  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
0005  */
0006
0007 #ifndef MFD_STMFX_H
0008 #define MFD_STMFX_H
0009
0010 #include <linux/regmap.h>
0011
0012 /* General */
0013 #define STMFX_REG_CHIP_ID       0x00 /* R */
0014 #define STMFX_REG_FW_VERSION_MSB    0x01 /* R */
0015 #define STMFX_REG_FW_VERSION_LSB    0x02 /* R */
0016 #define STMFX_REG_SYS_CTRL      0x40 /* RW */
0017 /* IRQ output management */
0018 #define STMFX_REG_IRQ_OUT_PIN       0x41 /* RW */
0019 #define STMFX_REG_IRQ_SRC_EN        0x42 /* RW */
0020 #define STMFX_REG_IRQ_PENDING       0x08 /* R */
0021 #define STMFX_REG_IRQ_ACK       0x44 /* RW */
0022 /* GPIO management */
0023 #define STMFX_REG_IRQ_GPI_PENDING1  0x0C /* R */
0024 #define STMFX_REG_IRQ_GPI_PENDING2  0x0D /* R */
0025 #define STMFX_REG_IRQ_GPI_PENDING3  0x0E /* R */
0026 #define STMFX_REG_GPIO_STATE1       0x10 /* R */
0027 #define STMFX_REG_GPIO_STATE2       0x11 /* R */
0028 #define STMFX_REG_GPIO_STATE3       0x12 /* R */
0029 #define STMFX_REG_IRQ_GPI_SRC1      0x48 /* RW */
0030 #define STMFX_REG_IRQ_GPI_SRC2      0x49 /* RW */
0031 #define STMFX_REG_IRQ_GPI_SRC3      0x4A /* RW */
0032 #define STMFX_REG_IRQ_GPI_EVT1      0x4C /* RW */
0033 #define STMFX_REG_IRQ_GPI_EVT2      0x4D /* RW */
0034 #define STMFX_REG_IRQ_GPI_EVT3      0x4E /* RW */
0035 #define STMFX_REG_IRQ_GPI_TYPE1     0x50 /* RW */
0036 #define STMFX_REG_IRQ_GPI_TYPE2     0x51 /* RW */
0037 #define STMFX_REG_IRQ_GPI_TYPE3     0x52 /* RW */
0038 #define STMFX_REG_IRQ_GPI_ACK1      0x54 /* RW */
0039 #define STMFX_REG_IRQ_GPI_ACK2      0x55 /* RW */
0040 #define STMFX_REG_IRQ_GPI_ACK3      0x56 /* RW */
0041 #define STMFX_REG_GPIO_DIR1     0x60 /* RW */
0042 #define STMFX_REG_GPIO_DIR2     0x61 /* RW */
0043 #define STMFX_REG_GPIO_DIR3     0x62 /* RW */
0044 #define STMFX_REG_GPIO_TYPE1        0x64 /* RW */
0045 #define STMFX_REG_GPIO_TYPE2        0x65 /* RW */
0046 #define STMFX_REG_GPIO_TYPE3        0x66 /* RW */
0047 #define STMFX_REG_GPIO_PUPD1        0x68 /* RW */
0048 #define STMFX_REG_GPIO_PUPD2        0x69 /* RW */
0049 #define STMFX_REG_GPIO_PUPD3        0x6A /* RW */
0050 #define STMFX_REG_GPO_SET1      0x6C /* RW */
0051 #define STMFX_REG_GPO_SET2      0x6D /* RW */
0052 #define STMFX_REG_GPO_SET3      0x6E /* RW */
0053 #define STMFX_REG_GPO_CLR1      0x70 /* RW */
0054 #define STMFX_REG_GPO_CLR2      0x71 /* RW */
0055 #define STMFX_REG_GPO_CLR3      0x72 /* RW */
0056
0057 #define STMFX_REG_MAX           0xB0
0058
0059 /* MFX boot time is around 10ms, so after reset, we have to wait this delay */
0060 #define STMFX_BOOT_TIME_MS 10
0061
0062 /* STMFX_REG_CHIP_ID bitfields */
0063 #define STMFX_REG_CHIP_ID_MASK      GENMASK(7, 0)
0064
0065 /* STMFX_REG_SYS_CTRL bitfields */
0066 #define STMFX_REG_SYS_CTRL_GPIO_EN  BIT(0)
0067 #define STMFX_REG_SYS_CTRL_TS_EN    BIT(1)
0068 #define STMFX_REG_SYS_CTRL_IDD_EN   BIT(2)
0069 #define STMFX_REG_SYS_CTRL_ALTGPIO_EN   BIT(3)
0070 #define STMFX_REG_SYS_CTRL_SWRST    BIT(7)
0071
0072 /* STMFX_REG_IRQ_OUT_PIN bitfields */
0073 #define STMFX_REG_IRQ_OUT_PIN_TYPE  BIT(0) /* 0-OD 1-PP */
0074 #define STMFX_REG_IRQ_OUT_PIN_POL   BIT(1) /* 0-active LOW 1-active HIGH */
0075
0076 /* STMFX_REG_IRQ_(SRC_EN/PENDING/ACK) bit shift */
0077 enum stmfx_irqs {
0078     STMFX_REG_IRQ_SRC_EN_GPIO = 0,
0079     STMFX_REG_IRQ_SRC_EN_IDD,
0080     STMFX_REG_IRQ_SRC_EN_ERROR,
0081     STMFX_REG_IRQ_SRC_EN_TS_DET,
0082     STMFX_REG_IRQ_SRC_EN_TS_NE,
0083     STMFX_REG_IRQ_SRC_EN_TS_TH,
0084     STMFX_REG_IRQ_SRC_EN_TS_FULL,
0085     STMFX_REG_IRQ_SRC_EN_TS_OVF,
0086     STMFX_REG_IRQ_SRC_MAX,
0087 };
0088
0089 enum stmfx_functions {
0090     STMFX_FUNC_GPIO     = BIT(0), /* GPIO[15:0] */
0091     STMFX_FUNC_ALTGPIO_LOW  = BIT(1), /* aGPIO[3:0] */
0092     STMFX_FUNC_ALTGPIO_HIGH = BIT(2), /* aGPIO[7:4] */
0093     STMFX_FUNC_TS       = BIT(3),
0094     STMFX_FUNC_IDD      = BIT(4),
0095 };
0096
0097 /**
0098  * struct stmfx_ddata - STMFX MFD structure
0099  * @device:     device reference used for logs
0100  * @map:        register map
0101  * @vdd:        STMFX power supply
0102  * @irq_domain:     IRQ domain
0103  * @lock:       IRQ bus lock
0104  * @irq_src:        cache of IRQ_SRC_EN register for bus_lock
0105  * @bkp_sysctrl:    backup of SYS_CTRL register for suspend/resume
0106  * @bkp_irqoutpin:  backup of IRQ_OUT_PIN register for suspend/resume
0107  */
0108 struct stmfx {
0109     struct device *dev;
0110     struct regmap *map;
0111     struct regulator *vdd;
0112     int irq;
0113     struct irq_domain *irq_domain;
0114     struct mutex lock; /* IRQ bus lock */
0115     u8 irq_src;
0116 #ifdef CONFIG_PM
0117     u8 bkp_sysctrl;
0118     u8 bkp_irqoutpin;
0119 #endif
0120 };
0121
0122 int stmfx_function_enable(struct stmfx *stmfx, u32 func);
0123 int stmfx_function_disable(struct stmfx *stmfx, u32 func);
0124 #endif